diff options
Diffstat (limited to 'tests')
386 files changed, 24314 insertions, 10199 deletions
diff --git a/tests/SConscript b/tests/SConscript index 62c4d0508..38e9ae9d2 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -29,7 +29,7 @@ # Authors: Steve Reinhardt # Kevin Lim -import os +import os, signal import sys import glob from SCons.Script.SConscript import SConsEnvironment @@ -44,57 +44,115 @@ env.Tests = {} def contents(node): return file(str(node)).read() -def check_test(target, source, env): +# functions to parse return value from scons Execute()... not the same +# as wait() etc., so python built-in os funcs don't work. +def signaled(status): + return (status & 0x80) != 0; + +def signum(status): + return (status & 0x7f); + +# List of signals that indicate that we should retry the test rather +# than consider it failed. +retry_signals = (signal.SIGTERM, signal.SIGKILL, signal.SIGINT, + signal.SIGQUIT, signal.SIGHUP) + +# regular expressions of lines to ignore when diffing outputs +output_ignore_regexes = ( + '^command line:', # for stdout file + '^M5 compiled ', # for stderr file + '^M5 started ', # for stderr file + '^M5 executing on ', # for stderr file + '^Simulation complete at', # for stderr file + '^Listening for', # for stderr file + 'listening for remote gdb', # for stderr file + ) + +output_ignore_args = ' '.join(["-I '"+s+"'" for s in output_ignore_regexes]) + +output_ignore_args += ' --exclude=stats.txt --exclude=outdiff' + +def run_test(target, source, env): """Check output from running test. Targets are as follows: - target[0] : outdiff - target[1] : statsdiff - target[2] : status + target[0] : status + + Sources are: + source[0] : M5 binary + source[1] : tests/run.py script + source[2] : reference stats file """ # make sure target files are all gone for t in target: if os.path.exists(t.abspath): - Execute(Delete(t.abspath)) - # Run diff on output & ref directories to find differences. - # Exclude m5stats.txt since we will use diff-out on that. - Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' + - '-I "^command line:" ' + # for stdout file - '-I "^M5 compiled " ' + # for stderr file - '-I "^M5 started " ' + # for stderr file - '-I "^M5 executing on " ' + # for stderr file - '-I "^Simulation complete at" ' + # for stderr file - '-I "^Listening for" ' + # for stderr file - '-I "listening for remote gdb" ' + # for stderr file - '--exclude=m5stats.txt --exclude=SCCS ' + - '--exclude=${TARGETS[0].file} ' + - '> ${TARGETS[0]}', target=target, source=source), None) - print "===== Output differences =====" - print contents(target[0]) - # Run diff-out on m5stats.txt file - status = Execute(env.subst('$DIFFOUT $SOURCES > ${TARGETS[1]}', - target=target, source=source), - strfunction=None) - print "===== Statistics differences =====" - print contents(target[1]) - # Generate status file contents based on exit status of diff-out + env.Execute(Delete(t.abspath)) + + tgt_dir = os.path.dirname(str(target[0])) + + # Base command for running test. We mess around with indirectly + # referring to files via SOURCES and TARGETS so that scons can mess + # with paths all it wants to and we still get the right files. + cmd = '${SOURCES[0]} -d %s -re ${SOURCES[1]} %s' % (tgt_dir, tgt_dir) + + # Prefix test run with batch job submission command if appropriate. + # Batch command also supports timeout arg (in seconds, not minutes). + timeout = 15 * 60 # used to be a param, probably should be again + if env['BATCH']: + cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd) + + status = env.Execute(env.subst(cmd, target=target, source=source)) + if status == 0: + # M5 terminated normally. + # Run diff on output & ref directories to find differences. + # Exclude the stats file since we will use diff-out on that. + outdiff = os.path.join(tgt_dir, 'outdiff') + diffcmd = 'diff -ubr %s ${SOURCES[2].dir} %s > %s' \ + % (output_ignore_args, tgt_dir, outdiff) + env.Execute(env.subst(diffcmd, target=target, source=source)) + print "===== Output differences =====" + print contents(outdiff) + # Run diff-out on stats.txt file + statsdiff = os.path.join(tgt_dir, 'statsdiff') + diffcmd = '$DIFFOUT ${SOURCES[2]} %s > %s' \ + % (os.path.join(tgt_dir, 'stats.txt'), statsdiff) + diffcmd = env.subst(diffcmd, target=target, source=source) + status = env.Execute(diffcmd, strfunction=None) + print "===== Statistics differences =====" + print contents(statsdiff) + + else: # m5 exit status != 0 + # M5 did not terminate properly, so no need to check the output + if signaled(status): + print 'M5 terminated with signal', signum(status) + if signum(status) in retry_signals: + # Consider the test incomplete; don't create a 'status' output. + # Hand the return status to scons and let scons decide what + # to do about it (typically terminate unless run with -k). + return status + else: + print 'M5 exited with non-zero status', status + # complete but failed execution (call to exit() with non-zero + # status, SIGABORT due to assertion failure, etc.)... fall through + # and generate FAILED status as if output comparison had failed + + # Generate status file contents based on exit status of m5 or diff-out if status == 0: status_str = "passed." else: status_str = "FAILED!" - f = file(str(target[2]), 'w') - print >>f, env.subst('${TARGETS[2].dir}', target=target, source=source), \ - status_str + f = file(str(target[0]), 'w') + print >>f, tgt_dir, status_str f.close() # done return 0 -def check_test_string(target, source, env): - return env.subst("Comparing outputs in ${TARGETS[0].dir}.", +def run_test_string(target, source, env): + return env.subst("Running test in ${TARGETS[0].dir}.", target=target, source=source) -testAction = env.Action(check_test, check_test_string) +testAction = env.Action(run_test, run_test_string) def print_test(target, source, env): print '***** ' + contents(source[0]) @@ -111,14 +169,14 @@ Note: The following file(s) will not be copied. New non-standard inputs and are ignored. ''' # - reference files always needed -needed_files = set(['stdout', 'stderr', 'm5stats.txt', 'config.ini']) +needed_files = set(['simout', 'simerr', 'stats.txt', 'config.ini']) # - source files we always want to ignore known_ignores = set(['status', 'outdiff', 'statsdiff']) def update_test(target, source, env): """Update reference test outputs. - Target is phony. First two sources are the ref & new m5stats.txt + Target is phony. First two sources are the ref & new stats.txt file files, respectively. We actually copy everything in the respective directories except the status & diff output files. @@ -147,7 +205,7 @@ def update_test(target, source, env): print " Creating new file", f copyAction = Copy(os.path.join(dest_dir, f), os.path.join(src_dir, f)) copyAction.strfunction = None - Execute(copyAction) + env.Execute(copyAction) return 0 def update_test_string(target, source, env): @@ -170,35 +228,12 @@ def test_builder(env, ref_dir): def tgt(f): return os.path.join(tgt_dir, f) - ref_stats = os.path.join(ref_dir, 'm5stats.txt') - new_stats = tgt('m5stats.txt') + ref_stats = os.path.join(ref_dir, 'stats.txt') + new_stats = tgt('stats.txt') status_file = tgt('status') - # Base command for running test. We mess around with indirectly - # referring to files via SOURCES and TARGETS so that scons can - # mess with paths all it wants to and we still get the right - # files. - base_cmd = '${SOURCES[0]} -d $TARGET.dir ${SOURCES[1]} %s' % tgt_dir - # stdout and stderr files - cmd_stdout = '${TARGETS[0]}' - cmd_stderr = '${TARGETS[1]}' - - # Prefix test run with batch job submission command if appropriate. - # Output redirection is also different for batch runs. - # Batch command also supports timeout arg (in seconds, not minutes). - timeout = 15 # used to be a param, probably should be again - if env['BATCH']: - cmd = [env['BATCH_CMD'], '-t', str(timeout * 60), - '-o', cmd_stdout, '-e', cmd_stderr, base_cmd] - else: - cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr] - - env.Command([tgt('stdout'), tgt('stderr'), new_stats], - [env.M5Binary, 'run.py'], ' '.join(cmd)) - - # order of targets is important... see check_test - env.Command([tgt('outdiff'), tgt('statsdiff'), status_file], - [ref_stats, new_stats], + env.Command([status_file], + [env.M5Binary, 'run.py', ref_stats], testAction) # phony target to echo status @@ -221,13 +256,15 @@ if env['FULL_SYSTEM']: 'tsunami-simple-timing', 'tsunami-simple-atomic-dual', 'tsunami-simple-timing-dual', - 'twosys-tsunami-simple-atomic'] + 'twosys-tsunami-simple-atomic', + 'tsunami-o3', 'tsunami-o3-dual'] if env['TARGET_ISA'] == 'sparc': configs += ['t1000-simple-atomic', 't1000-simple-timing'] else: - configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest'] + configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest', + 'simple-atomic-mp', 'simple-timing-mp'] cwd = os.getcwd() os.chdir(str(Dir('.').srcdir)) diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py new file mode 100644 index 000000000..5dbfa5a8b --- /dev/null +++ b/tests/configs/tsunami-o3-dual.py @@ -0,0 +1,99 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +import FSConfig + + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + mem_side_filter_ranges=[AddrRange(0, Addr.max)] + cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] + +#cpu +cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] +#the system +system = FSConfig.makeLinuxAlphaSystem('timing') + +system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +for c in cpus: + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' + +root = Root(system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py new file mode 100644 index 000000000..ee60ea8ae --- /dev/null +++ b/tests/configs/tsunami-o3.py @@ -0,0 +1,98 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +import FSConfig + + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + mem_side_filter_ranges=[AddrRange(0, Addr.max)] + cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] + +#cpu +cpu = DerivO3CPU(cpu_id=0) +#the system +system = FSConfig.makeLinuxAlphaSystem('timing') + +system.cpu = cpu +#create the l1/l2 bus +system.toL2Bus = Bus() +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' + +root = Root(system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 60a97b97b..068fb2315 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=gzip input.log 1 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..0988daaa5 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:15:58 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 04959f23f..b3f903358 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,40 +1,36 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65739146 # Number of BTB hits -global.BPredUnit.BTBLookups 73253175 # Number of BTB lookups -global.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4205990 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70175548 # Number of conditional branches predicted -global.BPredUnit.lookups 76112488 # Number of BP lookups -global.BPredUnit.usedRAS 1692573 # Number of times the RAS was used to get a target. -host_inst_rate 185893 # Simulator instruction rate (inst/s) -host_mem_usage 223968 # Number of bytes of host memory used -host_seconds 3042.35 # Real time elapsed on the host -host_tick_rate 54375513 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 21896719 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 16284345 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 127086189 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 43192001 # Number of stores inserted to the mem dependence unit. +host_inst_rate 309694 # Simulator instruction rate (inst/s) +host_mem_usage 206028 # Number of bytes of host memory used +host_seconds 1826.17 # Real time elapsed on the host +host_tick_rate 91491135 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.165429 # Number of seconds simulated -sim_ticks 165429421500 # Number of ticks simulated +sim_seconds 0.167078 # Number of seconds simulated +sim_ticks 167078146500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 65718859 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 73181368 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76039018 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20148945 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 320950455 +system.cpu.commit.COM:committed_per_cycle.samples 322711249 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 102049912 3179.62% - 1 106118520 3306.38% - 2 36548740 1138.77% - 3 11550344 359.88% - 4 9951958 310.08% - 5 22152324 690.21% - 6 10779065 335.85% - 7 1650647 51.43% - 8 20148945 627.79% + 0 108088757 3349.40% + 1 100475751 3113.49% + 2 37367184 1157.91% + 3 9733028 301.60% + 4 10676883 330.85% + 5 22147835 686.31% + 6 13251874 410.64% + 7 3269687 101.32% + 8 17700250 548.49% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,249 +39,231 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4205367 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61707712 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.585019 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.585019 # CPI: Total CPI of All Threads +system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 114321557 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26993.890628 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3367.177206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114105250 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5838967500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 216307 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 716795 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 728344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001892 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 216307 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 37579282 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 48790.597140 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7159.473367 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37241994 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 16456482928 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008975 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 337288 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1872039 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2414804453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337288 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 1999.750000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2750 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 320.196392 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 7999 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 11000 # number of cycles access was blocked +system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 151900839 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 40273.937496 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency -system.cpu.dcache.demand_hits 151347244 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22295450428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003644 # miss rate for demand accesses -system.cpu.dcache.demand_misses 553595 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2588834 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3143148453 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003644 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553595 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 151900839 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 40273.937496 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 151347244 # number of overall hits -system.cpu.dcache.overall_miss_latency 22295450428 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003644 # miss rate for overall accesses -system.cpu.dcache.overall_misses 553595 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2588834 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3143148453 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003644 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553595 # number of overall MSHR misses +system.cpu.dcache.overall_hits 149415339 # number of overall hits +system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3182768 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 468826 # number of replacements -system.cpu.dcache.sampled_refs 472922 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 468828 # number of replacements +system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.170465 # Cycle average of tags in use -system.cpu.dcache.total_refs 151427918 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50285000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334126 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 46422286 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 645 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4161088 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 690019158 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 145191324 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123829448 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9907520 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1984 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5507398 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 163087430 # DTB accesses +system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use +system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 334123 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 163077390 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 163038163 # DTB hits -system.cpu.dtb.misses 49267 # DTB misses -system.cpu.dtb.read_accesses 122338189 # DTB read accesses +system.cpu.dtb.hits 163013880 # DTB hits +system.cpu.dtb.misses 63510 # DTB misses +system.cpu.dtb.read_accesses 122284109 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122317544 # DTB read hits -system.cpu.dtb.read_misses 20645 # DTB read misses -system.cpu.dtb.write_accesses 40749241 # DTB write accesses +system.cpu.dtb.read_hits 122260496 # DTB read hits +system.cpu.dtb.read_misses 23613 # DTB read misses +system.cpu.dtb.write_accesses 40793281 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40720619 # DTB write hits -system.cpu.dtb.write_misses 28622 # DTB write misses -system.cpu.fetch.Branches 76112488 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66025670 # Number of cache lines fetched -system.cpu.fetch.Cycles 197184214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1351502 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 699221634 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4235220 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230045 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66025670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67431719 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.113353 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 40753384 # DTB write hits +system.cpu.dtb.write_misses 39897 # DTB write misses +system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched +system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 330857976 +system.cpu.fetch.rateDist.samples 332581112 system.cpu.fetch.rateDist.min_value 0 - 0 199699470 6035.81% - 1 10371896 313.48% - 2 15863038 479.45% - 3 14602598 441.36% - 4 12358229 373.52% - 5 14818818 447.89% - 6 6010699 181.67% - 7 3341156 100.98% - 8 53792072 1625.84% + 0 201466223 6057.66% + 1 10360747 311.53% + 2 15882081 477.54% + 3 14599006 438.96% + 4 12362950 371.73% + 5 14822134 445.67% + 6 6008311 180.66% + 7 3307530 99.45% + 8 53772130 1616.81% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 66025546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 10641.352550 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6819.290466 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66024644 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 9598500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6151000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73198.053215 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66025546 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 10641.352550 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency -system.cpu.icache.demand_hits 66024644 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 9598500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_misses 902 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6151000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66025546 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 10641.352550 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency +system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66024644 # number of overall hits -system.cpu.icache.overall_miss_latency 9598500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_misses 902 # number of overall misses -system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6151000 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 66013237 # number of overall hits +system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_misses 1169 # number of overall misses +system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 32 # number of replacements +system.cpu.icache.replacements 34 # number of replacements system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.239178 # Cycle average of tags in use -system.cpu.icache.total_refs 66024644 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use +system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 868 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67336673 # Number of branches executed -system.cpu.iew.EXEC:nop 43018581 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.810881 # Inst execution rate -system.cpu.iew.EXEC:refs 164027135 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41145337 # Number of stores executed +system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67316859 # Number of branches executed +system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate +system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41189464 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 491694974 # num instructions consuming a value -system.cpu.iew.WB:count 595952322 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.808476 # average fanout of values written-back +system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value +system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 397523802 # num instructions producing a value -system.cpu.iew.WB:rate 1.801228 # insts written-back per cycle -system.cpu.iew.WB:sent 597113280 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671395 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 85472 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 127086189 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3259094 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43192001 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663707703 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122881798 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6536173 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599145915 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1317 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 395375802 # num instructions producing a value +system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle +system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9907520 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 4668 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 4162 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7269203 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 14266 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 32461 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5902 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 12036679 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3379478 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 32461 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540781 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4130614 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.709347 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.709347 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605682088 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 438760030 72.44% # Type of FU issued - IntMult 6517 0.00% # Type of FU issued + IntAlu 438834840 72.45% # Type of FU issued + IntMult 6546 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 29 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued @@ -293,17 +271,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 124950238 20.63% # Type of FU issued - MemWrite 41965260 6.93% # Type of FU issued + MemRead 124855453 20.61% # Type of FU issued + MemWrite 42021230 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6912738 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011413 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5342591 77.29% # attempts to use FU when none available - IntMult 72 0.00% # attempts to use FU when none available + IntAlu 5390831 74.54% # attempts to use FU when none available + IntMult 67 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -311,138 +289,136 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 924602 13.38% # attempts to use FU when none available - MemWrite 645473 9.34% # attempts to use FU when none available + MemRead 1490139 20.60% # attempts to use FU when none available + MemWrite 351286 4.86% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 330857976 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 90630363 2739.25% - 1 66723730 2016.69% - 2 79382589 2399.30% - 3 36274593 1096.38% - 4 32477730 981.62% - 5 12845074 388.24% - 6 10946309 330.85% - 7 1065447 32.20% - 8 512141 15.48% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.830636 # Inst issue rate -system.cpu.iq.iqInstsAdded 620689100 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605682088 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53858401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 17774 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29864580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 66025708 # ITB accesses +system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% +system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 +system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate +system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 66014446 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 66025670 # ITB hits -system.cpu.itb.misses 38 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 256615 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5221.239990 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2221.239990 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1339848500 # number of ReadExReq miss cycles +system.cpu.itb.hits 66014406 # ITB hits +system.cpu.itb.misses 40 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256615 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 570003500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256615 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217209 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5324.201615 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2324.201615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 181418 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 190558500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.164777 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83185500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164777 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35791 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80676 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5165.743220 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2166.071694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 416751500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80676 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 174750000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80676 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334126 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 334126 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.724082 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473824 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5233.842671 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 181418 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1530407000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.617119 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 292406 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 653189000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.617119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 292406 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 473824 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5233.842671 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 181418 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1530407000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.617119 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 292406 # number of overall misses +system.cpu.l2cache.overall_hits 181383 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 292443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 653189000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.617119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 292406 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 85250 # number of replacements -system.cpu.l2cache.sampled_refs 100885 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 85262 # number of replacements +system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16355.319881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 375704 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use +system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63237 # number of writebacks -system.cpu.numCycles 330858844 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 11109833 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 63236 # number of writebacks +system.cpu.memDep0.conflictingLoads 19292303 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 14732751 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 334156294 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 34908767 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 152607206 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 316634 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 896955924 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680550426 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519573186 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116670528 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9907520 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 40562533 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55718297 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 356 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 79715664 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.timesIdled 189 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr deleted file mode 100644 index 598fc86c0..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout deleted file mode 100644 index 9aaca3eeb..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,31 +0,0 @@ -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index e21c42f32..53e8ae1eb 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=gzip input.log 1 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..2a4b52a28 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py long/00.gzip/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index c668a0459..d5f13f08c 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2906348 # Simulator instruction rate (inst/s) -host_mem_usage 174252 # Number of bytes of host memory used -host_seconds 207.08 # Real time elapsed on the host -host_tick_rate 1453183573 # Simulator tick rate (ticks/s) +host_inst_rate 6175770 # Simulator instruction rate (inst/s) +host_mem_usage 195684 # Number of bytes of host memory used +host_seconds 97.45 # Real time elapsed on the host +host_tick_rate 3087904278 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100644 index f33d007a7..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100644 index 9aaca3eeb..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,31 +0,0 @@ -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 87443a024..6d294469b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=gzip input.log 1 cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..8b3b6bb5d --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py long/00.gzip/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 7a8a25a24..57d9b05f8 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1122189 # Simulator instruction rate (inst/s) -host_mem_usage 222560 # Number of bytes of host memory used -host_seconds 536.32 # Real time elapsed on the host -host_tick_rate 1430957420 # Simulator tick rate (ticks/s) +host_inst_rate 1969135 # Simulator instruction rate (inst/s) +host_mem_usage 203124 # Number of bytes of host memory used +host_seconds 305.65 # Real time elapsed on the host +host_tick_rate 2545444210 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.767457 # Number of seconds simulated -sim_ticks 767457055000 # Number of ticks simulated +sim_seconds 0.778004 # Number of seconds simulated +sim_ticks 778003833000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16196.211338 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13196.211338 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3259196000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2655500000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.984797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.984797 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8880052000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7893379000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,48 +37,39 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22898.927230 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12139248000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10548879000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22898.927230 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 12139248000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses system.cpu.dcache.overall_misses 530123 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10548879000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.918042 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 357644000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.dtb.accesses 153970296 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 39451321 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 21465000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 19080000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 21465000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 19080000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.overall_miss_latency 21465000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 19080000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.689179 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +142,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 601861898 # ITB hits system.cpu.itb.misses 20 # ITB misses system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5845749000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2795793000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 800193000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 382701000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22998.461086 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1718629000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) @@ -198,51 +180,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6645942000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3178494000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 167236 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6645942000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses system.cpu.l2cache.overall_misses 288954 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3178494000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 84513 # number of replacements system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16357.683393 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 63194 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1534914110 # number of cpu cycles simulated +system.cpu.numCycles 1556007666 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr deleted file mode 100644 index 598fc86c0..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout deleted file mode 100644 index 9aaca3eeb..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,31 +0,0 @@ -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 857d77efe..ee1f88977 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 8ee292d5b..293987f44 100644..100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:45 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1102714100000 because target called exit() +Exiting @ tick 1102659088000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index a32e8681e..3e5a615cf 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,438 +1,414 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 181883102 # Number of BTB hits -global.BPredUnit.BTBLookups 205056000 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 84375502 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted -global.BPredUnit.lookups 253548806 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 116576 # Simulator instruction rate (inst/s) -host_mem_usage 226608 # Number of bytes of host memory used -host_seconds 12057.44 # Real time elapsed on the host -host_tick_rate 91455071 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 303434180 # Number of stores inserted to the mem dependence unit. +host_inst_rate 159348 # Simulator instruction rate (inst/s) +host_mem_usage 206344 # Number of bytes of host memory used +host_seconds 8821.04 # Real time elapsed on the host +host_tick_rate 125003315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405610550 # Number of instructions simulated -sim_seconds 1.102714 # Number of seconds simulated -sim_ticks 1102714100000 # Number of ticks simulated -system.cpu.commit.COM:branches 86246390 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8144258 # number cycles where commit BW limit reached +sim_insts 1405618365 # Number of instructions simulated +sim_seconds 1.102659 # Number of seconds simulated +sim_ticks 1102659088000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 203429498 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 254458061 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 254458061 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 86248929 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 8096109 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1965947566 +system.cpu.commit.COM:committed_per_cycle.samples 1964055004 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1089819992 5543.48% - 1 575192807 2925.78% - 2 120683737 613.87% - 3 121997081 620.55% - 4 27903521 141.93% - 5 7399306 37.64% - 6 10435277 53.08% - 7 4371587 22.24% - 8 8144258 41.43% + 0 1088074201 5539.94% + 1 575643784 2930.89% + 2 120435541 613.20% + 3 120975798 615.95% + 4 27955067 142.33% + 5 8084166 41.16% + 6 10447088 53.19% + 7 4343250 22.11% + 8 8096109 41.22% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 1489528973 # Number of instructions committed -system.cpu.commit.COM:loads 402516086 # Number of loads committed +system.cpu.commit.COM:count 1489537508 # Number of instructions committed +system.cpu.commit.COM:loads 402517243 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569373868 # Number of memory references committed +system.cpu.commit.COM:refs 569375199 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 84375502 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1379622895 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405610550 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated -system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 430903803 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21506.820895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000527 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000527 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses +system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1390237652 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618365 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated +system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14297.662769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.135084 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 425346235 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13092355500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 915699 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 667386 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1685830500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 165064291 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 64362.786896 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 341979 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 37763.269313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.327068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 83930150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1192.736607 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1119.158447 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 595968094 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 47263.919107 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000955 # miss rate for demand accesses -system.cpu.dcache.demand_misses 569002 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000955 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30916.284897 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency +system.cpu.dcache.demand_hits 589980331 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97022505500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3138233 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2538011 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14382118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 595968094 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 47263.919107 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595399092 # number of overall hits -system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000955 # miss rate for overall accesses -system.cpu.dcache.overall_misses 569002 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000955 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses +system.cpu.dcache.overall_hits 589980331 # number of overall hits +system.cpu.dcache.overall_miss_latency 97022505500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3138233 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2538011 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14382118500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 495151 # number of replacements -system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 523278 # number of replacements +system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use -system.cpu.dcache.total_refs 595470173 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338813 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3446272352 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 768408181 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782722330 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239479384 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2858739 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 253548806 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 356679455 # Number of cache lines fetched -system.cpu.fetch.Cycles 1203440686 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10248277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3739797008 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 90313792 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114966 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 356679455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 181883102 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.695724 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use +system.cpu.dcache.total_refs 590215067 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 348749 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 416443317 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3435538799 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 762668513 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782001789 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239759977 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2941385 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254458061 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354588619 # Number of cache lines fetched +system.cpu.fetch.Cycles 1199300749 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10659931 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3732201000 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2205426950 +system.cpu.fetch.rateDist.samples 2203814981 system.cpu.fetch.rateDist.min_value 0 - 0 1358665764 6160.56% - 1 256941668 1165.04% - 2 81115553 367.80% - 3 38329197 173.79% - 4 87812032 398.16% - 5 41184299 186.74% - 6 30948569 140.33% - 7 20663338 93.69% - 8 289766530 1313.88% + 0 1359102894 6167.05% + 1 256500547 1163.89% + 2 81150170 368.23% + 3 38425919 174.36% + 4 85384463 387.44% + 5 41200023 186.95% + 6 32567288 147.78% + 7 20688755 93.88% + 8 288794922 1310.43% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 356679310 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9956.762749 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 354588619 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 354586492 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 263620.071693 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 257319.660377 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 356679310 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9956.762749 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency -system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 354588619 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.demand_hits 354586492 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 356679310 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9956.762749 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency +system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 356677957 # number of overall hits -system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1353 # number of overall misses -system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 354586492 # number of overall hits +system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_misses 2127 # number of overall misses +system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 208 # number of replacements -system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks. +system.cpu.icache.replacements 222 # number of replacements +system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1040.462476 # Cycle average of tags in use -system.cpu.icache.total_refs 356677957 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1057.993144 # Cycle average of tags in use +system.cpu.icache.total_refs 354586492 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1251 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 127605912 # Number of branches executed -system.cpu.iew.EXEC:nop 350340512 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.854314 # Inst execution rate -system.cpu.iew.EXEC:refs 751911003 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 205327510 # Number of stores executed +system.cpu.idleCycles 1503196 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 128154505 # Number of branches executed +system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate +system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207432555 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1480058841 # num instructions consuming a value -system.cpu.iew.WB:count 1846013592 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.961975 # average fanout of values written-back +system.cpu.iew.WB:consumers 1490113215 # num instructions consuming a value +system.cpu.iew.WB:count 1862924801 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1423779046 # num instructions producing a value -system.cpu.iew.WB:rate 0.837032 # insts written-back per cycle -system.cpu.iew.WB:sent 1859125771 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 92169328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 589466 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 741821167 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21373722 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17131490 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 303434180 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2869215575 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 546583493 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 102562223 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1884127631 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 34476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1435567297 # num instructions producing a value +system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle +system.cpu.iew.WB:sent 1872447487 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91815044 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3100855 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21390967 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17059392 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 301399339 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2879831174 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94512444 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1894795217 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6237 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239479384 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 64949 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9892 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239759977 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75722 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115050739 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 46193 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6187227 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 339305081 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 136576398 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6187227 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1512324 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90657004 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637341 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637341 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1986689854 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 134541383 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90333500 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1989307661 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1179867838 59.39% # Type of FU issued + IntAlu 1186637129 59.65% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 3034528 0.15% # Type of FU issued + FloatAdd 2990803 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 573302529 28.86% # Type of FU issued - MemWrite 230484959 11.60% # Type of FU issued + MemRead 571681967 28.74% # Type of FU issued + MemWrite 227997762 11.46% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3941211 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 4014627 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 143231 3.63% # attempts to use FU when none available + IntAlu 142220 3.54% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 224126 5.69% # attempts to use FU when none available + FloatAdd 232755 5.80% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3231195 81.98% # attempts to use FU when none available - MemWrite 342659 8.69% # attempts to use FU when none available + MemRead 3328922 82.92% # attempts to use FU when none available + MemWrite 310730 7.74% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2205426950 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1088269781 4934.51% - 1 585554812 2655.06% - 2 294018661 1333.16% - 3 167298864 758.58% - 4 47518780 215.46% - 5 16542191 75.01% - 6 5287334 23.97% - 7 801167 3.63% - 8 135360 0.61% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.900818 # Inst issue rate -system.cpu.iq.iqInstsAdded 2497204504 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1986689854 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21670559 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1069656656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 613177 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19427058 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1294993594 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 272224 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5810.711032 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.711032 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1581815000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% +system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 +system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate +system.cpu.iq.iqInstsAdded 2506731488 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1989307661 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21683045 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1079315429 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 646014 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19439374 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1293054156 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.562838 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.514866 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9570275000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 272224 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 765143000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 272224 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5108.225294 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.225294 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 193435 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 178486500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.152998 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34941 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73663500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.152998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34941 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 69802 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.366465 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.524054 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 363694000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34106.857257 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384760 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 214678 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1194217500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.140229 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35014 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1085517500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140229 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35014 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 69802 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154299000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 69802 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338813 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338813 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 348749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 348749 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.927611 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.234507 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 500600 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5730.801035 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 193435 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1760301500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.613594 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 307165 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34273.636870 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 214678 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10764492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.593992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 314075 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 838806500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.613594 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 307165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9781481000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.593992 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 314075 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 500600 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5730.801035 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 193435 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1760301500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.613594 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 307165 # number of overall misses +system.cpu.l2cache.overall_hits 214678 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10764492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.593992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 314075 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 838806500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.613594 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 307165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9781481000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.593992 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 314075 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84439 # number of replacements -system.cpu.l2cache.sampled_refs 99904 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84499 # number of replacements +system.cpu.l2cache.sampled_refs 99950 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16410.322643 # Cycle average of tags in use -system.cpu.l2cache.total_refs 392384 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16402.920353 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423239 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61955 # number of writebacks -system.cpu.numCycles 2205428201 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14473307 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 33045 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 831088395 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23088197 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4934346294 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3102230072 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2427283324 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 719527974 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239479384 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32278343 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1182512267 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368579547 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 22008768 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170264872 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21765105 # count of temporary serializing insts renamed -system.cpu.timesIdled 5236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.l2cache.writebacks 61948 # number of writebacks +system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 141106002 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 301399339 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 2205318177 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 17694861 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 27117 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 826425901 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23298995 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4917191691 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3093611594 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2420068259 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 717791884 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239759977 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32521130 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1175289009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369621228 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21984761 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170791702 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21775082 # count of temporary serializing insts renamed +system.cpu.timesIdled 43184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr deleted file mode 100644 index 320065be7..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index b267c8dc4..8d0eebe28 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index ce05ca938..d1dad3acf 100644..100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:46:25 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:45 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2070157841000 because target called exit() +Exiting @ tick 744764119000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index a5fcdb950..d5f28736a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3930303 # Simulator instruction rate (inst/s) -host_mem_usage 176592 # Number of bytes of host memory used -host_seconds 378.98 # Real time elapsed on the host -host_tick_rate 1965156849 # Simulator tick rate (ticks/s) +host_inst_rate 3714547 # Simulator instruction rate (inst/s) +host_mem_usage 197792 # Number of bytes of host memory used +host_seconds 401.00 # Real time elapsed on the host +host_tick_rate 1857278454 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 0.744760 # Number of seconds simulated -sim_ticks 744759833500 # Number of ticks simulated +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 0.744764 # Number of seconds simulated +sim_ticks 744764119000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1489519668 # number of cpu cycles simulated -system.cpu.num_insts 1489514761 # Number of instructions executed -system.cpu.num_refs 569364430 # Number of memory references -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index 802ce964e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 6c34c6dee..90217b2a5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 5f4ac4eab..d75186ab5 100644..100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 744759833500 because target called exit() +Exiting @ tick 2076000877000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 49a7103b2..8851d2d2a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,244 +1,217 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1554729 # Simulator instruction rate (inst/s) -host_mem_usage 223840 # Number of bytes of host memory used -host_seconds 958.05 # Real time elapsed on the host -host_tick_rate 2160793398 # Simulator tick rate (ticks/s) +host_inst_rate 1328193 # Simulator instruction rate (inst/s) +host_mem_usage 205396 # Number of bytes of host memory used +host_seconds 1121.47 # Real time elapsed on the host +host_tick_rate 1851148785 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.070158 # Number of seconds simulated -sim_ticks 2070157841000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16192.525780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13192.525780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3132687000 # number of ReadReq miss cycles +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 2.076001 # Number of seconds simulated +sim_ticks 2076000877000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4079726000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2552292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3499268000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8629360000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7670542000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.282200 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 11762047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21977044000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10222834000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20437801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568845259 # number of overall hits -system.cpu.dcache.overall_miss_latency 11762047000 # number of overall miss cycles +system.cpu.dcache.overall_hits 568846579 # number of overall hits +system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513071 # number of overall misses +system.cpu.dcache.overall_misses 513081 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10222834000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20437801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449114 # number of replacements -system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 449125 # number of replacements +system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.499108 # Cycle average of tags in use -system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 373865000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316430 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26988.160291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23988.160291 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29633000 # number of ReadReq miss cycles +system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316424 # number of writebacks +system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 26339000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1356574.259563 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29633000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses +system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 26339000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489518537 # number of overall hits -system.cpu.icache.overall_miss_latency 29633000 # number of overall miss cycles +system.cpu.icache.overall_hits 1485111905 # number of overall hits +system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 1098 # number of overall misses +system.cpu.icache.overall_misses 1107 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 26339000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 115 # number of replacements -system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. +system.cpu.icache.replacements 118 # number of replacements +system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.563559 # Cycle average of tags in use -system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.413760 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5974135000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160837 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 775698000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173342 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33726 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 370986000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173342 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33726 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232066 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1377677000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 160849 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1754688000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173408 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33744 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1349760000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33744 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316430 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.429642 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160837 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6749833000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645974 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293471 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 160849 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15260908000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645963 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293479 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3228181000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645974 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293471 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11739160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645963 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293479 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160837 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6749833000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645974 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293471 # number of overall misses +system.cpu.l2cache.overall_hits 160849 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293479 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3228181000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645974 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293471 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11739160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645963 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293479 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82889 # number of replacements -system.cpu.l2cache.sampled_refs 98333 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82908 # number of replacements +system.cpu.l2cache.sampled_refs 98342 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16360.066474 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337247 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16358.086686 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61877 # number of writebacks +system.cpu.l2cache.writebacks 61864 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4140315682 # number of cpu cycles simulated -system.cpu.num_insts 1489514761 # Number of instructions executed -system.cpu.num_refs 569364430 # Number of memory references -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.numCycles 4152001754 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index 2a6ac4135..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index b66960bf9..1f354a5d6 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=gzip input.log 1 cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index b0a68cad2..875533d57 100644..100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 22:05:32 +M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch +M5 started Feb 24 2009 22:07:57 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes @@ -6,6 +20,7 @@ Input data 1048576 bytes in length Compressing Input Data, level 1 Compressed data 108074 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 @@ -29,16 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 21:35:26 2007 -M5 executing on nacho -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 954931687500 because target called exit() +Exiting @ tick 962928676500 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 15b900ea5..0158d9e3d 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3600198 # Simulator instruction rate (inst/s) -host_mem_usage 308780 # Number of bytes of host memory used -host_seconds 67.73 # Real time elapsed on the host -host_tick_rate 1804495302 # Simulator tick rate (ticks/s) +host_inst_rate 1045935 # Simulator instruction rate (inst/s) +host_mem_usage 197296 # Number of bytes of host memory used +host_seconds 1548.25 # Real time elapsed on the host +host_tick_rate 621947296 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 243829010 # Number of instructions simulated -sim_seconds 0.122213 # Number of seconds simulated -sim_ticks 122212687000 # Number of ticks simulated +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 0.962929 # Number of seconds simulated +sim_ticks 962928676500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 244425375 # number of cpu cycles simulated -system.cpu.num_insts 243829010 # Number of instructions executed -system.cpu.num_refs 105710359 # Number of memory references -system.cpu.workload.PROG:num_syscalls 428 # Number of system calls +system.cpu.numCycles 1925857354 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607228174 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr deleted file mode 100644 index 01076d21a..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,6 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..1e457c793 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..4f608c9b1 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 22:05:32 +M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch +M5 started Feb 24 2009 22:07:57 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +info: Increasing stack size by one page. +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 1814896671000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..b764de67a --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,207 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 660241 # Simulator instruction rate (inst/s) +host_mem_usage 204740 # Number of bytes of host memory used +host_seconds 2452.69 # Real time elapsed on the host +host_tick_rate 739961389 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 1.814897 # Number of seconds simulated +sim_ticks 1814896671000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 20939.027041 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17939.027041 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 418844309 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4141928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000472 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 197809 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3548501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000472 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 197809 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187873910 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17480176000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001659 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 312146 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16543738000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001659 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 312146 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1364.014744 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42400.023531 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606718219 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21622104000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000840 # miss rate for demand accesses +system.cpu.dcache.demand_misses 509955 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20092239000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000840 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 509955 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42400.023531 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 606718219 # number of overall hits +system.cpu.dcache.overall_miss_latency 21622104000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000840 # miss rate for overall accesses +system.cpu.dcache.overall_misses 509955 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20092239000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000840 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 509955 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 440755 # number of replacements +system.cpu.dcache.sampled_refs 444851 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.900352 # Cycle average of tags in use +system.cpu.dcache.total_refs 606783323 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 779366000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 308934 # number of writebacks +system.cpu.icache.ReadReq_accesses 1186516694 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1186515973 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1645653.221914 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1186516694 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 1186515973 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 721 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1186516694 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1186515973 # number of overall hits +system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 721 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 659.162719 # Cycle average of tags in use +system.cpu.icache.total_refs 1186515973 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 247042 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 12846184000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 247042 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9881680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 247042 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 198530 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 165128 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1736904000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.168247 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33402 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1336080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.168247 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33402 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 65104 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3385408000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 65104 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2604160000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 65104 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 308934 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 308934 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.437930 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 445572 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 165128 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14583088000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.629402 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 280444 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11217760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.629402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 280444 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 445572 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 165128 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14583088000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.629402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 280444 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11217760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.629402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 280444 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 82238 # number of replacements +system.cpu.l2cache.sampled_refs 97728 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16489.299090 # Cycle average of tags in use +system.cpu.l2cache.total_refs 335982 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61724 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 3629793342 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607228174 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini new file mode 100644 index 000000000..cd4931e34 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -0,0 +1,1355 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=LinuxAlphaSystem +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +boot_cpu_frequency=500 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=timing +pal=/dist/m5/system/binaries/ts_osfpal +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= +system_rev=1024 +system_type=34 + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:8589934591 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] + +[system.cpu0] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu0.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu0.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu0.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu0.fuPool.FUList0.opList + +[system.cpu0.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 + +[system.cpu0.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu0.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu0.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 + +[system.cpu0.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu0.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu0.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu0.fuPool.FUList4.opList + +[system.cpu0.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu0.fuPool.FUList5.opList + +[system.cpu0.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 + +[system.cpu0.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu0.fuPool.FUList7.opList + +[system.cpu0.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.interrupts] +type=AlphaInterrupts + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu1] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=1 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu1.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu1.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu1.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu1.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 + +[system.cpu1.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu1.fuPool.FUList0.opList + +[system.cpu1.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu1.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 + +[system.cpu1.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu1.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu1.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 + +[system.cpu1.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu1.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu1.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu1.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 + +[system.cpu1.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu1.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu1.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu1.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu1.fuPool.FUList4.opList + +[system.cpu1.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu1.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu1.fuPool.FUList5.opList + +[system.cpu1.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu1.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 + +[system.cpu1.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu1.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu1.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu1.fuPool.FUList7.opList + +[system.cpu1.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.interrupts] +type=AlphaInterrupts + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk0.image + +[system.disk0.image] +type=CowDiskImage +children=child +child=system.disk0.image.child +image_file= +read_only=false +table_size=65536 + +[system.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk2.image + +[system.disk2.image] +type=CowDiskImage +children=child +child=system.disk2.image.child +image_file= +read_only=false +table_size=65536 + +[system.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=true +width=64 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma + +[system.iocache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges=549755813888:18446744073709551615 +hash_delay=1 +latency=50000 +max_miss_count=0 +mem_side_filter_ranges=0:18446744073709551615 +mshrs=20 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[28] +mem_side=system.membus.port[2] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[3] + +[system.membus] +type=Bus +children=responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.membus.responder.pio +port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side + +[system.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.simple_disk] +type=SimpleDisk +children=disk +disk=system.simple_disk.disk +system=system + +[system.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + +[system.tsunami] +type=Tsunami +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=system.intrctrl +system=system + +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu0 +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + +[system.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[1] + +[system.tsunami.ethernet] +type=NSGigE +BAR0=1 +BAR0LegacyIO=false +BAR0Size=256 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=4096 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] + +[system.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[9] + +[system.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[20] + +[system.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[21] + +[system.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[10] + +[system.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[12] + +[system.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[13] + +[system.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[14] + +[system.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[15] + +[system.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[16] + +[system.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[17] + +[system.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[18] + +[system.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[19] + +[system.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[11] + +[system.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848891 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[8] + +[system.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[3] + +[system.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[4] + +[system.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[5] + +[system.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[6] + +[system.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[7] + +[system.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=system.tsunami +system=system +pio=system.iobus.port[22] + +[system.tsunami.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] + +[system.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=system.tsunami +system=system +time=Thu Jan 1 00:00:00 2009 +tsunami=system.tsunami +year_is_bcd=false +pio=system.iobus.port[23] + +[system.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[2] + +[system.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=system.tsunami +size=16777216 +system=system +pio=system.iobus.default + +[system.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[24] + diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr new file mode 100755 index 000000000..f51a48835 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: 125740500: Trying to launch CPU number 1! +For more information see: http://www.m5sim.org/warn/8f7d2563 +hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout new file mode 100755 index 000000000..a6115dc06 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:39 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:15:43 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1907705384500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt new file mode 100644 index 000000000..a35446ce7 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -0,0 +1,1073 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 195579 # Simulator instruction rate (inst/s) +host_mem_usage 296668 # Number of bytes of host memory used +host_seconds 287.30 # Real time elapsed on the host +host_tick_rate 6640015618 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 56190549 # Number of instructions simulated +sim_seconds 1.907705 # Number of seconds simulated +sim_ticks 1907705384500 # Number of ticks simulated +system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.BPredUnit.BTBHits 4976196 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 9270308 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 8475186 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 10093436 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 5979895 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 670394 # number cycles where commit BW limit reached +system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle.samples 69432721 +system.cpu0.commit.COM:committed_per_cycle.min_value 0 + 0 52134013 7508.57% + 1 7662361 1103.57% + 2 4443978 640.04% + 3 2023859 291.48% + 4 1473823 212.27% + 5 453847 65.37% + 6 276435 39.81% + 7 294011 42.34% + 8 670394 96.55% +system.cpu0.commit.COM:committed_per_cycle.max_value 8 +system.cpu0.commit.COM:committed_per_cycle.end_dist + +system.cpu0.commit.COM:count 39866260 # Number of instructions committed +system.cpu0.commit.COM:loads 6404474 # Number of loads committed +system.cpu0.commit.COM:membars 151021 # Number of memory barriers committed +system.cpu0.commit.COM:refs 10831640 # Number of memory references committed +system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.branchMispredicts 524450 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 39866260 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 458375 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6218747 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 37660679 # Number of Instructions Simulated +system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated +system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.679241 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses 147686 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15414.654688 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 135219 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 192174500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.084416 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 12467 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 6414696 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 28975.378056 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28716.351233 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_hits 5468142 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 27426760000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.147560 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 946554 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 250845 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 19978224000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108455 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 156551 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 54667.977283 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51667.977283 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 140528 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 875945000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.102350 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 16023 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827876000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 4258061 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 48857.574152 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.516019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_hits 2612712 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 80387760774 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.386408 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 1645349 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 15269940236 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066495 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050786497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9307.072518 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.224260 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 116343 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 1082812738 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 10672757 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 41596.664989 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 8080854 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 107814520774 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.242852 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2591903 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1613053 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 35248164236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.091715 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 10672757 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 41596.664989 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 8080854 # number of overall hits +system.cpu0.dcache.overall_miss_latency 107814520774 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.242852 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2591903 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1613053 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 35248164236 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.091715 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1690648997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.replacements 922726 # number of replacements +system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 442.178159 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8515127 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 297339 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33638498 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 26518 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 401379 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 50930127 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 25726100 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9143957 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1094068 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking +system.cpu0.dtb.accesses 812672 # DTB accesses +system.cpu0.dtb.acv 801 # DTB access violations +system.cpu0.dtb.hits 11625470 # DTB hits +system.cpu0.dtb.misses 28525 # DTB misses +system.cpu0.dtb.read_accesses 605265 # DTB read accesses +system.cpu0.dtb.read_acv 596 # DTB read access violations +system.cpu0.dtb.read_hits 7063685 # DTB read hits +system.cpu0.dtb.read_misses 24056 # DTB read misses +system.cpu0.dtb.write_accesses 207407 # DTB write accesses +system.cpu0.dtb.write_acv 205 # DTB write access violations +system.cpu0.dtb.write_hits 4561785 # DTB write hits +system.cpu0.dtb.write_misses 4469 # DTB write misses +system.cpu0.fetch.Branches 10093436 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6456939 # Number of cache lines fetched +system.cpu0.fetch.Cycles 16710993 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 292607 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 52006564 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 345 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 660338 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100032 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6456939 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5666570 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist.samples 70526789 +system.cpu0.fetch.rateDist.min_value 0 + 0 60303520 8550.44% + 1 761818 108.02% + 2 1433854 203.31% + 3 636079 90.19% + 4 2329702 330.33% + 5 474692 67.31% + 6 552513 78.34% + 7 815433 115.62% + 8 3219178 456.45% +system.cpu0.fetch.rateDist.max_value 8 +system.cpu0.fetch.rateDist.end_dist + +system.cpu0.icache.ReadReq_accesses 6456939 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 15194.131269 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.657762 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 5806696 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 9879877499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.100705 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 650243 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 29877 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 7526067999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.096077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs 11808.794118 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 9.361637 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 34 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 401499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 6456939 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 15194.131269 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency +system.cpu0.icache.demand_hits 5806696 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 9879877499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.100705 # miss rate for demand accesses +system.cpu0.icache.demand_misses 650243 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 29877 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 7526067999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.096077 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 620366 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 6456939 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 15194.131269 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 5806696 # number of overall hits +system.cpu0.icache.overall_miss_latency 9879877499 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.100705 # miss rate for overall accesses +system.cpu0.icache.overall_misses 650243 # number of overall misses +system.cpu0.icache.overall_mshr_hits 29877 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 7526067999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.096077 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.replacements 619753 # number of replacements +system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 509.829037 # Cycle average of tags in use +system.cpu0.icache.total_refs 5806696 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idleCycles 30375232 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6436271 # Number of branches executed +system.cpu0.iew.EXEC:nop 2512861 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.402649 # Inst execution rate +system.cpu0.iew.EXEC:refs 11740634 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4575971 # Number of stores executed +system.cpu0.iew.EXEC:swp 0 # number of swp insts executed +system.cpu0.iew.WB:consumers 24161361 # num instructions consuming a value +system.cpu0.iew.WB:count 40226140 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.779058 # average fanout of values written-back +system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.iew.WB:producers 18823101 # num instructions producing a value +system.cpu0.iew.WB:rate 0.398665 # insts written-back per cycle +system.cpu0.iew.WB:sent 40293974 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 568843 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7178022 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 7553751 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1229599 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 771955 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 4835994 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 46191067 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7164663 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359395 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 40628051 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 33755 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewLSQFullEvents 4184 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1094068 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 453365 # Number of cycles IEW is unblocking +system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread.0.cacheBlocked 243041 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 357779 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8886 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.memOrderViolation 34084 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12238 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1149277 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 408828 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 34084 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 255799 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0 40987446 # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.start_dist + No_OpClass 3326 0.01% # Type of FU issued + IntAlu 28267902 68.97% # Type of FU issued + IntMult 42211 0.10% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 12076 0.03% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 1657 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 7398183 18.05% # Type of FU issued + MemWrite 4612040 11.25% # Type of FU issued + IprAccess 650051 1.59% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.end_dist +system.cpu0.iq.ISSUE:fu_busy_cnt 290461 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 33502 11.53% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 185625 63.91% # attempts to use FU when none available + MemWrite 71334 24.56% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full.end_dist +system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526789 +system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764698 70.56% +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507711 14.90% +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625293 6.56% +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839060 4.03% +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729945 2.45% +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663621 0.94% +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315226 0.45% +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67152 0.10% +system.cpu0.iq.ISSUE:issued_per_cycle::8 14083 0.02% +system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu0.iq.ISSUE:issued_per_cycle::total 70526789 +system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581161 +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133095 +system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate +system.cpu0.iq.iqInstsAdded 42280485 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 40987446 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1397721 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 5737873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 23379 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3058467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.itb.accesses 875811 # ITB accesses +system.cpu0.itb.acv 900 # ITB acv +system.cpu0.itb.hits 845925 # ITB hits +system.cpu0.itb.misses 29886 # ITB misses +system.cpu0.kern.callpal 129578 # number of callpals executed +system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed +system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed +system.cpu0.kern.callpal_swpipl 116005 89.53% 91.51% # number of callpals executed +system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.42% # number of callpals executed +system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed +system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.hwrei 144417 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4856 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 122308 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 47763 39.05% 39.05% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1931 1.58% 40.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 72358 59.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 96397 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 47113 48.87% 48.87% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1931 2.00% 51.13% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1907288793500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1871606924500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 101495000 0.01% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 397995000 0.02% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 35173048000 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.986391 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.650889 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1283 +system.cpu0.kern.mode_good_user 1283 +system.cpu0.kern.mode_good_idle 0 +system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1283 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.217679 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 1905143965500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2121516000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 2411 # number of times the context was actually changed +system.cpu0.kern.syscall 222 # number of syscalls executed +system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2050532 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1832540 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 7553751 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4835994 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 100902021 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 10627682 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 742849 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 26930411 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1646609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16617 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 58880309 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 48158423 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 32535865 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9104795 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1094068 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3612727 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5197954 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 19157104 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1163461 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 8536821 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed +system.cpu0.timesIdled 904725 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.BPredUnit.BTBHits 2271370 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 5052293 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 5538388 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 2947825 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached +system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle.samples 37477455 +system.cpu1.commit.COM:committed_per_cycle.min_value 0 + 0 29419466 7849.91% + 1 3577484 954.57% + 2 1728132 461.11% + 3 1049888 280.14% + 4 708571 189.07% + 5 265965 70.97% + 6 180885 48.27% + 7 145538 38.83% + 8 401526 107.14% +system.cpu1.commit.COM:committed_per_cycle.max_value 8 +system.cpu1.commit.COM:committed_per_cycle.end_dist + +system.cpu1.commit.COM:count 19663805 # Number of instructions committed +system.cpu1.commit.COM:loads 3551077 # Number of loads committed +system.cpu1.commit.COM:membars 87378 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5861573 # Number of memory references committed +system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.branchMispredicts 311117 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 19663805 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 255745 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3736987 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 18529870 # Number of Instructions Simulated +system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated +system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.312190 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses 72126 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14445.783133 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 59842 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 177452000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.170313 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 12284 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 2016 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115024000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 10268 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 3589521 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15546.334532 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11998.783257 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_hits 2947311 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9984011500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.178912 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 642210 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 211141 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 5172303500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 431069 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298579500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 68169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 54676.100066 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 51420 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 915770000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.245698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 16749 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865523000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245698 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 16749 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 2234886 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 49366.448141 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.795546 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_hits 1540754 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 34266831381 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.310589 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 694132 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 551528 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 7735952636 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063808 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs 13994.026145 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 8.879315 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 31364 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 438908636 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 5824407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 33113.411747 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 4488065 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 44250842881 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.229438 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 1336342 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 762669 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 12908256136 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.098495 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 573673 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 5824407 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 33113.411747 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 4488065 # number of overall hits +system.cpu1.dcache.overall_miss_latency 44250842881 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.229438 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 1336342 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 762669 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 12908256136 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.098495 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 824622000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.replacements 531784 # number of replacements +system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 487.083551 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4726424 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 158239 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 17789626 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 246498 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 26253438 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 14731458 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4724229 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 641522 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking +system.cpu1.dtb.accesses 433929 # DTB accesses +system.cpu1.dtb.acv 77 # DTB access violations +system.cpu1.dtb.hits 6280849 # DTB hits +system.cpu1.dtb.misses 17153 # DTB misses +system.cpu1.dtb.read_accesses 314117 # DTB read accesses +system.cpu1.dtb.read_acv 13 # DTB read access violations +system.cpu1.dtb.read_hits 3872885 # DTB read hits +system.cpu1.dtb.read_misses 13436 # DTB read misses +system.cpu1.dtb.write_accesses 119812 # DTB write accesses +system.cpu1.dtb.write_acv 64 # DTB write access violations +system.cpu1.dtb.write_hits 2407964 # DTB write hits +system.cpu1.dtb.write_misses 3717 # DTB write misses +system.cpu1.fetch.Branches 5538388 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 3089103 # Number of cache lines fetched +system.cpu1.fetch.Cycles 8137043 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 192735 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 26826541 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 1090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 373513 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.129267 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.626136 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist.samples 38118977 +system.cpu1.fetch.rateDist.min_value 0 + 0 33077956 8677.56% + 1 338219 88.73% + 2 684572 179.59% + 3 401330 105.28% + 4 792380 207.87% + 5 254419 66.74% + 6 341251 89.52% + 7 404733 106.18% + 8 1824117 478.53% +system.cpu1.fetch.rateDist.max_value 8 +system.cpu1.fetch.rateDist.end_dist + +system.cpu1.icache.ReadReq_accesses 3089103 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14554.963245 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.753460 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 2620972 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6813629499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 468131 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 20962 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 5189286000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.144757 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 5.861938 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 3089103 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14554.963245 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency +system.cpu1.icache.demand_hits 2620972 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6813629499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_misses 468131 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 20962 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 5189286000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.144757 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 447169 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 3089103 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14554.963245 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 2620972 # number of overall hits +system.cpu1.icache.overall_miss_latency 6813629499 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_misses 468131 # number of overall misses +system.cpu1.icache.overall_mshr_hits 20962 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 5189286000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.144757 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.replacements 446606 # number of replacements +system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 504.476148 # Cycle average of tags in use +system.cpu1.icache.total_refs 2620972 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idleCycles 4725605 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 3215748 # Number of branches executed +system.cpu1.iew.EXEC:nop 1316352 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.474711 # Inst execution rate +system.cpu1.iew.EXEC:refs 6453696 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2419389 # Number of stores executed +system.cpu1.iew.EXEC:swp 0 # number of swp insts executed +system.cpu1.iew.WB:consumers 12378269 # num instructions consuming a value +system.cpu1.iew.WB:count 20082329 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.731659 # average fanout of values written-back +system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.iew.WB:producers 9056670 # num instructions producing a value +system.cpu1.iew.WB:rate 0.468725 # insts written-back per cycle +system.cpu1.iew.WB:sent 20124761 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 338961 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2501198 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 4247428 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 782465 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 352902 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2557361 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 23476813 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 4034307 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 224585 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 20338799 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 13271 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewLSQFullEvents 2314 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 641522 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 92599 # Number of cycles IEW is unblocking +system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread.0.cacheBlocked 96430 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 136935 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 5812 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread.0.memOrderViolation 18288 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 7650 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 696351 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 246865 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 18288 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 160561 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0 20563386 # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0.start_dist + No_OpClass 3984 0.02% # Type of FU issued + IntAlu 13476321 65.54% # Type of FU issued + IntMult 28965 0.14% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 13702 0.07% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 1986 0.01% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 4173926 20.30% # Type of FU issued + MemWrite 2443261 11.88% # Type of FU issued + IprAccess 421241 2.05% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0.end_dist +system.cpu1.iq.ISSUE:fu_busy_cnt 221052 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010750 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 16139 7.30% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 131915 59.68% # attempts to use FU when none available + MemWrite 72998 33.02% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full.end_dist +system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118977 +system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405823 74.52% +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664380 12.24% +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989669 5.22% +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362790 3.58% +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979073 2.57% +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465618 1.22% +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186895 0.49% +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52286 0.14% +system.cpu1.iq.ISSUE:issued_per_cycle::8 12443 0.03% +system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu1.iq.ISSUE:issued_per_cycle::total 38118977 +system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539453 +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158806 +system.cpu1.iq.ISSUE:rate 0.479953 # Inst issue rate +system.cpu1.iq.iqInstsAdded 21283894 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 20563386 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 876567 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3483485 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 16725 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1773520 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.itb.accesses 525294 # ITB accesses +system.cpu1.itb.acv 109 # ITB acv +system.cpu1.itb.hits 518481 # ITB hits +system.cpu1.itb.misses 6813 # ITB misses +system.cpu1.kern.callpal 87355 # number of callpals executed +system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed +system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed +system.cpu1.kern.callpal_swpipl 79684 91.22% 93.36% # number of callpals executed +system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 96.12% # number of callpals executed +system.cpu1.kern.callpal_rti 3206 3.67% 99.79% # number of callpals executed +system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # number of callpals executed +system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.hwrei 93966 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3806 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 84915 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 34143 40.21% 40.21% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 48748 57.41% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 68760 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 33416 48.60% 48.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1907704531000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1871986899500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 352080000 0.02% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 40004500 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 35325547000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.978707 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.683515 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 521 +system.cpu1.kern.mode_good_user 463 +system.cpu1.kern.mode_good_idle 58 +system.cpu1.kern.mode_switch_kernel 2305 # number of protection mode switches +system.cpu1.kern.mode_switch_user 463 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.254532 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.226030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 46750182500 2.45% 2.45% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1015923000 0.05% 2.50% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1859938417500 97.50% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1839 # number of times the context was actually changed +system.cpu1.kern.syscall 104 # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 906322 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 817104 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 4247428 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2557361 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 42844582 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3655834 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 331503 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 15199760 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 648645 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 1226 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 29419469 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 24525114 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 16182590 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 4333684 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 641522 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1812010 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2990936 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 12476165 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 728375 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4962161 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 86287 # count of temporary serializing insts renamed +system.cpu1.timesIdled 480520 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115331.417143 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20182998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 175 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11082998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137844.166490 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727700806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3566847774 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6165.982406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64483844 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41727 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137749.749658 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5747883804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41727 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3577930772 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41727 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137749.749658 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5747883804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41727 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3577930772 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.replacements 41697 # number of replacements +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0.387817 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1717170531000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41522 # number of writebacks +system.l2c.ReadExReq_accesses 317502 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52375.567080 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40223.034620 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16629347299 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 317502 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12770893938 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 317502 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2204255 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52067.361570 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.445360 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1893900 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16159366000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.140798 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 310355 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12421727000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.140790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 310338 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840472000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 141949 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 51066.182164 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.287026 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7248793492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 141949 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5691202000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1423764498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 455578 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 455578 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 4.834791 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2521757 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52223.218502 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency +system.l2c.demand_hits 1893900 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32788713299 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.248976 # miss rate for demand accesses +system.l2c.demand_misses 627857 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 25192620938 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.248969 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 627840 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2521757 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52223.218502 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1893900 # number of overall hits +system.l2c.overall_miss_latency 32788713299 # number of overall miss cycles +system.l2c.overall_miss_rate 0.248976 # miss rate for overall accesses +system.l2c.overall_misses 627857 # number of overall misses +system.l2c.overall_mshr_hits 17 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 25192620938 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.248969 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 627840 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2264236498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 402142 # number of replacements +system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 31163.178814 # Cycle average of tags in use +system.l2c.total_refs 2096699 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 124293 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index c2aeea3f1..6c5842787 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -27,6 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 @@ -60,6 +61,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -71,6 +73,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini new file mode 100644 index 000000000..c7a30cef6 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -0,0 +1,1048 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=LinuxAlphaSystem +children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +boot_cpu_frequency=500 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=timing +pal=/dist/m5/system/binaries/ts_osfpal +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= +system_rev=1024 +system_type=34 + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:8589934591 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList5.opList + +[system.cpu.fuPool.FUList5.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList7.opList + +[system.cpu.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.interrupts] +type=AlphaInterrupts + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk0.image + +[system.disk0.image] +type=CowDiskImage +children=child +child=system.disk0.image.child +image_file= +read_only=false +table_size=65536 + +[system.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk2.image + +[system.disk2.image] +type=CowDiskImage +children=child +child=system.disk2.image.child +image_file= +read_only=false +table_size=65536 + +[system.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=true +width=64 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma + +[system.iocache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges=549755813888:18446744073709551615 +hash_delay=1 +latency=50000 +max_miss_count=0 +mem_side_filter_ranges=0:18446744073709551615 +mshrs=20 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[28] +mem_side=system.membus.port[2] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[3] + +[system.membus] +type=Bus +children=responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.membus.responder.pio +port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side + +[system.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.simple_disk] +type=SimpleDisk +children=disk +disk=system.simple_disk.disk +system=system + +[system.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-latest.img +read_only=true + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + +[system.tsunami] +type=Tsunami +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=system.intrctrl +system=system + +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + +[system.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[1] + +[system.tsunami.ethernet] +type=NSGigE +BAR0=1 +BAR0LegacyIO=false +BAR0Size=256 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=4096 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] + +[system.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[9] + +[system.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[20] + +[system.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[21] + +[system.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[10] + +[system.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[12] + +[system.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[13] + +[system.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[14] + +[system.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[15] + +[system.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[16] + +[system.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[17] + +[system.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[18] + +[system.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[19] + +[system.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[11] + +[system.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848891 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[8] + +[system.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[3] + +[system.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[4] + +[system.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[5] + +[system.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[6] + +[system.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=system.tsunami +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[7] + +[system.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=system.tsunami +system=system +pio=system.iobus.port[22] + +[system.tsunami.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] + +[system.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=system.tsunami +system=system +time=Thu Jan 1 00:00:00 2009 +tsunami=system.tsunami +year_is_bcd=false +pio=system.iobus.port[23] + +[system.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=system.tsunami +system=system +tsunami=system.tsunami +pio=system.iobus.port[2] + +[system.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=system.tsunami +size=16777216 +system=system +pio=system.iobus.default + +[system.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[24] + diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr new file mode 100755 index 000000000..83c71fc5c --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout new file mode 100755 index 000000000..139f5f740 --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:39 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:15:42 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1867363148500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt new file mode 100644 index 000000000..4534484ec --- /dev/null +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -0,0 +1,640 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 203131 # Simulator instruction rate (inst/s) +host_mem_usage 294692 # Number of bytes of host memory used +host_seconds 261.36 # Real time elapsed on the host +host_tick_rate 7144744614 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 53090630 # Number of instructions simulated +sim_seconds 1.867363 # Number of seconds simulated +sim_ticks 1867363148500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 6937900 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 13339861 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14570242 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8461943 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 974606 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 100617513 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 76371867 7590.32% + 1 10755813 1068.98% + 2 5991818 595.50% + 3 2987930 296.96% + 4 2074332 206.16% + 5 671621 66.75% + 6 397219 39.48% + 7 392307 38.99% + 8 974606 96.86% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 56284983 # Number of instructions committed +system.cpu.commit.COM:loads 9308629 # Number of loads committed +system.cpu.commit.COM:membars 228003 # Number of memory barriers committed +system.cpu.commit.COM:refs 15700868 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 787164 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56284983 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667781 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9518126 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53090630 # Number of Instructions Simulated +system.cpu.committedInsts_total 53090630 # Number of Instructions Simulated +system.cpu.cpi 2.580435 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.580435 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 214297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 15516.058460 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11817.323059 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 192128 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 343975500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.103450 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 22169 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4649 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207039500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081756 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17520 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9342423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 23886.371687 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.504418 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits 7809504 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36615873000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.164082 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1532919 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 448215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24692749000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.116105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1084704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904972000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 219789 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.265633 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.265633 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 189804 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689093000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.136426 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29985 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599138000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136426 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 29985 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6157295 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 49032.528329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.949680 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits 3927003 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109356855672 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.362219 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2230292 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833354 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21630322460 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.064466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 396938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235426497 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.885310 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.828407 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1383175962 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 15499718 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38789.408479 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency +system.cpu.dcache.demand_hits 11736507 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 145972728672 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.242792 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3763211 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46323071460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095592 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1481642 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 15499718 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38789.408479 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 11736507 # number of overall hits +system.cpu.dcache.overall_miss_latency 145972728672 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.242792 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3763211 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46323071460 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095592 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1401991 # number of replacements +system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use +system.cpu.dcache.total_refs 12381868 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430428 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48410304 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42525 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 614935 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72780900 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37979006 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 13077120 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1650418 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134762 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1151082 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 1236420 # DTB accesses +system.cpu.dtb.acv 825 # DTB access violations +system.cpu.dtb.hits 16772347 # DTB hits +system.cpu.dtb.misses 44495 # DTB misses +system.cpu.dtb.read_accesses 910052 # DTB read accesses +system.cpu.dtb.read_acv 586 # DTB read access violations +system.cpu.dtb.read_hits 10174508 # DTB read hits +system.cpu.dtb.read_misses 36219 # DTB read misses +system.cpu.dtb.write_accesses 326368 # DTB write accesses +system.cpu.dtb.write_acv 239 # DTB write access violations +system.cpu.dtb.write_hits 6597839 # DTB write hits +system.cpu.dtb.write_misses 8276 # DTB write misses +system.cpu.fetch.Branches 14570242 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 9007841 # Number of cache lines fetched +system.cpu.fetch.Cycles 23500316 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455597 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74326781 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 969865 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106355 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 9007841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7972800 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542543 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 102267931 +system.cpu.fetch.rateDist.min_value 0 + 0 87815810 8586.84% + 1 1050742 102.74% + 2 2021882 197.70% + 3 969421 94.79% + 4 3003437 293.68% + 5 686434 67.12% + 6 832579 81.41% + 7 1218388 119.14% + 8 4669238 456.57% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 9007841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14905.597019 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.422251 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 7960337 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15613672500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.116288 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1047504 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51957 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11854398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.110520 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 995547 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs 11175.438596 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 7.997460 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 57 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 637000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 9007841 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14905.597019 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency +system.cpu.icache.demand_hits 7960337 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15613672500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.116288 # miss rate for demand accesses +system.cpu.icache.demand_misses 1047504 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51957 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11854398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.110520 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 995547 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 9007841 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14905.597019 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 7960337 # number of overall hits +system.cpu.icache.overall_miss_latency 15613672500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.116288 # miss rate for overall accesses +system.cpu.icache.overall_misses 1047504 # number of overall misses +system.cpu.icache.overall_mshr_hits 51957 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11854398500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.110520 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 994847 # number of replacements +system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 509.772456 # Cycle average of tags in use +system.cpu.icache.total_refs 7960336 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 34729008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9164699 # Number of branches executed +system.cpu.iew.EXEC:nop 3680668 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420415 # Inst execution rate +system.cpu.iew.EXEC:refs 17055609 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6621040 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 34548488 # num instructions consuming a value +system.cpu.iew.WB:count 57002857 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763990 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 26394693 # num instructions producing a value +system.cpu.iew.WB:rate 0.416089 # insts written-back per cycle +system.cpu.iew.WB:sent 57104330 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 856523 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9726576 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11055097 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1799800 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1048637 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7027136 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65932751 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10434569 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 539744 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57595615 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 50922 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 6567 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1650418 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 550443 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 311143 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 426303 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 11520 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 46025 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15352 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1746468 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 634897 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 46025 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 380989 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 475534 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387532 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387532 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 58135361 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 7284 0.01% # Type of FU issued + IntAlu 39619390 68.15% # Type of FU issued + IntMult 62115 0.11% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 25609 0.04% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 3636 0.01% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 10789898 18.56% # Type of FU issued + MemWrite 6674141 11.48% # Type of FU issued + IprAccess 953288 1.64% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 434481 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 52045 11.98% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 278817 64.17% # attempts to use FU when none available + MemWrite 103619 23.85% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle::samples 102267931 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73151138 71.53% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14628619 14.30% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6419666 6.28% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3934330 3.85% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528894 2.47% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1032607 1.01% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 444582 0.43% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 106443 0.10% +system.cpu.iq.ISSUE:issued_per_cycle::8 21652 0.02% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 102267931 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568461 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.134174 +system.cpu.iq.ISSUE:rate 0.424355 # Inst issue rate +system.cpu.iq.iqInstsAdded 60200389 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58135361 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2051694 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8738375 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34584 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1383913 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4729371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1303895 # ITB accesses +system.cpu.itb.acv 943 # ITB acv +system.cpu.itb.hits 1264480 # ITB hits +system.cpu.itb.misses 39415 # ITB misses +system.cpu.kern.callpal 192656 # number of callpals executed +system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175684 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.hwrei 211815 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6383 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183033 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74957 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105949 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149307 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73590 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73590 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1867362274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1824759658500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 102563000 0.01% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 392423000 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 42107629500 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.694579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1911 +system.cpu.kern.mode_good_user 1741 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5973 # number of protection mode switches +system.cpu.kern.mode_switch_user 1741 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.401085 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319940 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 31312997500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3190588500 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1832858680000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed +system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.memDep0.conflictingLoads 3083644 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2877472 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7027136 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 136996939 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14276861 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38259280 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1099460 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39573188 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2235524 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15708 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83522905 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68741813 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46071316 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12717646 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1650418 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5220588 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7812034 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28829228 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704991 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12807732 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256915 # count of temporary serializing insts renamed +system.cpu.timesIdled 1321478 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115277.445087 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses 173 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency 137802.098720 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85798.754910 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725952806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3565109864 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles_no_mshrs 6162.652539 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked_no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64559948 # number of cycles access was blocked +system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses 41725 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137708.707106 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency +system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 5745895804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate 1 # miss rate for demand accesses +system.iocache.demand_misses 41725 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 3576056862 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses 41725 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137708.707106 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_miss_latency 5745895804 # number of overall miss cycles +system.iocache.overall_miss_rate 1 # miss rate for overall accesses +system.iocache.overall_misses 41725 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 3576056862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.replacements 41685 # number of replacements +system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 1.267414 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 1716180054000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41512 # number of writebacks +system.l2c.ReadExReq_accesses 300588 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52362.011561 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40213.127257 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739392331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 300588 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12087583496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 300588 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2097395 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52065.516476 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40025.575526 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits 1786374 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16193469000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.148289 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 311021 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12448754500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.148289 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 311020 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810514000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 130249 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52272.455021 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40098.173498 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6808434994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 130249 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5222747000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 130249 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1115855498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430428 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430428 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 4.596635 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2397983 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52211.235170 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency +system.l2c.demand_hits 1786374 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31932861331 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.255051 # miss rate for demand accesses +system.l2c.demand_misses 611609 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24536337996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.255051 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 611608 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 2397983 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52211.235170 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits 1786374 # number of overall hits +system.l2c.overall_miss_latency 31932861331 # number of overall miss cycles +system.l2c.overall_miss_rate 0.255051 # miss rate for overall accesses +system.l2c.overall_misses 611609 # number of overall misses +system.l2c.overall_mshr_hits 1 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24536337996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.255051 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 396031 # number of replacements +system.l2c.sampled_refs 427707 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 30680.970322 # Cycle average of tags in use +system.l2c.total_refs 1966013 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119091 # number of writebacks +system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal index 7930e9e46..1b4012ef1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -24,6 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 @@ -55,6 +56,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -66,6 +68,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/long/10.linux-boot/test.py b/tests/long/10.linux-boot/test.py new file mode 100644 index 000000000..215d63700 --- /dev/null +++ b/tests/long/10.linux-boot/test.py @@ -0,0 +1,29 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +root.system.readfile = os.path.join(tests_root, 'halt.sh') diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index ef3141a33..3c2bf8020 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=mcf mcf.in cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=55300000000 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:268435455 zero=false port=system.membus.port[0] diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index 8270f923d..6c41adbc1 100644..100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:51:47 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py long/10.mcf/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -14,16 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:46 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 363652229000 because target called exit() +Exiting @ tick 122215830000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 794286196..a02166247 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1168424 # Simulator instruction rate (inst/s) -host_mem_usage 310284 # Number of bytes of host memory used -host_seconds 230.78 # Real time elapsed on the host -host_tick_rate 718029499 # Simulator tick rate (ticks/s) +host_inst_rate 2414989 # Simulator instruction rate (inst/s) +host_mem_usage 329980 # Number of bytes of host memory used +host_seconds 100.97 # Real time elapsed on the host +host_tick_rate 1210444801 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269642969 # Number of instructions simulated -sim_seconds 0.165704 # Number of seconds simulated -sim_ticks 165703616000 # Number of ticks simulated +sim_insts 243835278 # Number of instructions simulated +sim_seconds 0.122216 # Number of seconds simulated +sim_ticks 122215830000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331407233 # number of cpu cycles simulated -system.cpu.num_insts 269642969 # Number of instructions executed -system.cpu.num_refs 124052668 # Number of memory references -system.cpu.workload.PROG:num_syscalls 429 # Number of system calls +system.cpu.numCycles 244431661 # number of cpu cycles simulated +system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.num_refs 105711442 # Number of memory references +system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index 2a6ac4135..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index a0f77bf10..8066afd8e 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=mcf mcf.in cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=55300000000 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:268435455 zero=false port=system.membus.port[0] diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index eb0a0f196..b171def01 100644..100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -14,16 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 122212687000 because target called exit() +Exiting @ tick 366435406000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 7fe2ea602..1e841feab 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,244 +1,217 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 892340 # Simulator instruction rate (inst/s) -host_mem_usage 338704 # Number of bytes of host memory used -host_seconds 273.25 # Real time elapsed on the host -host_tick_rate 1330855666 # Simulator tick rate (ticks/s) +host_inst_rate 1212571 # Simulator instruction rate (inst/s) +host_mem_usage 337588 # Number of bytes of host memory used +host_seconds 201.09 # Real time elapsed on the host +host_tick_rate 1822248337 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 243829010 # Number of instructions simulated -sim_seconds 0.363652 # Number of seconds simulated -sim_ticks 363652229000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14002.970284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.970284 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 81326625 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12502468000 # number of ReadReq miss cycles +sim_insts 243835278 # Number of instructions simulated +sim_seconds 0.366435 # Number of seconds simulated +sim_ticks 366435406000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 892844 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9823936000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 892844 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 216000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 192000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 22806873 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2564001000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2279112000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 110.887563 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15252.442026 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12252.442026 # average overall mshr miss latency -system.cpu.dcache.demand_hits 104133498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15066469000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency +system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses -system.cpu.dcache.demand_misses 987807 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12103048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 987807 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15252.442026 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12252.442026 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 104133498 # number of overall hits -system.cpu.dcache.overall_miss_latency 15066469000 # number of overall miss cycles +system.cpu.dcache.overall_hits 104134565 # number of overall hits +system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses -system.cpu.dcache.overall_misses 987807 # number of overall misses +system.cpu.dcache.overall_misses 987820 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12103048000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 987807 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 935465 # number of replacements -system.cpu.dcache.sampled_refs 939561 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 935475 # number of replacements +system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3567.172946 # Cycle average of tags in use -system.cpu.dcache.total_refs 104185630 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134200939000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 94875 # number of writebacks -system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26970.420933 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.420933 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 244424462 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 23707000 # number of ReadReq miss cycles +system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use +system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 94877 # number of writebacks +system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 21070000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 278071.060296 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 244425341 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26970.420933 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23970.420933 # average overall mshr miss latency -system.cpu.icache.demand_hits 244424462 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 23707000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency +system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 879 # number of demand (read+write) misses +system.cpu.icache.demand_misses 882 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21070000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 244425341 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26970.420933 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23970.420933 # average overall mshr miss latency +system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 244424462 # number of overall hits -system.cpu.icache.overall_miss_latency 23707000 # number of overall miss cycles +system.cpu.icache.overall_hits 244420630 # number of overall hits +system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 879 # number of overall misses +system.cpu.icache.overall_misses 882 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21070000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.881678 # Cycle average of tags in use -system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use +system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 46717 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1074491000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 46717 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 513887000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 46717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 893723 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 892642 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 24863000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11891000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 48254 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1109842000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 48254 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530794000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 48254 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 51.564846 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 940440 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 892642 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1099354000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.050825 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 47798 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 525778000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.050825 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 47798 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 940440 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 892642 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1099354000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.050825 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 47798 # number of overall misses +system.cpu.l2cache.overall_hits 892653 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47800 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 525778000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.050825 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 47798 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 877 # number of replacements -system.cpu.l2cache.sampled_refs 15560 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 891 # number of replacements +system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8941.212243 # Cycle average of tags in use -system.cpu.l2cache.total_refs 802349 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8959.416448 # Cycle average of tags in use +system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 727304458 # number of cpu cycles simulated -system.cpu.num_insts 243829010 # Number of instructions executed -system.cpu.num_refs 105710359 # Number of memory references -system.cpu.workload.PROG:num_syscalls 428 # Number of system calls +system.cpu.numCycles 732870812 # number of cpu cycles simulated +system.cpu.num_insts 243835278 # Number of instructions executed +system.cpu.num_refs 105711442 # Number of memory references +system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index c59920875..000000000 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7004 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index 527f1b385..640586f7b 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=mcf mcf.in cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=55300000000 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:268435455 zero=false port=system.membus.port[0] diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 743c3e8f1..b197a138a 100644..100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -14,16 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 21:57:00 2007 -M5 executing on nacho -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 165703616000 because target called exit() +Exiting @ tick 164697191500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..412b43cf4 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 738696 # Simulator instruction rate (inst/s) +host_mem_usage 331676 # Number of bytes of host memory used +host_seconds 365.09 # Real time elapsed on the host +host_tick_rate 451120089 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.164697 # Number of seconds simulated +sim_ticks 164697191500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 329394384 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed +system.cpu.num_refs 122219131 # Number of memory references +system.cpu.workload.PROG:num_syscalls 444 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr deleted file mode 100644 index 863f1adb9..000000000 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,5 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..c34572b5c --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:268435455 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() 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+202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..160928f1d --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:36:40 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 381620498000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..cc9d82b6a --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,207 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 587866 # Simulator instruction rate (inst/s) +host_mem_usage 339232 # Number of bytes of host memory used +host_seconds 458.76 # Real time elapsed on the host +host_tick_rate 831860032 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.381620 # Number of seconds simulated +sim_ticks 381620498000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency +system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 120039828 # number of overall hits +system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2179365 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 2049944 # number of replacements +system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4079.427520 # Cycle average of tags in use +system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 127225609000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 229129 # number of writebacks +system.cpu.icache.ReadReq_accesses 217696163 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 217695356 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 269758.805452 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 217696163 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 217695356 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_misses 807 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 217696163 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 217695356 # number of overall hits +system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_misses 807 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 666.511426 # Cycle average of tags in use +system.cpu.icache.total_refs 217695356 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1950995 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 4627376000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 88988 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3559520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 88988 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 13.678221 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000.160755 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10027711000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7713600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.093846 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 192840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000.160755 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1862007 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10027711000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 192840 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7713600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 108885 # number of replacements +system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 18002.978067 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 70892 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 763240996 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed +system.cpu.num_refs 122219131 # Number of memory references +system.cpu.workload.PROG:num_syscalls 444 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 10efbab5f..dd5474f9a 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=parser 2.1.dict -batch cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=114600000000 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 727d390d0..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 830115 # Simulator instruction rate (inst/s) -host_mem_usage 150180 # Number of bytes of host memory used -host_seconds 1788.44 # Real time elapsed on the host -host_tick_rate 482678947 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1484611664 # Number of instructions simulated -sim_seconds 0.863243 # Number of seconds simulated -sim_ticks 863243462500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1726486926 # number of cpu cycles simulated -system.cpu.num_insts 1484611664 # Number of instructions executed -system.cpu.num_refs 533543283 # Number of memory references -system.cpu.workload.PROG:num_syscalls 541 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 3c6b14676..6f49cefcf 100644..100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,5 +1,20 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: ************************************************* + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** 58924 words stored in 3784810 bytes @@ -13,6 +28,8 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -57,16 +74,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 16 2008 13:01:44 -M5 started Sat Feb 16 13:01:45 2008 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 863243462500 because target called exit() +Exiting @ tick 868476152500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..a32bcd78e --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 954040 # Simulator instruction rate (inst/s) +host_mem_usage 200820 # Number of bytes of host memory used +host_seconds 1567.53 # Real time elapsed on the host +host_tick_rate 554042856 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1495482356 # Number of instructions simulated +sim_seconds 0.868476 # Number of seconds simulated +sim_ticks 868476152500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1736952306 # number of cpu cycles simulated +system.cpu.num_insts 1495482356 # Number of instructions executed +system.cpu.num_refs 533262337 # Number of memory references +system.cpu.workload.PROG:num_syscalls 551 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr deleted file mode 100644 index 46a429e22..000000000 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,8 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..87163bbc2 --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..e9b88174e --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -0,0 +1,77 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:46:46 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 1722352498000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..422faa1c9 --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,207 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 782704 # Simulator instruction rate (inst/s) +host_mem_usage 208376 # Number of bytes of host memory used +host_seconds 1910.66 # Real time elapsed on the host +host_tick_rate 901442913 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1495482356 # Number of instructions simulated +sim_seconds 1.722352 # Number of seconds simulated +sim_ticks 1722352498000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 382375369 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147694052 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 210.782575 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency +system.cpu.dcache.demand_hits 530069421 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 530069421 # number of overall hits +system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3192961 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 2513875 # number of replacements +system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4086.831321 # Cycle average of tags in use +system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8217698000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1463913 # number of writebacks +system.cpu.icache.ReadReq_accesses 1068347064 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1068344251 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 379788.215784 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1068347064 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency +system.cpu.icache.demand_hits 1068344251 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1068347064 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1068344251 # number of overall hits +system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_misses 2813 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 1253 # number of replacements +system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 886.488028 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344251 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1310104 # number of overall hits +system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1210680 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 663512 # number of replacements +system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 17216.029598 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 921771430000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 481430 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 3444704996 # number of cpu cycles simulated +system.cpu.num_insts 1495482356 # Number of instructions executed +system.cpu.num_refs 533262337 # Number of memory references +system.cpu.workload.PROG:num_syscalls 551 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 50eaa3f41..253ff4370 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr index 4bb0d9bbe..f7b481bbe 100644..100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -1,11 +1,10 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..d243310c6 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:25:10 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 3af370c7d..5e076a275 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,40 +1,36 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 37055347 # Number of BTB hits -global.BPredUnit.BTBLookups 45947414 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1096 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5691744 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 35558640 # Number of conditional branches predicted -global.BPredUnit.lookups 62480259 # Number of BP lookups -global.BPredUnit.usedRAS 12398507 # Number of times the RAS was used to get a target. -host_inst_rate 155119 # Simulator instruction rate (inst/s) -host_mem_usage 205336 # Number of bytes of host memory used -host_seconds 2421.21 # Real time elapsed on the host -host_tick_rate 55712012 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 72769124 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 54049353 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 125306666 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92782205 # Number of stores inserted to the mem dependence unit. +host_inst_rate 243217 # Simulator instruction rate (inst/s) +host_mem_usage 213460 # Number of bytes of host memory used +host_seconds 1544.20 # Real time elapsed on the host +host_tick_rate 87422028 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.134890 # Number of seconds simulated -sim_ticks 134890208500 # Number of ticks simulated +sim_seconds 0.134997 # Number of seconds simulated +sim_ticks 134996684500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 38296034 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 45834466 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 62209737 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13065530 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 254286247 +system.cpu.commit.COM:committed_per_cycle.samples 254545672 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 123470433 4855.57% - 1 49744073 1956.22% - 2 18820215 740.12% - 3 19293865 758.75% - 4 12510791 492.00% - 5 8575068 337.22% - 6 5688152 223.69% - 7 3118120 122.62% - 8 13065530 513.81% + 0 123085209 4835.49% + 1 50466868 1982.63% + 2 18758377 736.94% + 3 19955031 783.95% + 4 11844121 465.30% + 5 8478667 333.09% + 6 5819307 228.62% + 7 2974518 116.86% + 8 13163574 517.14% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,406 +39,386 @@ system.cpu.commit.COM:loads 100651995 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5687554 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 96777858 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574819 # Number of Instructions Simulated system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.718313 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.718313 # CPI: Total CPI of All Threads +system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95885180 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15194.726166 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7312.880325 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95884194 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 14982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 986 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7210500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73513083 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32019.486405 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7598.791541 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73509773 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 105984500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 7646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 25152000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40554.006943 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169398263 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 28157.937616 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169393967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 120966500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4296 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 8182 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 32362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses +system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169398263 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 28157.937616 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169393967 # number of overall hits -system.cpu.dcache.overall_miss_latency 120966500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4296 # number of overall misses -system.cpu.dcache.overall_mshr_hits 8182 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 32362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 169002312 # number of overall hits +system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses +system.cpu.dcache.overall_misses 19726 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.replacements 782 # number of replacements system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3296.858616 # Cycle average of tags in use -system.cpu.dcache.total_refs 169394087 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use +system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 636 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 18955564 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4312 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11369096 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 533723337 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 133094788 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 100949486 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15490881 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12729 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1286410 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 186077432 # DTB accesses -system.cpu.dtb.acv 11216 # DTB access violations -system.cpu.dtb.hits 186006805 # DTB hits -system.cpu.dtb.misses 70627 # DTB misses -system.cpu.dtb.read_accesses 104841123 # DTB read accesses -system.cpu.dtb.read_acv 11216 # DTB read access violations -system.cpu.dtb.read_hits 104772046 # DTB read hits -system.cpu.dtb.read_misses 69077 # DTB read misses -system.cpu.dtb.write_accesses 81236309 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 81234759 # DTB write hits -system.cpu.dtb.write_misses 1550 # DTB write misses -system.cpu.fetch.Branches 62480259 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 64020665 # Number of cache lines fetched -system.cpu.fetch.Cycles 168778939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1468351 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 547045642 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6042059 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.231597 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 64020665 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 49453854 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.027744 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 635 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 185115437 # DTB accesses +system.cpu.dtb.acv 1 # DTB access violations +system.cpu.dtb.hits 185076670 # DTB hits +system.cpu.dtb.misses 38767 # DTB misses +system.cpu.dtb.read_accesses 104449499 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 104412186 # DTB read hits +system.cpu.dtb.read_misses 37313 # DTB read misses +system.cpu.dtb.write_accesses 80665938 # DTB write accesses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_hits 80664484 # DTB write hits +system.cpu.dtb.write_misses 1454 # DTB write misses +system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched +system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 269777129 +system.cpu.fetch.rateDist.samples 269852647 system.cpu.fetch.rateDist.min_value 0 - 0 165019149 6116.87% - 1 11208105 415.46% - 2 10970042 406.63% - 3 7809028 289.46% - 4 16007682 593.37% - 5 8770390 325.10% - 6 6686429 247.85% - 7 3981315 147.58% - 8 39324989 1457.68% + 0 164102333 6081.18% + 1 12367121 458.29% + 2 12410556 459.90% + 3 6615129 245.14% + 4 15923029 590.06% + 5 8709903 322.77% + 6 6580254 243.85% + 7 4007808 148.52% + 8 39136514 1450.29% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 64020369 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9431.835687 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6021.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 64016474 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 36737000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3895 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 296 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 23455500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3895 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16435.551733 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 64020369 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9431.835687 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency -system.cpu.icache.demand_hits 64016474 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 36737000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.demand_misses 3895 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 23455500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency +system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses +system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3895 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 64020369 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9431.835687 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency +system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 64016474 # number of overall hits -system.cpu.icache.overall_miss_latency 36737000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.overall_misses 3895 # number of overall misses -system.cpu.icache.overall_mshr_hits 296 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 23455500 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 63861348 # number of overall hits +system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses +system.cpu.icache.overall_misses 4841 # number of overall misses +system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3895 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1973 # number of replacements -system.cpu.icache.sampled_refs 3895 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1975 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1826.958701 # Cycle average of tags in use -system.cpu.icache.total_refs 64016474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use +system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 3290 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 51062363 # Number of branches executed -system.cpu.iew.EXEC:nop 27214999 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.560789 # Inst execution rate -system.cpu.iew.EXEC:refs 192842691 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 81246989 # Number of stores executed +system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50976851 # Number of branches executed +system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate +system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80676625 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 287107823 # num instructions consuming a value -system.cpu.iew.WB:count 417299912 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.702706 # average fanout of values written-back +system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value +system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 201752289 # num instructions producing a value -system.cpu.iew.WB:rate 1.546813 # insts written-back per cycle -system.cpu.iew.WB:sent 418066212 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6311133 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2198946 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 125306666 # Number of dispatched load instructions +system.cpu.iew.WB:producers 200770520 # num instructions producing a value +system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle +system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6339692 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92782205 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 495443138 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111595702 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10411801 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 421070304 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 127438 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 23538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15490881 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 491568 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8710387 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3327 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 505299 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 175942 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24654671 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 19250803 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 505299 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 821714 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5489419 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.392150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.392150 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 431482105 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued - IntAlu 167002612 38.70% # Type of FU issued - IntMult 2153139 0.50% # Type of FU issued + IntAlu 166319014 38.71% # Type of FU issued + IntMult 2152935 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 34874757 8.08% # Type of FU issued - FloatCmp 7889981 1.83% # Type of FU issued - FloatCvt 2903377 0.67% # Type of FU issued - FloatMult 16803027 3.89% # Type of FU issued - FloatDiv 1591666 0.37% # Type of FU issued + FloatAdd 35077566 8.17% # Type of FU issued + FloatCmp 7830879 1.82% # Type of FU issued + FloatCvt 2898460 0.67% # Type of FU issued + FloatMult 16788316 3.91% # Type of FU issued + FloatDiv 1569716 0.37% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 114230521 26.47% # Type of FU issued - MemWrite 83999444 19.47% # Type of FU issued + MemRead 113503270 26.42% # Type of FU issued + MemWrite 83426459 19.42% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 10446664 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024211 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 32363 0.31% # attempts to use FU when none available + IntAlu 40640 0.39% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 95689 0.92% # attempts to use FU when none available - FloatCmp 7492 0.07% # attempts to use FU when none available - FloatCvt 12721 0.12% # attempts to use FU when none available - FloatMult 1683122 16.11% # attempts to use FU when none available - FloatDiv 1408746 13.49% # attempts to use FU when none available + FloatAdd 76056 0.73% # attempts to use FU when none available + FloatCmp 13381 0.13% # attempts to use FU when none available + FloatCvt 12891 0.12% # attempts to use FU when none available + FloatMult 1723474 16.48% # attempts to use FU when none available + FloatDiv 1473560 14.09% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5941492 56.87% # attempts to use FU when none available - MemWrite 1265039 12.11% # attempts to use FU when none available + MemRead 5907144 56.49% # attempts to use FU when none available + MemWrite 1209900 11.57% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 269777129 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 99508340 3688.54% - 1 57898126 2146.15% - 2 39403533 1460.60% - 3 28850583 1069.42% - 4 24598298 911.80% - 5 10625217 393.85% - 6 6146486 227.84% - 7 2145397 79.52% - 8 601149 22.28% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.599383 # Inst issue rate -system.cpu.iq.iqInstsAdded 468227900 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 431482105 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::samples 269852647 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 99465935 36.86% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 57766030 21.41% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 39984554 14.82% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 29664959 10.99% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 23966120 8.88% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 10452563 3.87% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 5712016 2.12% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 2252970 0.83% +system.cpu.iq.ISSUE:issued_per_cycle::8 587500 0.22% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 269852647 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.591981 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720906 +system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate +system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 91553989 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1306748 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68680838 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 64020959 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 63866476 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 64020665 # ITB hits -system.cpu.itb.misses 294 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 6098.591549 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3098.591549 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 19485000 # number of ReadExReq miss cycles +system.cpu.itb.hits 63866189 # ITB hits +system.cpu.itb.misses 287 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9900000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5592.080378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2592.080378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 647 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 23654500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.867336 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4230 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10964500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867336 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4230 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5698.347107 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2698.347107 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 689500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 326500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 636 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.128309 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8072 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5810.033670 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 647 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 43139500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.919846 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7425 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 20864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.919846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8072 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5810.033670 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 647 # number of overall hits -system.cpu.l2cache.overall_miss_latency 43139500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.919846 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7425 # number of overall misses +system.cpu.l2cache.overall_hits 655 # number of overall hits +system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7418 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 20864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.919846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7425 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 15 # number of replacements -system.cpu.l2cache.sampled_refs 4684 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 14 # number of replacements +system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3884.477480 # Cycle average of tags in use -system.cpu.l2cache.total_refs 601 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use +system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 269780419 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8898218 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 73961217 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54131405 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 269993372 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1493929 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 138057394 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7378387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 685335905 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 519882318 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 336260549 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96875532 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15490881 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 10098203 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 76728208 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 356901 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37939 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 22218757 # count of insts added to the skid buffer +system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed -system.cpu.timesIdled 727 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout deleted file mode 100644 index 50ed34325..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,2 +0,0 @@ -Eon, Version 1.1 -OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index bfc3d0e40..b219ea49a 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr index 56a19a708..f7b481bbe 100644..100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -1,12 +1,10 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..320d9365d --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py long/30.eon/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index e32cacf16..f57fc8170 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2526947 # Simulator instruction rate (inst/s) -host_mem_usage 181828 # Number of bytes of host memory used -host_seconds 157.77 # Real time elapsed on the host -host_tick_rate 1263471125 # Simulator tick rate (ticks/s) +host_inst_rate 3515833 # Simulator instruction rate (inst/s) +host_mem_usage 203260 # Number of bytes of host memory used +host_seconds 113.39 # Real time elapsed on the host +host_tick_rate 1757913715 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100644 index 5f057b8dd..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,2 +0,0 @@ -Eon, Version 1.1 -OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 6912167e0..86203bb88 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr index 57ac24419..f7b481bbe 100644..100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -1,12 +1,10 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..3eda1fae9 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:52 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py long/30.eon/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.566667 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index f6e3615e0..56640f3eb 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 948947 # Simulator instruction rate (inst/s) -host_mem_usage 204452 # Number of bytes of host memory used -host_seconds 420.11 # Real time elapsed on the host -host_tick_rate 1349967290 # Simulator tick rate (ticks/s) +host_inst_rate 1674592 # Simulator instruction rate (inst/s) +host_mem_usage 210700 # Number of bytes of host memory used +host_seconds 238.07 # Real time elapsed on the host +host_tick_rate 2383160323 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated -sim_seconds 0.567139 # Number of seconds simulated -sim_ticks 567138642000 # Number of ticks simulated +sim_seconds 0.567352 # Number of seconds simulated +sim_ticks 567351850000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25398.947368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22398.947368 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24129000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 21279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 89478000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 79536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,46 +37,37 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26643.292683 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 113607000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 100815000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26643.292683 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 168270956 # number of overall hits -system.cpu.dcache.overall_miss_latency 113607000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4264 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 100815000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.418113 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 73520730 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25343.588347 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22343.588347 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 93087000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 82068000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25343.588347 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 93087000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 82068000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25343.588347 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 398660993 # number of overall hits -system.cpu.icache.overall_miss_latency 93087000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 82068000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.354000 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +142,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 398664666 # ITB hits system.cpu.itb.misses 173 # ITB misses system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 73646000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35222000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 92874000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44418000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2576000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) @@ -198,51 +180,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 166520000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 79640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 585 # number of overall hits -system.cpu.l2cache.overall_miss_latency 166520000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses system.cpu.l2cache.overall_misses 7240 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 79640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 15 # number of replacements system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3714.818787 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1134277284 # number of cpu cycles simulated +system.cpu.numCycles 1134703700 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout deleted file mode 100644 index f9d497506..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,2 +0,0 @@ -Eon, Version 1.1 -OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini new file mode 100644 index 000000000..2eb72fecc --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -0,0 +1,394 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc 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+[system.cpu.fuPool.FUList7.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..01b34fd92 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(1, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..3ec2c9e61 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,1392 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:24:11 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. 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---------- +host_inst_rate 233158 # Simulator instruction rate (inst/s) +host_mem_usage 213372 # Number of bytes of host memory used +host_seconds 7818.92 # Real time elapsed on the host +host_tick_rate 90186298 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1823043370 # Number of instructions simulated +sim_seconds 0.705159 # Number of seconds simulated +sim_ticks 705159454500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 240462096 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 294213603 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 349424731 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 266706457 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 1310002800 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 603585596 4607.51% + 1 273587005 2088.45% + 2 174037133 1328.52% + 3 65399708 499.23% + 4 48333001 368.95% + 5 34003110 259.57% + 6 18481318 141.08% + 7 23715685 181.04% + 8 68860244 525.65% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 2008987604 # Number of instructions committed +system.cpu.commit.COM:loads 511595302 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 722390433 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1823043370 # Number of Instructions Simulated +system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated +system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 674038251 # number of overall hits +system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2493914 # number of overall misses +system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1526847 # number of replacements +system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use +system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74589 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 775959987 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 775335043 # DTB hits +system.cpu.dtb.misses 624944 # DTB misses +system.cpu.dtb.read_accesses 516992085 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 516404963 # DTB read hits +system.cpu.dtb.read_misses 587122 # DTB read misses +system.cpu.dtb.write_accesses 258967902 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 258930080 # DTB write hits +system.cpu.dtb.write_misses 37822 # DTB write misses +system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched +system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 1410161885 +system.cpu.fetch.rateDist.min_value 0 + 0 830588040 5890.02% + 1 53463106 379.13% + 2 39766072 282.00% + 3 63538024 450.57% + 4 121390719 860.83% + 5 35256321 250.02% + 6 38761682 274.87% + 7 6988644 49.56% + 8 220409277 1563.01% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses +system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 348437250 # number of overall hits +system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses +system.cpu.icache.overall_misses 10649 # number of overall misses +system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 8097 # number of replacements +system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use +system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 274534145 # Number of branches executed +system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate +system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258968900 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value +system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1136229268 # num instructions producing a value +system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle +system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 2752 0.00% # Type of FU issued + IntAlu 1204412678 57.64% # Type of FU issued + IntMult 17591 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 27851349 1.33% # Type of FU issued + FloatCmp 8254694 0.40% # Type of FU issued + FloatCvt 7204646 0.34% # Type of FU issued + FloatMult 4 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 557993260 26.70% # Type of FU issued + MemWrite 283770831 13.58% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 8291 0.02% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 28032977 75.57% # attempts to use FU when none available + MemWrite 9052278 24.40% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle::samples 1410161885 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 537278436 38.10% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 285217724 20.23% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 273546804 19.40% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 154810620 10.98% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 63341841 4.49% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 51438515 3.65% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 32491109 2.30% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 9036668 0.64% +system.cpu.iq.ISSUE:issued_per_cycle::8 3000168 0.21% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 1410161885 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.481750 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637343 +system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate +system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 348448092 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 348447899 # ITB hits +system.cpu.itb.misses 193 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 8187.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 8 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 65500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 28934 # number of overall hits +system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511777 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 1474251 # number of replacements +system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66899 # number of writebacks +system.cpu.memDep0.conflictingLoads 118847053 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21034746 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1410318910 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed +system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 9054cf093..4863763a5 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=perlbmk -I. -I lib lgred.makerand.pl cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..01b34fd92 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(1, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index d4a078b85..3e0584ae3 100644..100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 3a5a57719..a2839e9d4 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2579952 # Simulator instruction rate (inst/s) -host_mem_usage 180972 # Number of bytes of host memory used -host_seconds 778.69 # Real time elapsed on the host -host_tick_rate 1290253991 # Simulator tick rate (ticks/s) +host_inst_rate 3467416 # Simulator instruction rate (inst/s) +host_mem_usage 202428 # Number of bytes of host memory used +host_seconds 579.39 # Real time elapsed on the host +host_tick_rate 1734081372 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100644 index a6133a5ee..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 7985d0869..a7ffe8cab 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=perlbmk -I. -I lib lgred.makerand.pl cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..01b34fd92 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(1, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index d4a078b85..bfb6dafd6 100644..100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:29:29 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py long/40.perlbmk/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1375000: 2038431008 1374000: 3487365506 1373000: 4184770123 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 6e1f5bd66..87861b454 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1017888 # Simulator instruction rate (inst/s) -host_mem_usage 209744 # Number of bytes of host memory used -host_seconds 1973.68 # Real time elapsed on the host -host_tick_rate 1403993769 # Simulator tick rate (ticks/s) +host_inst_rate 2199489 # Simulator instruction rate (inst/s) +host_mem_usage 209876 # Number of bytes of host memory used +host_seconds 913.39 # Real time elapsed on the host +host_tick_rate 3081877276 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated -sim_seconds 2.771038 # Number of seconds simulated -sim_ticks 2771037759000 # Number of ticks simulated +sim_seconds 2.814951 # Number of seconds simulated +sim_ticks 2814951154000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26811.881426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23811.881426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 39096871000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 34722295000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.692460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.692460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2019226000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1794865000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,48 +37,39 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26821.043863 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 41116097000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 36517160000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26821.043863 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720331943 # number of overall hits -system.cpu.dcache.overall_miss_latency 41116097000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses system.cpu.dcache.overall_misses 1532979 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 36517160000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.350762 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 812770000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.dtb.accesses 722298387 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 210794896 # DTB write hits system.cpu.dtb.write_misses 14581 # DTB write misses system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 16916.289166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 13916.289166 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 179245000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147457000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 16916.289166 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 179245000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147457000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 16916.289166 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2009410475 # number of overall hits -system.cpu.icache.overall_miss_latency 179245000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147457000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.550297 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +142,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 2009421071 # ITB hits system.cpu.itb.misses 105 # ITB misses system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1654896000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 791472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 33107764000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15834148000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22813.403880 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 64676000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31185000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) @@ -198,51 +180,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 34762660000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 16625620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 29320 # number of overall hits -system.cpu.l2cache.overall_miss_latency 34762660000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses system.cpu.l2cache.overall_misses 1511420 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 16625620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 1473608 # number of replacements system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31923.721558 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66899 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5542075518 # number of cpu cycles simulated +system.cpu.numCycles 5629902308 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr deleted file mode 100644 index fc28a8ff6..000000000 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,5 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 0, ...) -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index fcea1b656..2927f396f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..3c4f7e5f4 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:23:18 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 3829dd799..c3cb349a5 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,40 +1,36 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8028209 # Number of BTB hits -global.BPredUnit.BTBLookups 14249713 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35529 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 455745 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10549276 # Number of conditional branches predicted -global.BPredUnit.lookups 16239906 # Number of BP lookups -global.BPredUnit.usedRAS 1939086 # Number of times the RAS was used to get a target. -host_inst_rate 101925 # Simulator instruction rate (inst/s) -host_mem_usage 220292 # Number of bytes of host memory used -host_seconds 780.89 # Real time elapsed on the host -host_tick_rate 32150232 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12312682 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 10887004 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 22965315 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16290741 # Number of stores inserted to the mem dependence unit. +host_inst_rate 261905 # Simulator instruction rate (inst/s) +host_mem_usage 216920 # Number of bytes of host memory used +host_seconds 303.90 # Real time elapsed on the host +host_tick_rate 89289765 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.025106 # Number of seconds simulated -sim_ticks 25105678500 # Number of ticks simulated +sim_seconds 0.027135 # Number of seconds simulated +sim_ticks 27134794500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 8039250 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14256744 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 16249463 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3423734 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 48941983 +system.cpu.commit.COM:committed_per_cycle.samples 51751168 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 20096984 4106.29% - 1 10996856 2246.92% - 2 5104227 1042.91% - 3 3459002 706.76% - 4 2556441 522.34% - 5 1507300 307.98% - 6 975853 199.39% - 7 821586 167.87% - 8 3423734 699.55% + 0 22506445 4348.97% + 1 11357579 2194.65% + 2 5114502 988.29% + 3 3560855 688.07% + 4 2552504 493.23% + 5 1532717 296.17% + 6 1008933 194.96% + 7 796739 153.96% + 8 3320894 641.70% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,266 +39,248 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 360068 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8053439 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.630861 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630861 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20369036 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19244.510005 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4564.311373 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20307515 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1183941500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 61521 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 83859 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 280801000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61521 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 13753160 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 50456.177120 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7344.479005 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13603341 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7559294000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010893 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 149819 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 860217 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1100342500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010893 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149819 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.441832 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34122196 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41370.471752 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33910856 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8743235500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006194 # miss rate for demand accesses -system.cpu.dcache.demand_misses 211340 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 944076 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1381143500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211340 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34122196 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41370.471752 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33910856 # number of overall hits -system.cpu.dcache.overall_miss_latency 8743235500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006194 # miss rate for overall accesses -system.cpu.dcache.overall_misses 211340 # number of overall misses -system.cpu.dcache.overall_mshr_hits 944076 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1381143500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006194 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211340 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33838925 # number of overall hits +system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1199965 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200914 # number of replacements -system.cpu.dcache.sampled_refs 205010 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200933 # number of replacements +system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.749840 # Cycle average of tags in use -system.cpu.dcache.total_refs 33917230 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 125269000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147756 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1159763 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 96488 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3648673 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101620182 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28148001 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19589576 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1262270 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284391 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 44644 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36627367 # DTB accesses +system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use +system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147760 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36599689 # DTB accesses system.cpu.dtb.acv 39 # DTB access violations -system.cpu.dtb.hits 36456086 # DTB hits -system.cpu.dtb.misses 171281 # DTB misses -system.cpu.dtb.read_accesses 21562223 # DTB read accesses +system.cpu.dtb.hits 36425481 # DTB hits +system.cpu.dtb.misses 174208 # DTB misses +system.cpu.dtb.read_accesses 21541288 # DTB read accesses system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21405571 # DTB read hits -system.cpu.dtb.read_misses 156652 # DTB read misses -system.cpu.dtb.write_accesses 15065144 # DTB write accesses +system.cpu.dtb.read_hits 21383020 # DTB read hits +system.cpu.dtb.read_misses 158268 # DTB read misses +system.cpu.dtb.write_accesses 15058401 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15050515 # DTB write hits -system.cpu.dtb.write_misses 14629 # DTB write misses -system.cpu.fetch.Branches 16239906 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13373612 # Number of cache lines fetched -system.cpu.fetch.Cycles 33209884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 156374 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103204931 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 573221 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.323431 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13373612 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9967295 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.055410 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 15042461 # DTB write hits +system.cpu.dtb.write_misses 15940 # DTB write misses +system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched +system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 50204254 +system.cpu.fetch.rateDist.samples 53041270 system.cpu.fetch.rateDist.min_value 0 - 0 30393344 6053.94% - 1 1855009 369.49% - 2 1535971 305.94% - 3 1792342 357.01% - 4 4000264 796.80% - 5 1878750 374.22% - 6 697475 138.93% - 7 1087494 216.61% - 8 6963605 1387.05% + 0 33206277 6260.46% + 1 1871594 352.86% + 2 1529415 288.34% + 3 1809626 341.17% + 4 3985239 751.35% + 5 1867239 352.04% + 6 695846 131.19% + 7 1111736 209.60% + 8 6964298 1313.00% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13372459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5833.169458 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2760.964989 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13287028 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 498333500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006389 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 85431 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 235872000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006389 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85431 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 155.531172 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13372459 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5833.169458 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency -system.cpu.icache.demand_hits 13287028 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 498333500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006389 # miss rate for demand accesses -system.cpu.icache.demand_misses 85431 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 235872000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006389 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85431 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses +system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13372459 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5833.169458 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency +system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13287028 # number of overall hits -system.cpu.icache.overall_miss_latency 498333500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006389 # miss rate for overall accesses -system.cpu.icache.overall_misses 85431 # number of overall misses -system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 235872000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006389 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85431 # number of overall MSHR misses +system.cpu.icache.overall_hits 13297366 # number of overall hits +system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses +system.cpu.icache.overall_misses 88706 # number of overall misses +system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83382 # number of replacements -system.cpu.icache.sampled_refs 85430 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83888 # number of replacements +system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1922.332648 # Cycle average of tags in use -system.cpu.icache.total_refs 13287028 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 21794210000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use +system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7104 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14739955 # Number of branches executed -system.cpu.iew.EXEC:nop 9377104 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.689247 # Inst execution rate -system.cpu.iew.EXEC:refs 36969517 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15298022 # Number of stores executed +system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14745486 # Number of branches executed +system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate +system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291392 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42338801 # num instructions consuming a value -system.cpu.iew.WB:count 84336475 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765870 # average fanout of values written-back +system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value +system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32426009 # num instructions producing a value -system.cpu.iew.WB:rate 1.679629 # insts written-back per cycle -system.cpu.iew.WB:sent 84568976 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 400439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 20274 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 22965315 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 357828 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16290741 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98799135 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21671495 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539331 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84819374 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2040 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32396987 # num instructions producing a value +system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle +system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 162 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1262270 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 2540 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 951318 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 20550 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1303 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2585916 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1446122 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 20550 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 108250 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 292189 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.585135 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.585135 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85358705 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 47875288 56.09% # Type of FU issued - IntMult 42930 0.05% # Type of FU issued + IntAlu 47898565 56.12% # Type of FU issued + IntMult 42953 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 121387 0.14% # Type of FU issued - FloatCmp 87 0.00% # Type of FU issued - FloatCvt 121941 0.14% # Type of FU issued - FloatMult 50 0.00% # Type of FU issued - FloatDiv 38534 0.05% # Type of FU issued + FloatAdd 121655 0.14% # Type of FU issued + FloatCmp 88 0.00% # Type of FU issued + FloatCvt 122104 0.14% # Type of FU issued + FloatMult 53 0.00% # Type of FU issued + FloatDiv 38535 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21778158 25.51% # Type of FU issued - MemWrite 15380330 18.02% # Type of FU issued + MemRead 21753622 25.49% # Type of FU issued + MemWrite 15368770 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 989684 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011594 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 96046 9.70% # attempts to use FU when none available + IntAlu 97100 9.91% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -311,138 +289,136 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 442273 44.69% # attempts to use FU when none available - MemWrite 451365 45.61% # attempts to use FU when none available + MemRead 470602 48.04% # attempts to use FU when none available + MemWrite 411938 42.05% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 50204254 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 15297066 3046.97% - 1 13336776 2656.50% - 2 8168141 1626.98% - 3 4718425 939.85% - 4 4728752 941.90% - 5 2063960 411.11% - 6 1191217 237.27% - 7 451074 89.85% - 8 248843 49.57% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.699988 # Inst issue rate -system.cpu.iq.iqInstsAdded 89417045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85358705 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9619776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 47402 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6577473 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 13398974 # ITB accesses +system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% +system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333 +system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate +system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13412237 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 13373612 # ITB hits -system.cpu.itb.misses 25362 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5477.120197 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2477.120197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 785906500 # number of ReadExReq miss cycles +system.cpu.itb.hits 13386072 # ITB hits +system.cpu.itb.misses 26165 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143489 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 355439500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143489 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 146952 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5163.421419 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2163.421419 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 102374 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 230175000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.303351 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 96441000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303351 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44578 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6345 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5226.319937 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2257.919622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 33161000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6345 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14326500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6345 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147756 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147756 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.675694 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5402.763377 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 102374 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1016081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.647522 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 188067 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 451880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.647522 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 188067 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5402.763377 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 102374 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1016081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.647522 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 188067 # number of overall misses +system.cpu.l2cache.overall_hits 102894 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188071 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 451880500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.647522 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 188067 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 148782 # number of replacements -system.cpu.l2cache.sampled_refs 173999 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148779 # number of replacements +system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18435.407852 # Cycle average of tags in use -system.cpu.l2cache.total_refs 117570 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use +system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120646 # number of writebacks -system.cpu.numCycles 50211358 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 378329 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120647 # number of writebacks +system.cpu.memDep0.conflictingLoads 12835812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11558188 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 54269590 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 33543 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28456807 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 636231 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 121456625 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100818725 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60666627 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19319540 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1262270 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 711864 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8119746 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 75444 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5250 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1518293 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5248 # count of temporary serializing insts renamed -system.cpu.timesIdled 2224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed +system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr deleted file mode 100644 index 8053728f7..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 4745ee94c..5a410e8c9 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..7f58d408c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:31:50 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py long/50.vortex/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index f06392b4f..3b23e3386 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2496642 # Simulator instruction rate (inst/s) -host_mem_usage 184388 # Number of bytes of host memory used -host_seconds 35.38 # Real time elapsed on the host -host_tick_rate 1249741953 # Simulator tick rate (ticks/s) +host_inst_rate 5386925 # Simulator instruction rate (inst/s) +host_mem_usage 205832 # Number of bytes of host memory used +host_seconds 16.40 # Real time elapsed on the host +host_tick_rate 2696520513 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100644 index f33d007a7..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100644 index e69de29bb..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 2aab198c9..74756cd76 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..9806a0cdd --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:32:07 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py long/50.vortex/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 068d99b92..66817a603 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,84 +1,75 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 866615 # Simulator instruction rate (inst/s) -host_mem_usage 218536 # Number of bytes of host memory used -host_seconds 101.94 # Real time elapsed on the host -host_tick_rate 1271060462 # Simulator tick rate (ticks/s) +host_inst_rate 2514121 # Simulator instruction rate (inst/s) +host_mem_usage 213276 # Number of bytes of host memory used +host_seconds 35.14 # Real time elapsed on the host +host_tick_rate 3846798027 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.129569 # Number of seconds simulated -sim_ticks 129569130000 # Number of ticks simulated +sim_seconds 0.135169 # Number of seconds simulated +sim_ticks 135168766000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21389.665103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18389.665103 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1299743000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1117448000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.752992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.752992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4044374000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3594995000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5344117000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses -system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4712443000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 5344117000 # number of overall miss cycles +system.cpu.dcache.overall_hits 34679456 # number of overall hits +system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses -system.cpu.dcache.overall_misses 210558 # number of overall misses +system.cpu.dcache.overall_misses 210559 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4712443000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200247 # number of replacements -system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200248 # number of replacements +system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.797262 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 750583000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15489.023497 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12489.023497 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1183919000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 954611000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1183919000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 954611000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1183919000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 954611000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1876.637848 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,89 +142,80 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 88438074 # ITB hits system.cpu.itb.misses 3934 # ITB misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3302294000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 995808000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22863.073210 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 142094000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.630834 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4298102000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2055614000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4298102000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186874 # number of overall misses +system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 186875 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2055614000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 147560 # number of replacements -system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147561 # number of replacements +system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18265.835561 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259138260 # number of cpu cycles simulated +system.cpu.numCycles 270337532 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr deleted file mode 100644 index 26249ed90..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout deleted file mode 100644 index e69de29bb..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ /dev/null diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 973d6211f..5b764e1f0 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=vortex bendian.raw cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..b33f4f1d5 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,1125 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall time(4026527848, 4026528248, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527400, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527312, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 413, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 414, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527288, 4026527688, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526840, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526960, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527040, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527000, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526312, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526832, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526840, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526936, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527008, 4026527408, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526560, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527184, 18732, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526632, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526736, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527744, 225, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527096, 4026527496, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526648, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526824, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527184, 1879089152, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 1595768, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026525968, 20500, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026525968, 4026526436, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526056, 7004192, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527512, 4, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026525760, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..95b7d967f --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:53:28 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py long/50.vortex/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index d8596d3fc..be8f1d320 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3368510 # Simulator instruction rate (inst/s) -host_mem_usage 185484 # Number of bytes of host memory used -host_seconds 40.42 # Real time elapsed on the host -host_tick_rate 1686201794 # Simulator tick rate (ticks/s) +host_inst_rate 3821272 # Simulator instruction rate (inst/s) +host_mem_usage 206688 # Number of bytes of host memory used +host_seconds 35.63 # Real time elapsed on the host +host_tick_rate 1912846403 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index bc4f4d822..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,564 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7013 -warn: Entering event queue @ 0. Starting simulation... -warn: ignoring syscall time(4026527848, 4026528248, ...) -warn: ignoring syscall time(4026527400, 1375098, ...) -warn: ignoring syscall time(4026527312, 1, ...) -warn: ignoring syscall time(4026527048, 413, ...) -warn: ignoring syscall time(4026527048, 414, ...) -warn: ignoring syscall time(4026527288, 4026527688, ...) -warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526960, 409, ...) -warn: ignoring syscall time(4026527040, 409, ...) -warn: ignoring syscall time(4026527000, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526312, 19045, ...) -warn: ignoring syscall time(4026526832, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526840, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526936, 409, ...) -warn: ignoring syscall time(4026527008, 4026527408, ...) -warn: ignoring syscall time(4026526560, 1375098, ...) -warn: ignoring syscall time(4026527184, 18732, ...) -warn: ignoring syscall time(4026526632, 409, ...) -warn: ignoring syscall time(4026526736, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527744, 225, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026527096, 4026527496, ...) -warn: ignoring syscall time(4026526648, 1375098, ...) -warn: ignoring syscall time(4026526824, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527184, 1879089152, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall 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times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall time(4026527472, 1595768, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026525968, 20500, ...) -warn: ignoring syscall time(4026525968, 4026526436, ...) -warn: ignoring syscall time(4026526056, 7004192, ...) -warn: ignoring syscall time(4026527512, 4, ...) -warn: ignoring syscall time(4026525760, 0, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout deleted file mode 100644 index 0a780ccee..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 01fab79ce..4e4bcb117 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=vortex bendian.raw cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..b33f4f1d5 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,1125 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall time(4026527848, 4026528248, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527400, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527312, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 413, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 414, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527288, 4026527688, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526840, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526960, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527040, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527000, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526984, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526312, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526832, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526840, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526848, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526936, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527008, 4026527408, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526560, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527184, 18732, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526632, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526736, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527744, 225, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527048, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526856, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526872, 409, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527096, 4026527496, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526648, 1375098, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526824, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527320, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527184, 1879089152, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall times(4026527728, 246, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 1595768, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527472, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 19045, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526912, 17300, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026525968, 20500, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026525968, 4026526436, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026526056, 7004192, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026527512, 4, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall time(4026525760, 0, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..397f2cd80 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 203376692000 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 89c35043c..24dff0498 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 809753 # Simulator instruction rate (inst/s) -host_mem_usage 216324 # Number of bytes of host memory used -host_seconds 168.12 # Real time elapsed on the host -host_tick_rate 1194295397 # Simulator tick rate (ticks/s) +host_inst_rate 1347607 # Simulator instruction rate (inst/s) +host_mem_usage 214288 # Number of bytes of host memory used +host_seconds 101.02 # Real time elapsed on the host +host_tick_rate 2013168641 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.200790 # Number of seconds simulated -sim_ticks 200790381000 # Number of ticks simulated +sim_seconds 0.203377 # Number of seconds simulated +sim_ticks 203376692000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21620.738917 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18620.738917 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 983722000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 847225000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.835474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.835474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2953917000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2625702000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,196 +47,169 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25419.866498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3937639000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3472927000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25419.866498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57940701 # number of overall hits -system.cpu.dcache.overall_miss_latency 3937639000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses system.cpu.dcache.overall_misses 154904 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3472927000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.002644 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 600016000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107271 # number of writebacks -system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14908.771067 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11908.771067 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2788298000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses +system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107279 # number of writebacks +system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2227226000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14908.771067 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency -system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2788298000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses +system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency +system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2227226000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14908.771067 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency +system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 136106788 # number of overall hits -system.cpu.icache.overall_miss_latency 2788298000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses +system.cpu.icache.overall_hits 134366560 # number of overall hits +system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2227226000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2006.709249 # Cycle average of tags in use -system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 143009204000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 2004.715107 # Cycle average of tags in use +system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 144812317000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2419117000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 914158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 437206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22902.953586 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 97704000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107279 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.433874 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3333275000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1594175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 192777 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3333275000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses system.cpu.l2cache.overall_misses 144925 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1594175000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 120486 # number of replacements -system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 120487 # number of replacements +system.cpu.l2cache.sampled_refs 139197 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19341.325901 # Cycle average of tags in use -system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 19319.562378 # Cycle average of tags in use +system.cpu.l2cache.total_refs 199591 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 87413 # number of writebacks +system.cpu.l2cache.writebacks 87414 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 401580762 # number of cpu cycles simulated +system.cpu.numCycles 406753384 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index b5ea49da4..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,564 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 -warn: Entering event queue @ 0. Starting simulation... -warn: ignoring syscall time(4026527848, 4026528248, ...) -warn: ignoring syscall time(4026527400, 1375098, ...) -warn: ignoring syscall time(4026527312, 1, ...) -warn: ignoring syscall time(4026527048, 413, ...) -warn: ignoring syscall time(4026527048, 414, ...) -warn: ignoring syscall time(4026527288, 4026527688, ...) -warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526960, 409, ...) -warn: ignoring syscall time(4026527040, 409, ...) -warn: ignoring syscall time(4026527000, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526312, 19045, ...) -warn: ignoring syscall time(4026526832, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526840, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526936, 409, ...) -warn: ignoring syscall time(4026527008, 4026527408, ...) -warn: ignoring syscall time(4026526560, 1375098, ...) -warn: ignoring syscall time(4026527184, 18732, ...) -warn: ignoring syscall time(4026526632, 409, ...) -warn: ignoring syscall time(4026526736, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527744, 225, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026527096, 4026527496, ...) -warn: ignoring syscall time(4026526648, 1375098, ...) -warn: ignoring syscall time(4026526824, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527184, 1879089152, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall 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times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall time(4026527472, 1595768, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026525968, 20500, ...) -warn: ignoring syscall time(4026525968, 4026526436, ...) -warn: ignoring syscall time(4026526056, 7004192, ...) -warn: ignoring syscall time(4026527512, 4, ...) -warn: ignoring syscall time(4026525760, 0, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout deleted file mode 100644 index 5b4fb94a9..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:46 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 200790381000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 966f49abc..7014f9608 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=bzip2 input.source 1 cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..644c3eb5c --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,30 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:18:05 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d545db111..16f472fdf 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,40 +1,36 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 298925307 # Number of BTB hits -global.BPredUnit.BTBLookups 307254403 # Number of BTB lookups -global.BPredUnit.RASInCorrect 123 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19461333 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 256954278 # Number of conditional branches predicted -global.BPredUnit.lookups 332748805 # Number of BP lookups -global.BPredUnit.usedRAS 23332154 # Number of times the RAS was used to get a target. -host_inst_rate 185907 # Simulator instruction rate (inst/s) -host_mem_usage 374916 # Number of bytes of host memory used -host_seconds 9338.25 # Real time elapsed on the host -host_tick_rate 70823738 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 73213571 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 37308198 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 599919223 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 223513381 # Number of stores inserted to the mem dependence unit. +host_inst_rate 226973 # Simulator instruction rate (inst/s) +host_mem_usage 205820 # Number of bytes of host memory used +host_seconds 7648.67 # Real time elapsed on the host +host_tick_rate 97050740 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.661370 # Number of seconds simulated -sim_ticks 661369625500 # Number of ticks simulated +sim_seconds 0.742309 # Number of seconds simulated +sim_ticks 742309425500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 312845737 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 319575559 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 345502589 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 64339411 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1246869641 +system.cpu.commit.COM:committed_per_cycle.samples 1379215338 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 606206692 4861.83% - 1 260350579 2088.03% - 2 123843780 993.24% - 3 79587483 638.30% - 4 49145226 394.15% - 5 29422011 235.97% - 6 23247922 186.45% - 7 10726537 86.03% - 8 64339411 516.01% + 0 736540830 5340.29% + 1 260049504 1885.49% + 2 126970462 920.60% + 3 77723426 563.53% + 4 51327439 372.15% + 5 27759546 201.27% + 6 26179568 189.81% + 7 9881978 71.65% + 8 62782585 455.21% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,274 +39,256 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19460831 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19646824 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 498311436 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 627314235 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.761927 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.761927 # CPI: Total CPI of All Threads +system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.855174 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 9500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 6500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 9500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 6500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 513272040 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8025.908244 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3665.501336 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 505997425 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 58385392500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.014173 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7274615 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1427526 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 26665111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014173 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7274615 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 158750545 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19340.801620 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10117.659004 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 156501908 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 43490442133 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.014165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2248637 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1977957 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 22750942389 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.014165 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2248637 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2040.681665 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2667.920935 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 72.369821 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 71409 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 65111 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 145723037 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 173711000 # number of cycles access was blocked +system.cpu.dcache.ReadReq_accesses 523259964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 512954316 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 174039645000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 10305648 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3030509 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7275139 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 155297498 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 184204379594 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5431004 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 672022585 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 10697.588873 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency -system.cpu.dcache.demand_hits 662499333 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 101875834633 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.014171 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9523252 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3405483 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 49416053389 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014171 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9523252 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668251814 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 358244024594 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses +system.cpu.dcache.demand_misses 15736652 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6212986 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 165511176193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9523666 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 672022585 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 10697.588873 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 662499333 # number of overall hits -system.cpu.dcache.overall_miss_latency 101875834633 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.014171 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9523252 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3405483 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 49416053389 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014171 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9523252 # number of overall MSHR misses +system.cpu.dcache.overall_hits 668251814 # number of overall hits +system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses +system.cpu.dcache.overall_misses 15736652 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6212986 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 165511176193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9155291 # number of replacements -system.cpu.dcache.sampled_refs 9159387 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9155775 # number of replacements +system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.377148 # Cycle average of tags in use -system.cpu.dcache.total_refs 662863201 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6956358000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245548 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 25695554 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 564 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 51842469 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2704061258 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 689853878 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 528999718 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 75857193 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1673 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2320492 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 762597100 # DTB accesses +system.cpu.dcache.tagsinuse 4079.315794 # Cycle average of tags in use +system.cpu.dcache.total_refs 669159251 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245449 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 98604488 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2810650778 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 726334611 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 549143104 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 768331639 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 747387018 # DTB hits -system.cpu.dtb.misses 15210082 # DTB misses -system.cpu.dtb.read_accesses 561654782 # DTB read accesses +system.cpu.dtb.hits 752318838 # DTB hits +system.cpu.dtb.misses 16012801 # DTB misses +system.cpu.dtb.read_accesses 566617551 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 552717840 # DTB read hits -system.cpu.dtb.read_misses 8936942 # DTB read misses -system.cpu.dtb.write_accesses 200942318 # DTB write accesses +system.cpu.dtb.read_hits 557381525 # DTB read hits +system.cpu.dtb.read_misses 9236026 # DTB read misses +system.cpu.dtb.write_accesses 201714088 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 194669178 # DTB write hits -system.cpu.dtb.write_misses 6273140 # DTB write misses -system.cpu.fetch.Branches 332748805 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 340572268 # Number of cache lines fetched -system.cpu.fetch.Cycles 882406365 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 8482299 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2756699547 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 26531665 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.251560 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 340572268 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 322257461 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.084084 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 194937313 # DTB write hits +system.cpu.dtb.write_misses 6776775 # DTB write misses +system.cpu.fetch.Branches 345502589 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 355180518 # Number of cache lines fetched +system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1322726835 +system.cpu.fetch.rateDist.samples 1472299541 system.cpu.fetch.rateDist.min_value 0 - 0 780892776 5903.66% - 1 46232823 349.53% - 2 32110220 242.76% - 3 49083369 371.08% - 4 120415668 910.36% - 5 67469038 510.08% - 6 46013556 347.87% - 7 40168101 303.68% - 8 140341284 1061.00% + 0 907273323 6162.29% + 1 47886355 325.25% + 2 34613456 235.10% + 3 52095475 353.84% + 4 125971058 855.61% + 5 69335096 470.93% + 6 50458684 342.72% + 7 40993758 278.43% + 8 143672336 975.84% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 340572130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 10589.900111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6758.046615 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 340571229 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 9541500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 355179284 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 138 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 377992.485017 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 340572130 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 10589.900111 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency -system.cpu.icache.demand_hits 340571229 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 9541500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency +system.cpu.icache.demand_hits 355179284 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 901 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 138 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 31989000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 340572130 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 10589.900111 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency +system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 340571229 # number of overall hits -system.cpu.icache.overall_miss_latency 9541500 # number of overall miss cycles +system.cpu.icache.overall_hits 355179284 # number of overall hits +system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 901 # number of overall misses -system.cpu.icache.overall_mshr_hits 138 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6089000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1234 # number of overall misses +system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 31989000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 708.208043 # Cycle average of tags in use -system.cpu.icache.total_refs 340571229 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 711.425375 # Cycle average of tags in use +system.cpu.icache.total_refs 355179284 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12417 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 272957078 # Number of branches executed -system.cpu.iew.EXEC:nop 123939642 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.684042 # Inst execution rate -system.cpu.iew.EXEC:refs 763895221 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 201165010 # Number of stores executed +system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 282186314 # Number of branches executed +system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate +system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 201925301 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1488939134 # num instructions consuming a value -system.cpu.iew.WB:count 2188676291 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.814314 # average fanout of values written-back +system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value +system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1212463676 # num instructions producing a value -system.cpu.iew.WB:rate 1.654654 # insts written-back per cycle -system.cpu.iew.WB:sent 2210006196 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21034553 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251453 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 599919223 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 23371349 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 223513381 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2521543989 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 562730211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 40765112 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2227547936 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 36991 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1243717865 # num instructions producing a value +system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle +system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5661 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 75857193 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 176880 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 93084202 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 196633 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 37920789 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 331554 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 439987 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 154252862 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 62608399 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 439987 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 706308 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20328245 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.312461 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.312461 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2268313048 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 175942074 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 73141240 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1489479679 65.66% # Type of FU issued - IntMult 80 0.00% # Type of FU issued + IntAlu 1532920254 66.19% # Type of FU issued + IntMult 99 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 221 0.00% # Type of FU issued - FloatCmp 17 0.00% # Type of FU issued + FloatAdd 234 0.00% # Type of FU issued + FloatCmp 20 0.00% # Type of FU issued FloatCvt 143 0.00% # Type of FU issued - FloatMult 14 0.00% # Type of FU issued + FloatMult 16 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 574434192 25.32% # Type of FU issued - MemWrite 204398678 9.01% # Type of FU issued + MemRead 577889733 24.95% # Type of FU issued + MemWrite 205034377 8.85% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 16429831 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007243 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2410991 14.67% # attempts to use FU when none available + IntAlu 2738956 19.03% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -319,139 +297,136 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 10617024 64.62% # attempts to use FU when none available - MemWrite 3401816 20.71% # attempts to use FU when none available + MemRead 9224843 64.09% # attempts to use FU when none available + MemWrite 2429770 16.88% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1322726835 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 474192746 3584.96% - 1 247291499 1869.56% - 2 221816340 1676.96% - 3 137127863 1036.71% - 4 113209815 855.88% - 5 74495950 563.20% - 6 43530199 329.09% - 7 8994308 68.00% - 8 2068115 15.64% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.714860 # Inst issue rate -system.cpu.iq.iqInstsAdded 2397604305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2268313048 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 649290621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 732371 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 261741042 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 340572306 # ITB accesses +system.cpu.iq.ISSUE:issued_per_cycle::samples 1472299541 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% +system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 +system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate +system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 355180552 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 340572268 # ITB hits -system.cpu.itb.misses 38 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1884772 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5864.888697 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2864.888697 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 11053978000 # number of ReadExReq miss cycles +system.cpu.itb.hits 355180518 # ITB hits +system.cpu.itb.misses 34 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 65231013432 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1884772 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5399662000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1884731 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1884772 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7275516 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5386.307802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2386.307802 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5387207 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 10171013500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.259543 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1888309 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4506086500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1888309 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 363870 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5746.245912 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2753.549345 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2090886500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7276042 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5387454 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 363811 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.098007 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459167 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 12488575853 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 363870 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1001934000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 363811 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373262721 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 363870 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245548 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2245548 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.418060 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9160288 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5625.373932 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5387207 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21224991500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.411895 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3773081 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5387454 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9905748500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.411895 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3773081 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 118102234388 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.411900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3773319 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9160288 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5625.373932 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5387207 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21224991500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411895 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3773081 # number of overall misses +system.cpu.l2cache.overall_hits 5387454 # number of overall hits +system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3773319 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9905748500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411895 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3773081 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 118102234388 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2759208 # number of replacements -system.cpu.l2cache.sampled_refs 2783806 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2759426 # number of replacements +system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25817.282629 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6731411 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 140102368000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1195679 # number of writebacks -system.cpu.numCycles 1322739252 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 10423216 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 25902.034914 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1195718 # number of writebacks +system.cpu.memDep0.conflictingLoads 127392983 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 67515291 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 234046222 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1484618852 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 3385420 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 705442707 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9460872 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 157269 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3423780434 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2645446907 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1985349974 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 515854810 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 75857193 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 15148388 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 609147011 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 521 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 744648238 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 20682075 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3556218340 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2749142928 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2059304862 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 535957522 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 93084202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 30265720 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 683101899 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 33326787 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 60936722 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.timesIdled 4373 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr deleted file mode 100644 index 256a7f3be..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout deleted file mode 100644 index 0c5c00118..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 378e34da6..0a457f545 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=bzip2 input.source 1 cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..6942bb9c6 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,30 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:32:58 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py long/60.bzip2/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index ac280ef36..8b9cdfecf 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2729023 # Simulator instruction rate (inst/s) -host_mem_usage 174164 # Number of bytes of host memory used -host_seconds 666.82 # Real time elapsed on the host -host_tick_rate 1369458693 # Simulator tick rate (ticks/s) +host_inst_rate 3629734 # Simulator instruction rate (inst/s) +host_mem_usage 195600 # Number of bytes of host memory used +host_seconds 501.35 # Real time elapsed on the host +host_tick_rate 1821446907 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100644 index d0a887867..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100644 index 0c5c00118..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,14 +0,0 @@ -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 6adec3b74..c29e7b8cc 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=bzip2 input.source 1 cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..2a7a491ad --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,30 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:36:09 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py long/60.bzip2/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 69139eb9a..b4009b3e6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1098189 # Simulator instruction rate (inst/s) -host_mem_usage 373972 # Number of bytes of host memory used -host_seconds 1657.07 # Real time elapsed on the host -host_tick_rate 1574114309 # Simulator tick rate (ticks/s) +host_inst_rate 2148631 # Simulator instruction rate (inst/s) +host_mem_usage 203048 # Number of bytes of host memory used +host_seconds 846.95 # Real time elapsed on the host +host_tick_rate 3220962828 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.608424 # Number of seconds simulated -sim_ticks 2608424230000 # Number of ticks simulated +sim_seconds 2.727991 # Number of seconds simulated +sim_ticks 2727990505000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 17373.778213 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14373.778213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 125480619000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 103813377000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.842958 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.842958 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 60690301000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 53946895000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,48 +37,39 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 19658.571674 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 186170920000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 157760272000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 19658.571674 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 186170920000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses system.cpu.dcache.overall_misses 9470216 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 157760272000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.381693 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40744129000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.dtb.accesses 611922547 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 160728502 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 21654000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 19248000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 21654000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 19248000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1826377708 # number of overall hits -system.cpu.icache.overall_miss_latency 21654000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 19248000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.562745 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +142,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 1826378510 # ITB hits system.cpu.itb.misses 18 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 43454360000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 20782520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 43128979000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 20626903000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22977.351722 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 8236967000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) @@ -198,51 +180,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 86583339000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 41409423000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5348043 # number of overall hits -system.cpu.l2cache.overall_miss_latency 86583339000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses system.cpu.l2cache.overall_misses 3764493 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 41409423000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 2751986 # number of replacements system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25389.772813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 574940849000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1194738 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5216848460 # number of cpu cycles simulated +system.cpu.numCycles 5455981010 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr deleted file mode 100644 index 0efe6eafa..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout deleted file mode 100644 index 0c5c00118..000000000 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 322bfab4b..5ffe1d191 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=bzip2 input.source 1 cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 1a0378ca6..66e6ec11e 100644..100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,7 +1,24 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:48:10 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -12,16 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 22:20:45 2007 -M5 executing on nacho -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2806436542000 because target called exit() +Exiting @ tick 2829164056000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 03017061d..a2ce3d743 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1084871 # Simulator instruction rate (inst/s) -host_mem_usage 175684 # Number of bytes of host memory used -host_seconds 4236.15 # Real time elapsed on the host -host_tick_rate 662497504 # Simulator tick rate (ticks/s) +host_inst_rate 1367500 # Simulator instruction rate (inst/s) +host_mem_usage 197040 # Number of bytes of host memory used +host_seconds 3402.69 # Real time elapsed on the host +host_tick_rate 831449663 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4595672201 # Number of instructions simulated -sim_seconds 2.806437 # Number of seconds simulated -sim_ticks 2806436542000 # Number of ticks simulated +sim_insts 4653176258 # Number of instructions simulated +sim_seconds 2.829164 # Number of seconds simulated +sim_ticks 2829164056000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5612873085 # number of cpu cycles simulated -system.cpu.num_insts 4595672201 # Number of instructions executed -system.cpu.num_refs 1686312529 # Number of memory references -system.cpu.workload.PROG:num_syscalls 33 # Number of system calls +system.cpu.numCycles 5658328113 # number of cpu cycles simulated +system.cpu.num_insts 4653176258 # Number of instructions executed +system.cpu.num_refs 1677713078 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr deleted file mode 100644 index 46a429e22..000000000 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,8 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..4d80734e6 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..bdea83ec4 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:30:32 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 5988064029000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..55231f8a8 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,207 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 929786 # Simulator instruction rate (inst/s) +host_mem_usage 204596 # Number of bytes of host memory used +host_seconds 5004.56 # Real time elapsed on the host +host_tick_rate 1196520405 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4653176258 # Number of instructions simulated +sim_seconds 5.988064 # Number of seconds simulated +sim_ticks 5988064029000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1668242528 # number of overall hits +system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9470550 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 9108982 # number of replacements +system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4084.778559 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 58863922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244013 # number of writebacks +system.cpu.icache.ReadReq_accesses 4013232881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4013232206 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 5945529.194074 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 4013232881 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 4013232206 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 675 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 4013232881 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 4013232206 # number of overall hits +system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 675 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 10 # number of replacements +system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 555.573306 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232206 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5328546 # number of overall hits +system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3785207 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 2772128 # number of replacements +system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 25742.940427 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4737814303000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1199171 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 11976128058 # number of cpu cycles simulated +system.cpu.num_insts 4653176258 # Number of instructions executed +system.cpu.num_refs 1677713078 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index a81a73367..6fbd6e595 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=twolf smred cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..4f595ede7 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,29 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:16:08 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124
\ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 2580b06c8..21c5777d8 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,40 +1,36 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13021521 # Number of BTB hits -global.BPredUnit.BTBLookups 16952662 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1212 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1950052 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14577615 # Number of conditional branches predicted -global.BPredUnit.lookups 19451761 # Number of BP lookups -global.BPredUnit.usedRAS 1721600 # Number of times the RAS was used to get a target. -host_inst_rate 79678 # Simulator instruction rate (inst/s) -host_mem_usage 202860 # Number of bytes of host memory used -host_seconds 1056.50 # Real time elapsed on the host -host_tick_rate 38578826 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17804625 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5077040 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33854360 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10604217 # Number of stores inserted to the mem dependence unit. +host_inst_rate 205423 # Simulator instruction rate (inst/s) +host_mem_usage 211084 # Number of bytes of host memory used +host_seconds 409.79 # Real time elapsed on the host +host_tick_rate 99609545 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040758 # Number of seconds simulated -sim_ticks 40758469000 # Number of ticks simulated +sim_seconds 0.040819 # Number of seconds simulated +sim_ticks 40818658500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 13008791 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 16964874 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19468548 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2850471 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73485570 +system.cpu.commit.COM:committed_per_cycle.samples 73457196 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 36241200 4931.74% - 1 18077968 2460.07% - 2 7549008 1027.28% - 3 4015107 546.38% - 4 2030060 276.25% - 5 1302937 177.31% - 6 688676 93.72% - 7 730143 99.36% - 8 2850471 387.90% + 0 36278941 4938.79% + 1 18156304 2471.68% + 2 7455517 1014.95% + 3 3880419 528.26% + 4 2046448 278.59% + 5 1301140 177.13% + 6 721823 98.26% + 7 760802 103.57% + 8 2855802 388.77% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,406 +39,385 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1937588 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 55772540 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.968368 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.968368 # CPI: Total CPI of All Threads +system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23270992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 11553.149606 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6675.196850 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23270484 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5869000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 508 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3391000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 508 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6494911 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 34394.822006 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7197.950378 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493057 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 63768000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000285 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1854 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6192 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 13345000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13269.579581 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29765903 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29482.218459 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29763541 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 69637000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2362 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6315 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 16736000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2362 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29765903 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29482.218459 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29763541 # number of overall hits -system.cpu.dcache.overall_miss_latency 69637000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2362 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6315 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 16736000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 29894354 # number of overall hits +system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9171 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2362 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1461.984287 # Cycle average of tags in use -system.cpu.dcache.total_refs 29763667 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use +system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3862301 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12627 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3048985 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162336287 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39537926 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29896024 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8028470 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 189320 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 31783723 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 31911121 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 31332689 # DTB hits -system.cpu.dtb.misses 451034 # DTB misses -system.cpu.dtb.read_accesses 24575603 # DTB read accesses +system.cpu.dtb.hits 31454022 # DTB hits +system.cpu.dtb.misses 457099 # DTB misses +system.cpu.dtb.read_accesses 24718123 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24125563 # DTB read hits -system.cpu.dtb.read_misses 450040 # DTB read misses -system.cpu.dtb.write_accesses 7208120 # DTB write accesses +system.cpu.dtb.read_hits 24262026 # DTB read hits +system.cpu.dtb.read_misses 456097 # DTB read misses +system.cpu.dtb.write_accesses 7192998 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7207126 # DTB write hits -system.cpu.dtb.write_misses 994 # DTB write misses -system.cpu.fetch.Branches 19451761 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19219800 # Number of cache lines fetched -system.cpu.fetch.Cycles 50154718 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 536931 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167137455 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2059472 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238622 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19219800 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14743121 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.050340 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 7191996 # DTB write hits +system.cpu.dtb.write_misses 1002 # DTB write misses +system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched +system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81514041 +system.cpu.fetch.rateDist.samples 81528343 system.cpu.fetch.rateDist.min_value 0 - 0 50579197 6204.97% - 1 3119637 382.71% - 2 2009848 246.56% - 3 3519871 431.81% - 4 4617609 566.48% - 5 1511564 185.44% - 6 2006119 246.11% - 7 1828029 224.26% - 8 12322167 1511.66% + 0 50560378 6201.57% + 1 3114212 381.98% + 2 2012618 246.86% + 3 3505366 429.96% + 4 4590613 563.07% + 5 1506961 184.84% + 6 2028359 248.79% + 7 1846743 226.52% + 8 12363093 1516.42% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 19219343 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 6740.447436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3507.077806 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19209241 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 68092000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000526 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10102 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 457 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 35428500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10102 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1901.528509 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19219343 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 6740.447436 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency -system.cpu.icache.demand_hits 19209241 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 68092000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000526 # miss rate for demand accesses -system.cpu.icache.demand_misses 10102 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 457 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 35428500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10102 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency +system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses +system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19219343 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 6740.447436 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency +system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19209241 # number of overall hits -system.cpu.icache.overall_miss_latency 68092000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000526 # miss rate for overall accesses -system.cpu.icache.overall_misses 10102 # number of overall misses -system.cpu.icache.overall_mshr_hits 457 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 35428500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10102 # number of overall MSHR misses +system.cpu.icache.overall_hits 19218965 # number of overall hits +system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses +system.cpu.icache.overall_misses 11038 # number of overall misses +system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8191 # number of replacements -system.cpu.icache.sampled_refs 10102 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8143 # number of replacements +system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1547.575549 # Cycle average of tags in use -system.cpu.icache.total_refs 19209241 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use +system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 2898 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12781978 # Number of branches executed -system.cpu.iew.EXEC:nop 12589139 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.246896 # Inst execution rate -system.cpu.iew.EXEC:refs 31834864 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7209747 # Number of stores executed +system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12812003 # Number of branches executed +system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate +system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7194632 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 91092089 # num instructions consuming a value -system.cpu.iew.WB:count 99774116 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.721851 # average fanout of values written-back +system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value +system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65754876 # num instructions producing a value -system.cpu.iew.WB:rate 1.223968 # insts written-back per cycle -system.cpu.iew.WB:sent 100649675 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2112266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 284242 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33854360 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1723654 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10604217 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 147674740 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24625117 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2113526 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101643128 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 120911 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 65837672 # num instructions producing a value +system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle +system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8028470 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 165624 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 844640 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2772 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 223466 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13819947 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4101522 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 223466 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 201477 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1910789 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.032665 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.032665 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 103756654 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7 0.00% # Type of FU issued - IntAlu 64328227 62.00% # Type of FU issued - IntMult 474807 0.46% # Type of FU issued + IntAlu 64430040 61.93% # Type of FU issued + IntMult 475055 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2783435 2.68% # Type of FU issued - FloatCmp 115619 0.11% # Type of FU issued - FloatCvt 2381566 2.30% # Type of FU issued - FloatMult 305730 0.29% # Type of FU issued - FloatDiv 755065 0.73% # Type of FU issued - FloatSqrt 322 0.00% # Type of FU issued - MemRead 25279956 24.36% # Type of FU issued - MemWrite 7331920 7.07% # Type of FU issued + FloatAdd 2782164 2.67% # Type of FU issued + FloatCmp 115645 0.11% # Type of FU issued + FloatCvt 2377276 2.29% # Type of FU issued + FloatMult 305748 0.29% # Type of FU issued + FloatDiv 755245 0.73% # Type of FU issued + FloatSqrt 323 0.00% # Type of FU issued + MemRead 25462424 24.48% # Type of FU issued + MemWrite 7324714 7.04% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1948888 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018783 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 297234 15.25% # attempts to use FU when none available + IntAlu 274346 14.19% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 492 0.03% # attempts to use FU when none available + FloatAdd 31 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 3359 0.17% # attempts to use FU when none available - FloatMult 1274 0.07% # attempts to use FU when none available - FloatDiv 828421 42.51% # attempts to use FU when none available + FloatCvt 6547 0.34% # attempts to use FU when none available + FloatMult 2333 0.12% # attempts to use FU when none available + FloatDiv 832912 43.09% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 745957 38.28% # attempts to use FU when none available - MemWrite 72151 3.70% # attempts to use FU when none available + MemRead 743147 38.44% # attempts to use FU when none available + MemWrite 73812 3.82% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81514041 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35401194 4342.96% - 1 18638593 2286.55% - 2 11850080 1453.75% - 3 6738129 826.62% - 4 5072118 622.24% - 5 2314380 283.92% - 6 1219789 149.64% - 7 213656 26.21% - 8 66102 8.11% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.272823 # Inst issue rate -system.cpu.iq.iqInstsAdded 135085172 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 103756654 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50298713 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 225846 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47102449 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 19219874 # ITB accesses +system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% +system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 +system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate +system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 19230073 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 19219800 # ITB hits -system.cpu.itb.misses 74 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5751.440092 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2751.440092 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9984500 # number of ReadExReq miss cycles +system.cpu.itb.hits 19230003 # ITB hits +system.cpu.itb.misses 70 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4776500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10609 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5363.488784 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.488784 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 18171500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.319351 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8007500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319351 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 122 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5704.918033 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2704.918033 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 696000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 122 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 330000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 122 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.154260 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12345 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5494.925839 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 28156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415067 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12784000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415067 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12345 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5494.925839 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7221 # number of overall hits -system.cpu.l2cache.overall_miss_latency 28156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415067 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5124 # number of overall misses +system.cpu.l2cache.overall_hits 7186 # number of overall hits +system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5110 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12784000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415067 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3345 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2257.557113 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7206 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81516939 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1780351 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 17216078 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5041116 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 81637318 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1047628 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40793393 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 942240 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202632347 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157116893 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115707927 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28822360 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8028470 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2084695 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47280566 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4772 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 463 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4626500 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed -system.cpu.timesIdled 687 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed +system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr deleted file mode 100644 index 5992f7131..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout deleted file mode 100644 index f32f0a972..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124
\ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 8fbd6f60b..593992332 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=twolf smred cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index 4f9067256..d3d15e406 100644..100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,3 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:41:19 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py long/70.twolf/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -11,16 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Oct 21 2007 20:57:52 -M5 started Sun Oct 21 23:31:23 2007 -M5 executing on nacho -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 129910855000 because target called exit() +122 123 124
\ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 127e45547..bce09d7dd 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2451408 # Simulator instruction rate (inst/s) -host_mem_usage 179100 # Number of bytes of host memory used -host_seconds 37.49 # Real time elapsed on the host -host_tick_rate 1225693454 # Simulator tick rate (ticks/s) +host_inst_rate 5743124 # Simulator instruction rate (inst/s) +host_mem_usage 200524 # Number of bytes of host memory used +host_seconds 16.00 # Real time elapsed on the host +host_tick_rate 2871531471 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100644 index f33d007a7..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index fd50e16e0..b166b9052 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=twolf smred cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..b2d79346c --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index f32f0a972..c9ffcf959 100644..100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:41:35 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py long/70.twolf/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index a1b1d8e71..c77e086b4 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,83 +1,74 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1053450 # Simulator instruction rate (inst/s) -host_mem_usage 201692 # Number of bytes of host memory used -host_seconds 87.24 # Real time elapsed on the host -host_tick_rate 1359521857 # Simulator tick rate (ticks/s) +host_inst_rate 2902114 # Simulator instruction rate (inst/s) +host_mem_usage 207972 # Number of bytes of host memory used +host_seconds 31.67 # Real time elapsed on the host +host_tick_rate 3749775750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118605 # Number of seconds simulated -sim_ticks 118605062000 # Number of ticks simulated +sim_seconds 0.118747 # Number of seconds simulated +sim_ticks 118747246000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25546.413502 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22546.413502 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12109000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 10687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 50193000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 44616000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26704.672096 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 62302000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 55303000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26704.672096 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494968 # number of overall hits -system.cpu.dcache.overall_miss_latency 62302000 # number of overall miss cycles +system.cpu.dcache.overall_hits 26494967 # number of overall hits +system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2333 # number of overall misses +system.cpu.dcache.overall_misses 2334 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 55303000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.428133 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use +system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.dtb.accesses 26497334 # DTB accesses @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18003.877791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15003.877791 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 153213000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 127683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18003.877791 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 153213000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 127683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18003.877791 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.overall_miss_latency 153213000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 127683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.444669 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,89 +142,80 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 91903090 # ITB hits system.cpu.itb.misses 47 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 40204000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 69966000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2553000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.970090 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 110170000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 52690000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 110170000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4790 # number of overall misses +system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4791 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 52690000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2021.668860 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237210124 # number of cpu cycles simulated +system.cpu.numCycles 237494492 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr deleted file mode 100644 index 26249ed90..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout deleted file mode 100644 index f32f0a972..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124
\ No newline at end of file diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 31489ec58..3d5e2c242 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=twolf smred cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 241142dbb..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2449488 # Simulator instruction rate (inst/s) -host_mem_usage 181120 # Number of bytes of host memory used -host_seconds 78.97 # Real time elapsed on the host -host_tick_rate 1224747555 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193435005 # Number of instructions simulated -sim_seconds 0.096718 # Number of seconds simulated -sim_ticks 96718067000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 193436135 # number of cpu cycles simulated -system.cpu.num_insts 193435005 # Number of instructions executed -system.cpu.num_refs 76733003 # Number of memory references -system.cpu.workload.PROG:num_syscalls 396 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index 8a70482ca..eb6462de2 100644..100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:55:15 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py long/70.twolf/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -11,16 +25,5 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 96718067000 because target called exit() +info: Increasing stack size by one page. +122 123 124 Exiting @ tick 96722951500 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..9b4c86591 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2406877 # Simulator instruction rate (inst/s) +host_mem_usage 202316 # Number of bytes of host memory used +host_seconds 80.37 # Real time elapsed on the host +host_tick_rate 1203441627 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 193444769 # Number of instructions simulated +sim_seconds 0.096723 # Number of seconds simulated +sim_ticks 96722951500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 193445904 # number of cpu cycles simulated +system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.num_refs 76733959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 401 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index 598fc86c0..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index fe6c893b2..65aeb1d48 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=twolf smred cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index 0d7eb187f..b27d83682 100644..100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:33:08 +M5 executing on tater +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -11,18 +27,5 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:18:16 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 270416976000 because target called exit() +info: Increasing stack size by one page. +122 123 124 Exiting @ tick 270578335000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index b8ccd7e90..f73a0dcbf 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,244 +1,217 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1067073 # Simulator instruction rate (inst/s) -host_mem_usage 203488 # Number of bytes of host memory used -host_seconds 181.28 # Real time elapsed on the host -host_tick_rate 1491737734 # Simulator tick rate (ticks/s) +host_inst_rate 732316 # Simulator instruction rate (inst/s) +host_mem_usage 209324 # Number of bytes of host memory used +host_seconds 264.15 # Real time elapsed on the host +host_tick_rate 1024317022 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 193435005 # Number of instructions simulated -sim_seconds 0.270417 # Number of seconds simulated -sim_ticks 270416976000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13446000 # number of ReadReq miss cycles +sim_insts 193444769 # Number of instructions simulated +sim_seconds 0.270578 # Number of seconds simulated +sim_ticks 270578335000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 11952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 54000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975304 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 29970000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1110 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 26640000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1110 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 76708944 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43416000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1608 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 38592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1608 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 76708944 # number of overall hits -system.cpu.dcache.overall_miss_latency 43416000 # number of overall miss cycles +system.cpu.dcache.overall_hits 76709909 # number of overall hits +system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1608 # number of overall misses +system.cpu.dcache.overall_misses 1599 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 38592000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1608 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 26 # number of replacements -system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2 # number of replacements +system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.389513 # Cycle average of tags in use -system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1237.193190 # Cycle average of tags in use +system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 23 # number of writebacks -system.cpu.icache.ReadReq_accesses 193436018 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 17803.146397 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 14803.146397 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193423750 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 218409000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 181605000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks 2 # number of writebacks +system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15766.526736 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193436018 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 17803.146397 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency -system.cpu.icache.demand_hits 193423750 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 218409000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses -system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency +system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses +system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 181605000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 193436018 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 17803.146397 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency +system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193423750 # number of overall hits -system.cpu.icache.overall_miss_latency 218409000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses -system.cpu.icache.overall_misses 12268 # number of overall misses +system.cpu.icache.overall_hits 193433261 # number of overall hits +system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses +system.cpu.icache.overall_misses 12288 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 181605000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 10342 # number of replacements -system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. +system.cpu.icache.replacements 10362 # number of replacements +system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.711897 # Cycle average of tags in use -system.cpu.icache.total_refs 193423750 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.566647 # Cycle average of tags in use +system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1087 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 25001000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1087 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 11957000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1087 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 12766 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8679 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 94001000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.320147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4087 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44957000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4087 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 575000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.128249 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 13853 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8679 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 119002000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.373493 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5174 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 56914000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.373493 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 13853 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 8679 # number of overall hits -system.cpu.l2cache.overall_miss_latency 119002000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.373493 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5174 # number of overall misses +system.cpu.l2cache.overall_hits 8691 # number of overall hits +system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5173 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 56914000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.373493 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5174 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4078 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2649.681897 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2657.327979 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 540833952 # number of cpu cycles simulated -system.cpu.num_insts 193435005 # Number of instructions executed -system.cpu.num_refs 76733003 # Number of memory references -system.cpu.workload.PROG:num_syscalls 396 # Number of system calls +system.cpu.numCycles 541156670 # number of cpu cycles simulated +system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.num_refs 76733959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index d6124e8ba..000000000 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index 0644df864..d0a878165 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=twolf smred cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index db17fc7d7..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1304954 # Simulator instruction rate (inst/s) -host_mem_usage 183200 # Number of bytes of host memory used -host_seconds 167.36 # Real time elapsed on the host -host_tick_rate 776224834 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218399764 # Number of instructions simulated -sim_seconds 0.129911 # Number of seconds simulated -sim_ticks 129910855000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259821711 # number of cpu cycles simulated -system.cpu.num_insts 218399764 # Number of instructions executed -system.cpu.num_refs 77164404 # Number of memory references -system.cpu.workload.PROG:num_syscalls 395 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..100c59b7e --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:54:15 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 130009234000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..f3c94835b --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 744144 # Simulator instruction rate (inst/s) +host_mem_usage 204416 # Number of bytes of host memory used +host_seconds 293.75 # Real time elapsed on the host +host_tick_rate 442578451 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 218595300 # Number of instructions simulated +sim_seconds 0.130009 # Number of seconds simulated +sim_ticks 130009234000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 260018469 # number of cpu cycles simulated +system.cpu.num_insts 218595300 # Number of instructions executed +system.cpu.num_refs 77165298 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr deleted file mode 100644 index 6947c985e..000000000 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,7 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..c231a2f5e --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..2a43627aa --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:58:47 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 250945484000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..3d7cbb069 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,207 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 660588 # Simulator instruction rate (inst/s) +host_mem_usage 211972 # Number of bytes of host memory used +host_seconds 330.91 # Real time elapsed on the host +host_tick_rate 758349031 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 218595300 # Number of instructions simulated +sim_seconds 0.250945 # Number of seconds simulated +sim_ticks 250945484000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency +system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 77163409 # number of overall hits +system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1920 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 27 # number of replacements +system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1362.582924 # Cycle average of tags in use +system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2 # number of writebacks +system.cpu.icache.ReadReq_accesses 173494366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 173489673 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 36967.754741 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 173494366 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency +system.cpu.icache.demand_hits 173489673 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses +system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 173494366 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 173489673 # number of overall hits +system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses +system.cpu.icache.overall_misses 4693 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 2835 # number of replacements +system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1454.285546 # Cycle average of tags in use +system.cpu.icache.total_refs 173489673 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1855 # number of overall hits +system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4732 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 2032.147267 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 501890968 # number of cpu cycles simulated +system.cpu.num_insts 218595300 # Number of instructions executed +system.cpu.num_refs 77165298 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 7369c8a0c..1a673fafa 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -47,7 +47,8 @@ side_b=system.membus.port[2] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer +children=dtb interrupts itb tracer +checker=Null clock=1 cpu_id=0 defer_registration=false @@ -57,15 +58,18 @@ do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -76,6 +80,9 @@ icache_port=system.membus.port[9] type=SparcDTB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcITB size=64 @@ -97,6 +104,7 @@ pio=system.iobus.port[15] type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -108,7 +116,9 @@ read_only=true [system.hypervisor_desc] type=PhysicalMemory file= -latency=1 +latency=60 +latency_var=0 +null=false range=133446500352:133446508543 zero=false port=system.membus.port[7] @@ -123,6 +133,7 @@ children=responder block_size=64 bus_id=0 clock=2 +header_cycles=1 responder_set=false width=64 default=system.iobus.responder.pio @@ -150,6 +161,7 @@ children=responder block_size=64 bus_id=1 clock=2 +header_cycles=1 responder_set=false width=64 default=system.membus.responder.pio @@ -174,7 +186,9 @@ pio=system.membus.default [system.nvram] type=PhysicalMemory file= -latency=1 +latency=60 +latency_var=0 +null=false range=133429198848:133429207039 zero=false port=system.membus.port[6] @@ -182,7 +196,9 @@ port=system.membus.port[6] [system.partition_desc] type=PhysicalMemory file= -latency=1 +latency=60 +latency_var=0 +null=false range=133445976064:133445984255 zero=false port=system.membus.port[8] @@ -190,7 +206,9 @@ port=system.membus.port[8] [system.physmem] type=PhysicalMemory file= -latency=1 +latency=60 +latency_var=0 +null=false range=1048576:68157439 zero=true port=system.membus.port[3] @@ -198,7 +216,9 @@ port=system.membus.port[3] [system.physmem2] type=PhysicalMemory file= -latency=1 +latency=60 +latency_var=0 +null=false range=2147483648:2415919103 zero=true port=system.membus.port[4] @@ -206,14 +226,16 @@ port=system.membus.port[4] [system.rom] type=PhysicalMemory file= -latency=1 +latency=60 +latency_var=0 +null=false range=1099243192320:1099251580927 zero=false port=system.membus.port[5] [system.t1000] type=T1000 -children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hconsole htod hvuart iob pconsole puart0 +children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 intrctrl=system.intrctrl system=system @@ -409,12 +431,11 @@ update_data=false warn_access= pio=system.iobus.port[10] -[system.t1000.hconsole] -type=SimConsole -append_name=true +[system.t1000.hterm] +type=Terminal intr_control=system.intrctrl number=0 -output=console +output=true port=3456 [system.t1000.htod] @@ -431,8 +452,8 @@ type=Uart8250 pio_addr=1099255955456 pio_latency=2 platform=system.t1000 -sim_console=system.t1000.hconsole system=system +terminal=system.t1000.hterm pio=system.iobus.port[13] [system.t1000.iob] @@ -442,12 +463,11 @@ platform=system.t1000 system=system pio=system.membus.port[0] -[system.t1000.pconsole] -type=SimConsole -append_name=true +[system.t1000.pterm] +type=Terminal intr_control=system.intrctrl number=0 -output=console +output=true port=3456 [system.t1000.puart0] @@ -455,7 +475,7 @@ type=Uart8250 pio_addr=133412421632 pio_latency=2 platform=system.t1000 -sim_console=system.t1000.pconsole system=system +terminal=system.t1000.pterm pio=system.iobus.port[12] diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole deleted file mode 100644 index e69de29bb..000000000 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole +++ /dev/null diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr new file mode 100755 index 000000000..d6849b6b0 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -0,0 +1,15 @@ +Warning: rounding error > tolerance + 0.002000 rounded to 0 +Warning: rounding error > tolerance + 0.002000 rounded to 0 +Warning: rounding error > tolerance + 0.002000 rounded to 0 +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +Warning: rounding error > tolerance + 0.002000 rounded to 0 +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Don't know what interrupt to clear for console. +For more information see: http://www.m5sim.org/warn/7fe1004f +hack: be nice to actually delete the event here diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout new file mode 100755 index 000000000..177f45aa2 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 01:00:04 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:00:27 +M5 executing on zizzer +command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic +Global frequency set at 2000000000 ticks per second +info: No kernel set for full system simulation. Assuming you know what you're doing... +info: Entering event queue @ 0. Starting simulation... +info: Ignoring write to SPARC ERROR regsiter +info: Ignoring write to SPARC ERROR regsiter +Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 34b89818c..74e0ebf1a 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1839897 # Simulator instruction rate (inst/s) -host_mem_usage 481416 # Number of bytes of host memory used -host_seconds 1211.57 # Real time elapsed on the host -host_tick_rate 1843707 # Simulator tick rate (ticks/s) +host_inst_rate 2534703 # Simulator instruction rate (inst/s) +host_mem_usage 501600 # Number of bytes of host memory used +host_seconds 879.46 # Real time elapsed on the host +host_tick_rate 2539952 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2229160714 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr deleted file mode 100644 index 4c0b4aee0..000000000 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr +++ /dev/null @@ -1,16 +0,0 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Warning: rounding error > tolerance - 0.002000 rounded to 0 -warn: No kernel set for full system simulation. Assuming you know what you're doing... -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Listening for t1000 connection on port 3456 -Listening for t1000 connection on port 3457 -Warning: rounding error > tolerance - 0.002000 rounded to 0 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: Ignoring write to SPARC ERROR regsiter -warn: Ignoring write to SPARC ERROR regsiter -warn: Don't know what interrupt to clear for console. diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout deleted file mode 100644 index 4c8cf9392..000000000 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Aug 21 2007 14:42:25 -M5 started Tue Aug 21 14:44:56 2007 -M5 executing on nacho -command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -Global frequency set at 2000000000 ticks per second -Exiting @ tick 2233777512 because m5_exit instruction encountered diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm index e69de29bb..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm index f90a96e24..f90a96e24 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1d32ced97..46ef9d2b9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout new file mode 100755 index 000000000..f448ee025 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:22:19 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 12474500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index cd104d2c8..21437f2a4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,288 +1,270 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 574 # Number of BTB hits -global.BPredUnit.BTBLookups 1715 # Number of BTB lookups -global.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 425 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted -global.BPredUnit.lookups 2013 # Number of BP lookups -global.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. -host_inst_rate 44727 # Simulator instruction rate (inst/s) -host_mem_usage 151980 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 42091644 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1228 # Number of stores inserted to the mem dependence unit. +host_inst_rate 83921 # Simulator instruction rate (inst/s) +host_mem_usage 202572 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 163392144 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5303000 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 89 # number cycles where commit BW limit reached +sim_insts 6386 # Number of instructions simulated +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12474500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2263 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 1051 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9365 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7035 7512.01% - 1 1204 1285.64% - 2 411 438.87% - 3 192 205.02% - 4 145 154.83% - 5 90 96.10% - 6 97 103.58% - 7 102 108.92% - 8 89 95.03% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::samples 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9513 76.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 115 0.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515706 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.304935 # Number of insts commited each cycle +system.cpu.commit.COM:count 6403 # Number of instructions committed +system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 353 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4190 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.886360 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.886360 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1566 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10875.939850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8494.897959 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1433 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.084930 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 832500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062580 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8648.247978 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7436.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 441 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3208500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.456897 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 371 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit +system.cpu.committedInsts 6386 # Number of Instructions Simulated +system.cpu.committedInsts_total 6386 # Number of Instructions Simulated +system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.188235 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2378 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1874 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4655000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.211943 # miss rate for demand accesses -system.cpu.dcache.demand_misses 504 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1479500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.077796 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses +system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2378 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1874 # number of overall hits -system.cpu.dcache.overall_miss_latency 4655000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.211943 # miss rate for overall accesses -system.cpu.dcache.overall_misses 504 # number of overall misses -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1479500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.077796 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2104 # number of overall hits +system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses +system.cpu.dcache.overall_misses 554 # number of overall misses +system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 107.937594 # Cycle average of tags in use -system.cpu.dcache.total_refs 1902 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use +system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 163 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11516 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6794 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2076 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 792 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 231 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2663 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 2951 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2604 # DTB hits -system.cpu.dtb.misses 59 # DTB misses -system.cpu.dtb.read_accesses 1652 # DTB read accesses +system.cpu.dtb.hits 2890 # DTB hits +system.cpu.dtb.misses 61 # DTB misses +system.cpu.dtb.read_accesses 1876 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1614 # DTB read hits -system.cpu.dtb.read_misses 38 # DTB read misses -system.cpu.dtb.write_accesses 1011 # DTB write accesses +system.cpu.dtb.read_hits 1840 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.write_accesses 1075 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 990 # DTB write hits -system.cpu.dtb.write_misses 21 # DTB write misses -system.cpu.fetch.Branches 2013 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1565 # Number of cache lines fetched -system.cpu.fetch.Cycles 3769 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 233 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12458 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.189780 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 844 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.174507 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10158 -system.cpu.fetch.rateDist.min_value 0 - 0 7986 7861.78% - 1 184 181.14% - 2 171 168.34% - 3 148 145.70% - 4 221 217.56% - 5 166 163.42% - 6 188 185.08% - 7 106 104.35% - 8 988 972.63% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9178.260870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6606.451613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1220 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.220447 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2048000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.198083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.dtb.write_hits 1050 # DTB write hits +system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched +system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 10844 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 252 1.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 238 1.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 230 1.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 272 2.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 162 1.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 232 1.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 129 0.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 955 7.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.935484 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1565 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1220 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.220447 # miss rate for demand accesses -system.cpu.icache.demand_misses 345 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2048000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.198083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses +system.cpu.icache.demand_misses 424 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1565 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1220 # number of overall hits -system.cpu.icache.overall_miss_latency 3166500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.220447 # miss rate for overall accesses -system.cpu.icache.overall_misses 345 # number of overall misses -system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2048000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.198083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_hits 1378 # number of overall hits +system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses +system.cpu.icache.overall_misses 424 # number of overall misses +system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 162.483905 # Cycle average of tags in use -system.cpu.icache.total_refs 1220 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use +system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 449 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1210 # Number of branches executed -system.cpu.iew.EXEC:nop 70 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.759310 # Inst execution rate -system.cpu.iew.EXEC:refs 2668 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1014 # Number of stores executed +system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1450 # Number of branches executed +system.cpu.iew.EXEC:nop 82 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate +system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1077 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5427 # num instructions consuming a value -system.cpu.iew.WB:count 7728 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.742583 # average fanout of values written-back +system.cpu.iew.WB:consumers 6020 # num instructions consuming a value +system.cpu.iew.WB:count 8734 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4030 # num instructions producing a value -system.cpu.iew.WB:rate 0.728575 # insts written-back per cycle -system.cpu.iew.WB:sent 7840 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 420 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions +system.cpu.iew.WB:producers 4491 # num instructions producing a value +system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle +system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 185 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1228 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9927 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8054 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 792 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1034 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 416 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 297 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.530122 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.530122 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8404 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5587 66.48% # Type of FU issued + IntAlu 6254 66.92% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -291,16 +273,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1774 21.11% # Type of FU issued - MemWrite 1038 12.35% # Type of FU issued + MemRead 1986 21.25% # Type of FU issued + MemWrite 1100 11.77% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 103 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012256 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 0.97% # attempts to use FU when none available + IntAlu 14 13.33% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,135 +291,133 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 68 66.02% # attempts to use FU when none available - MemWrite 34 33.01% # attempts to use FU when none available + MemRead 56 53.33% # attempts to use FU when none available + MemWrite 35 33.33% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10158 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6739 6634.18% - 1 1163 1144.91% - 2 838 824.97% - 3 636 626.11% - 4 450 443.00% - 5 195 191.97% - 6 92 90.57% - 7 30 29.53% - 8 15 14.77% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.792307 # Inst issue rate -system.cpu.iq.iqInstsAdded 9833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8404 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% +system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 13314 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 +system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate +system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3830 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2411 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1597 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1838 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1565 # ITB hits -system.cpu.itb.misses 32 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 440000 # number of ReadExReq miss cycles +system.cpu.itb.hits 1802 # ITB hits +system.cpu.itb.misses 36 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5733.415233 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2733.415233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2333500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1112500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5433.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2433.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 81500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1336500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2773500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 479 # number of overall misses +system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1336500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 215.878593 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 10607 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 6962 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14001 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10976 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8169 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 792 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4118 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 79 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24950 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr deleted file mode 100644 index 5992f7131..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout deleted file mode 100644 index fc63a59a9..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:32 2008 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5303000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 264bd19de..5b4a31473 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout new file mode 100755 index 000000000..8975ff812 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py quick/00.hello/alpha/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 3215000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt index c89057e77..93917b1eb 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 274181 # Simulator instruction rate (inst/s) -host_mem_usage 172576 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 135418658 # Simulator tick rate (ticks/s) +host_inst_rate 122377 # Simulator instruction rate (inst/s) +host_mem_usage 192524 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 61135620 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated +sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2833500 # Number of ticks simulated -system.cpu.dtb.accesses 1801 # DTB accesses +sim_ticks 3215000 # Number of ticks simulated +system.cpu.dtb.accesses 2060 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2050 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 868 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.accesses 6431 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.hits 6414 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5668 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 6431 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr deleted file mode 100644 index f33d007a7..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout deleted file mode 100644 index 9af7c0a45..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Aug 14 2007 17:36:58 -M5 started Tue Aug 14 17:40:03 2007 -M5 executing on nacho -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2833500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 7b95a328d..26edcc7cf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout new file mode 100755 index 000000000..22d348b2d --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py quick/00.hello/alpha/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 33777000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index d791e0a2e..dc4411624 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,248 +1,221 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11324 # Simulator instruction rate (inst/s) -host_mem_usage 193960 # Number of bytes of host memory used -host_seconds 0.50 # Real time elapsed on the host -host_tick_rate 38693743 # Simulator tick rate (ticks/s) +host_inst_rate 344098 # Simulator instruction rate (inst/s) +host_mem_usage 199968 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1795121173 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19285000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses +sim_insts 6404 # Number of instructions simulated +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33777000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses -system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses +system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1612 # number of overall hits -system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses -system.cpu.dcache.overall_misses 179 # number of overall misses +system.cpu.dcache.overall_hits 1868 # number of overall hits +system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses +system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.207107 # Cycle average of tags in use -system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use +system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.accesses 2060 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2050 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 868 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26953.068592 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.068592 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7466000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency -system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7466000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses -system.cpu.icache.demand_misses 277 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency +system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses +system.cpu.icache.demand_misses 279 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency +system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5375 # number of overall hits -system.cpu.icache.overall_miss_latency 7466000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses -system.cpu.icache.overall_misses 277 # number of overall misses +system.cpu.icache.overall_hits 6136 # number of overall hits +system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses +system.cpu.icache.overall_misses 279 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 127.893604 # Cycle average of tags in use -system.cpu.icache.total_refs 5375 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use +system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5669 # ITB accesses +system.cpu.itb.accesses 6432 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5652 # ITB hits +system.cpu.itb.hits 6415 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1679000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8464000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002825 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10143000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10143000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 441 # number of overall misses +system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 446 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 177.260989 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 38570 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 67554 # number of cpu cycles simulated +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr deleted file mode 100644 index 5992f7131..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout deleted file mode 100644 index 11d2e9b8e..000000000 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 12:58:22 2008 -M5 executing on tater -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 19285000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 26f63e7be..9abe15dfc 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..bb8489f81 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..038644e5f --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:16:36 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 7183000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index b9f64c44d..14b605eaa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,288 +1,270 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 155 # Number of BTB hits -global.BPredUnit.BTBLookups 639 # Number of BTB lookups -global.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 405 # Number of conditional branches predicted -global.BPredUnit.lookups 821 # Number of BP lookups -global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. -host_inst_rate 39438 # Simulator instruction rate (inst/s) -host_mem_usage 151264 # Number of bytes of host memory used +host_inst_rate 39458 # Simulator instruction rate (inst/s) +host_mem_usage 201572 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 44410086 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 408 # Number of stores inserted to the mem dependence unit. +host_tick_rate 118256203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2700000 # Number of ticks simulated +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 7183000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 198 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 684 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 447 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 859 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 4866 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3922 8060.01% - 1 255 524.04% - 2 327 672.01% - 3 133 273.33% - 4 67 137.69% - 5 70 143.86% - 6 33 67.82% - 7 20 41.10% - 8 39 80.15% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 6196 +system.cpu.commit.COM:committed_per_cycle::min_value 0 +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% +system.cpu.commit.COM:committed_per_cycle::0-1 5239 84.55% +system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% +system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% +system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% +system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% +system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% +system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% +system.cpu.commit.COM:committed_per_cycle::8 38 0.61% +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% +system.cpu.commit.COM:committed_per_cycle::total 6196 +system.cpu.commit.COM:committed_per_cycle::max_value 8 +system.cpu.commit.COM:committed_per_cycle::mean 0.415752 +system.cpu.commit.COM:committed_per_cycle::stdev 1.208059 system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1414 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 542 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9881.944444 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.132841 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.112546 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9732.673267 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.343537 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 836 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9794.797688 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency -system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.206938 # miss rate for demand accesses -system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.117225 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses +system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 836 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9794.797688 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 663 # number of overall hits -system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.206938 # miss rate for overall accesses -system.cpu.dcache.overall_misses 173 # number of overall misses -system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.117225 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 674 # number of overall hits +system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses +system.cpu.dcache.overall_misses 193 # number of overall misses +system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use -system.cpu.dcache.total_refs 694 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use +system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 133 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4610 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3877 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 889 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 290 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 293 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 936 # DTB accesses +system.cpu.dtb.accesses 971 # DTB accesses system.cpu.dtb.acv 1 # DTB access violations -system.cpu.dtb.hits 911 # DTB hits +system.cpu.dtb.hits 946 # DTB hits system.cpu.dtb.misses 25 # DTB misses -system.cpu.dtb.read_accesses 578 # DTB read accesses +system.cpu.dtb.read_accesses 611 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 567 # DTB read hits +system.cpu.dtb.read_hits 600 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 358 # DTB write accesses +system.cpu.dtb.write_accesses 360 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 344 # DTB write hits +system.cpu.dtb.write_hits 346 # DTB write hits system.cpu.dtb.write_misses 14 # DTB write misses -system.cpu.fetch.Branches 821 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 705 # Number of cache lines fetched -system.cpu.fetch.Cycles 1625 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 104 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5290 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 238 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.152009 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 705 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 317 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.979448 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 5157 -system.cpu.fetch.rateDist.min_value 0 - 0 4266 8272.25% - 1 34 65.93% - 2 85 164.82% - 3 67 129.92% - 4 115 223.00% - 5 55 106.65% - 6 41 79.50% - 7 48 93.08% - 8 446 864.84% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 705 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8914.634146 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.290780 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 205 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.258156 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses +system.cpu.fetch.Branches 859 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 747 # Number of cache lines fetched +system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 5595 85.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 36 0.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 100 1.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 69 1.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 130 1.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 72 1.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 45 0.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 48 0.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 433 6.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 6528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.826134 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.219931 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.747253 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 705 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8914.634146 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency -system.cpu.icache.demand_hits 500 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.290780 # miss rate for demand accesses -system.cpu.icache.demand_misses 205 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.258156 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.demand_hits 512 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses +system.cpu.icache.demand_misses 235 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 705 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8914.634146 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency +system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 500 # number of overall hits -system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.290780 # miss rate for overall accesses -system.cpu.icache.overall_misses 205 # number of overall misses -system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.258156 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.icache.overall_hits 512 # number of overall hits +system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses +system.cpu.icache.overall_misses 235 # number of overall misses +system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 91.765219 # Cycle average of tags in use -system.cpu.icache.total_refs 500 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use +system.cpu.icache.total_refs 512 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 542 # Number of branches executed -system.cpu.iew.EXEC:nop 277 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.591187 # Inst execution rate -system.cpu.iew.EXEC:refs 939 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 358 # Number of stores executed +system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 584 # Number of branches executed +system.cpu.iew.EXEC:nop 286 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate +system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 360 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1788 # num instructions consuming a value -system.cpu.iew.WB:count 3104 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back +system.cpu.iew.WB:consumers 1896 # num instructions consuming a value +system.cpu.iew.WB:count 3311 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1414 # num instructions producing a value -system.cpu.iew.WB:rate 0.574708 # insts written-back per cycle -system.cpu.iew.WB:sent 3141 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 150 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 703 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1509 # num instructions producing a value +system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle +system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 408 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4070 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 581 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 98 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3193 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 290 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 288 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 114 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.441955 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.441955 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3291 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 2327 70.71% # Type of FU issued + IntAlu 2506 71.31% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -291,16 +273,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 599 18.20% # Type of FU issued - MemWrite 364 11.06% # Type of FU issued + MemRead 639 18.18% # Type of FU issued + MemWrite 368 10.47% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010635 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 2.86% # attempts to use FU when none available + IntAlu 1 2.94% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,63 +291,65 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 12 34.29% # attempts to use FU when none available - MemWrite 22 62.86% # attempts to use FU when none available + MemRead 11 32.35% # attempts to use FU when none available + MemWrite 22 64.71% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 5157 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3776 7322.09% - 1 540 1047.12% - 2 304 589.49% - 3 226 438.24% - 4 166 321.89% - 5 89 172.58% - 6 40 77.56% - 7 12 23.27% - 8 4 7.76% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.609332 # Inst issue rate -system.cpu.iq.iqInstsAdded 3787 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3291 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 6528 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 +system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate +system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 732 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 734 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 776 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 705 # ITB hits +system.cpu.itb.hits 747 # ITB hits system.cpu.itb.misses 29 # ITB misses system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5854.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2854.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 140500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5440.329218 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2440.329218 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1322000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 593000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5571.428571 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2571.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 78000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -376,66 +360,63 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5477.528090 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1462500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5477.528090 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1462500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 267 # number of overall misses +system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 661500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 114.387820 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 5401 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 738 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 411 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 14367 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3954 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5025 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4444 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3187 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 813 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 290 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1419 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 91 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 46 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr deleted file mode 100644 index 298b6fba0..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout deleted file mode 100644 index 95bc632c8..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:33 2008 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2700000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index ac0ec32b8..8ca1fff45 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..bb8489f81 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..7c13e1d4c --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py quick/00.hello/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 28ff448c6..ddfd1ad69 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 124133 # Simulator instruction rate (inst/s) -host_mem_usage 171628 # Number of bytes of host memory used +host_inst_rate 147781 # Simulator instruction rate (inst/s) +host_mem_usage 191596 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 61574601 # Simulator tick rate (ticks/s) +host_tick_rate 73371409 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100644 index 9f8e7c2e9..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100644 index d906bb79e..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 27 2007 13:46:37 -M5 started Thu Sep 27 20:06:36 2007 -M5 executing on zeep -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 4f7ec60f2..f0bdf09de 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..bb8489f81 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..3560f6496 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py quick/00.hello/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 17374000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index c93b1f19c..5c25b785f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 99969 # Simulator instruction rate (inst/s) -host_mem_usage 193012 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 383001655 # Simulator tick rate (ticks/s) +host_inst_rate 73131 # Simulator instruction rate (inst/s) +host_mem_usage 199016 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 490513834 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 9950000 # Number of ticks simulated +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17374000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,46 +37,37 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses system.cpu.dcache.overall_misses 93 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,30 +142,30 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 2586 # ITB hits system.cpu.itb.misses 11 # ITB misses system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -195,51 +177,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 19900 # number of cpu cycles simulated +system.cpu.numCycles 34748 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr deleted file mode 100644 index f26dcb93f..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout deleted file mode 100644 index c25792a5f..000000000 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 12:58:25 2008 -M5 executing on tater -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 9950000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 653ab3552..766c4f486 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -11,10 +11,68 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb itb tlb tracer workload +CP0_Config=0 +CP0_Config1=0 +CP0_Config1_C2=false +CP0_Config1_CA=false +CP0_Config1_DA=0 +CP0_Config1_DL=0 +CP0_Config1_DS=0 +CP0_Config1_EP=false +CP0_Config1_FP=false +CP0_Config1_IA=0 +CP0_Config1_IL=0 +CP0_Config1_IS=0 +CP0_Config1_M=0 +CP0_Config1_MD=false +CP0_Config1_MMU=0 +CP0_Config1_PC=false +CP0_Config1_WR=false +CP0_Config2=0 +CP0_Config2_M=false +CP0_Config2_SA=0 +CP0_Config2_SL=0 +CP0_Config2_SS=0 +CP0_Config2_SU=0 +CP0_Config2_TA=0 +CP0_Config2_TL=0 +CP0_Config2_TS=0 +CP0_Config2_TU=0 +CP0_Config3=0 +CP0_Config3_DSPP=false +CP0_Config3_LPA=false +CP0_Config3_M=false +CP0_Config3_MT=false +CP0_Config3_SM=false +CP0_Config3_SP=false +CP0_Config3_TL=false +CP0_Config3_VEIC=false +CP0_Config3_VInt=false +CP0_Config_AR=0 +CP0_Config_AT=0 +CP0_Config_BE=0 +CP0_Config_MT=0 +CP0_Config_VI=0 +CP0_EBase_CPUNum=0 +CP0_IntCtl_IPPCI=0 +CP0_IntCtl_IPTI=0 +CP0_PRId=0 +CP0_PRId_CompanyID=0 +CP0_PRId_CompanyOptions=0 +CP0_PRId_ProcessorID=1 +CP0_PRId_Revision=0 +CP0_PerfCtr_M=false +CP0_PerfCtr_W=false +CP0_SrsCtl_HSS=0 +CP0_WatchHi_M=false +UnifiedTLB=true +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,10 +81,13 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system +tlb=system.cpu.tlb tracer=system.cpu.tracer width=1 workload=system.cpu.workload @@ -35,9 +96,15 @@ icache_port=system.membus.port[1] [system.cpu.dtb] type=MipsDTB +size=64 [system.cpu.itb] type=MipsITB +size=64 + +[system.cpu.tlb] +type=MipsUTB +size=64 [system.cpu.tracer] type=ExeTracer @@ -48,13 +115,16 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -63,6 +133,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -70,7 +141,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout new file mode 100755 index 000000000..7b1955a4b --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:16:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:16:42 +M5 executing on zizzer +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py quick/00.hello/mips/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello World! +Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..20921ce17 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -0,0 +1,54 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 24803 # Simulator instruction rate (inst/s) +host_mem_usage 193824 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host +host_tick_rate 12384497 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5656 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2828000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5657 # number of cpu cycles simulated +system.cpu.num_insts 5656 # Number of instructions executed +system.cpu.num_refs 2055 # Number of memory references +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.accesses 0 # DTB accesses +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.hits 0 # DTB hits +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.misses 0 # DTB misses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_accesses 0 # DTB read accesses +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_hits 0 # DTB read hits +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.read_misses 0 # DTB read misses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_accesses 0 # DTB write accesses +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_hits 0 # DTB write hits +system.cpu.tlb.write_misses 0 # DTB write misses +system.cpu.tlb.write_misses 0 # DTB write misses +system.cpu.workload.PROG:num_syscalls 13 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr deleted file mode 100644 index f33d007a7..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout deleted file mode 100644 index 1cc3f6662..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello World! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Aug 14 2007 22:02:23 -M5 started Tue Aug 14 22:02:24 2007 -M5 executing on nacho -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 1b246149f..d6fb3e91a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -67,9 +67,12 @@ CP0_PerfCtr_W=false CP0_SrsCtl_HSS=0 CP0_WatchHi_M=false UnifiedTLB=true +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -78,6 +81,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -95,16 +99,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -113,8 +115,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -135,16 +135,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -153,8 +151,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -175,16 +171,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -193,8 +187,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -226,6 +218,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 @@ -234,6 +227,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -250,7 +244,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout new file mode 100755 index 000000000..a5bd2cd4d --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:16:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:16:42 +M5 executing on zizzer +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py quick/00.hello/mips/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello World! +Exiting @ tick 32322000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index d3bab9d0b..de10d4a74 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11117 # Simulator instruction rate (inst/s) -host_mem_usage 195308 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host -host_tick_rate 38035865 # Simulator tick rate (ticks/s) +host_inst_rate 26568 # Simulator instruction rate (inst/s) +host_mem_usage 201268 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 151609105 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19359000 # Number of ticks simulated +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 32322000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1968000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1728000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,46 +37,37 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3942000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1908 # number of overall hits -system.cpu.dcache.overall_miss_latency 3942000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses system.cpu.dcache.overall_misses 146 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3504000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.621729 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -90,13 +81,13 @@ system.cpu.dtb.write_accesses 0 # DT system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26914.191419 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23914.191419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8155000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 7246000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -108,46 +99,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26914.191419 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8155000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 7246000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26914.191419 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 8155000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 7246000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.855992 # Cycle average of tags in use +system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -162,31 +144,31 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8809000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -198,51 +180,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9959000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9959000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 183.190154 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 38718 # number of cpu cycles simulated +system.cpu.numCycles 64644 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.tlb.accesses 0 # DTB accesses diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr deleted file mode 100644 index 5992f7131..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr +++ /dev/null @@ -1,3 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout deleted file mode 100644 index 4dcddd5ae..000000000 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello World! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:24:29 -M5 started Sun Feb 24 13:24:31 2008 -M5 executing on tater -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 19359000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 73da00d73..970388ae5 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 9a9ac5a12..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1230 # Simulator instruction rate (inst/s) -host_mem_usage 173824 # Number of bytes of host memory used -host_seconds 3.93 # Real time elapsed on the host -host_tick_rate 622698 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2447500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4896 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references -system.cpu.workload.PROG:num_syscalls 11 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..eefaf1737 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py quick/00.hello/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 23e6b5f2c..b09b910ba 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 9753 # Simulator instruction rate (inst/s) -host_mem_usage 173424 # Number of bytes of host memory used -host_seconds 0.58 # Real time elapsed on the host -host_tick_rate 4872477 # Simulator tick rate (ticks/s) +host_inst_rate 25851 # Simulator instruction rate (inst/s) +host_mem_usage 193720 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 13060676 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5656 # Number of instructions simulated +sim_insts 5340 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2828000 # Number of ticks simulated +sim_ticks 2701000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5657 # number of cpu cycles simulated -system.cpu.num_insts 5656 # Number of instructions executed -system.cpu.num_refs 2055 # Number of memory references -system.cpu.workload.PROG:num_syscalls 13 # Number of system calls +system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index 41aec2f86..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7012 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout deleted file mode 100644 index cf86d0964..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,13 +0,0 @@ -Hello World!M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2447500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index ef40ce3fd..f68b9582f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..fcae28521 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py quick/00.hello/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 29031000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 08e810a08..cf7518d98 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,232 +1,205 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153074 # Simulator instruction rate (inst/s) -host_mem_usage 195092 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 524572616 # Simulator tick rate (ticks/s) +host_inst_rate 21374 # Simulator instruction rate (inst/s) +host_mem_usage 201092 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 116036277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16662000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29031000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 565 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.145234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.145234 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.400000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1119 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118203 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.118203 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1119 # number of overall hits -system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118203 # miss rate for overall accesses +system.cpu.dcache.overall_hits 1239 # number of overall hits +system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.118203 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.706581 # Cycle average of tags in use -system.cpu.dcache.total_refs 1134 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use +system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.437500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.437500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6886000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency -system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6886000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses -system.cpu.icache.demand_misses 256 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency +system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4621 # number of overall hits -system.cpu.icache.overall_miss_latency 6886000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses -system.cpu.icache.overall_misses 256 # number of overall misses +system.cpu.icache.overall_hits 5127 # number of overall hits +system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6118000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.043041 # Cycle average of tags in use -system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use +system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7061000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992327 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 388 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4268000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992327 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 388 # number of overall misses +system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4268000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.841445 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 33324 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 58062 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index 2a6ac4135..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout deleted file mode 100644 index 12e9a5d09..000000000 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,13 +0,0 @@ -Hello World!M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Sun Feb 24 13:28:47 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 16662000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 74f6c930e..1a9a034e8 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..60f35ee0f --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 23 2009 23:45:19 +M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch +M5 started Feb 23 2009 23:59:09 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 5484500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index f834f694b..454f55a63 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21996 # Simulator instruction rate (inst/s) -host_mem_usage 172228 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 12789916 # Simulator tick rate (ticks/s) +host_inst_rate 165270 # Simulator instruction rate (inst/s) +host_mem_usage 192880 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 95268287 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 8472 # Number of instructions simulated +sim_insts 9484 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4930500 # Number of ticks simulated +sim_ticks 5484500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9862 # number of cpu cycles simulated -system.cpu.num_insts 8472 # Number of instructions executed -system.cpu.num_refs 1765 # Number of memory references +system.cpu.numCycles 10970 # number of cpu cycles simulated +system.cpu.num_insts 9484 # Number of instructions executed +system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr deleted file mode 100644 index 863f1adb9..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,5 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'rdtsc' unimplemented diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout deleted file mode 100644 index 302f58c0c..000000000 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,14 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Oct 25 2007 18:49:38 -M5 started Thu Oct 25 18:49:42 2007 -M5 executing on nacho -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4930500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..d1edd6c59 --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,193 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=10 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..94d399eab --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: instruction 'fldcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..a84f40e19 --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:37:33 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 29717000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..b8a17302a --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,205 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 139542 # Simulator instruction rate (inst/s) +host_mem_usage 200396 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 436046426 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 9484 # Number of instructions simulated +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29717000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses +system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1835 # number of overall hits +system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses +system.cpu.dcache.overall_misses 152 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 80.867418 # Cycle average of tags in use +system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 6873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6645 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.033173 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.033173 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 29.144737 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 6873 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.demand_hits 6645 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.033173 # miss rate for demand accesses +system.cpu.icache.demand_misses 228 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.033173 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 6873 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 6645 # number of overall hits +system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.033173 # miss rate for overall accesses +system.cpu.icache.overall_misses 228 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.033173 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 106.639571 # Cycle average of tags in use +system.cpu.icache.total_refs 6645 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 360 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 128.121989 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 59434 # number of cpu cycles simulated +system.cpu.num_insts 9484 # Number of instructions executed +system.cpu.num_refs 1987 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index d966db2bf..9c8da927d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -385,6 +378,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 @@ -393,6 +387,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -409,7 +404,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout new file mode 100755 index 000000000..7101807df --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -0,0 +1,19 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:23:16 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Hello world! +Hello world! +Exiting @ tick 14251500 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 4a5d707e1..783867939 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,193 +1,187 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 722 # Number of BTB hits -global.BPredUnit.BTBLookups 3569 # Number of BTB lookups -global.BPredUnit.RASInCorrect 133 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1125 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2392 # Number of conditional branches predicted -global.BPredUnit.lookups 4127 # Number of BP lookups -global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. -host_inst_rate 41846 # Simulator instruction rate (inst/s) -host_mem_usage 152588 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host -host_tick_rate 23650670 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 33 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 36 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1975 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2036 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1163 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1158 # Number of stores inserted to the mem dependence unit. +host_inst_rate 106034 # Simulator instruction rate (inst/s) +host_mem_usage 203088 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 118060043 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 6363000 # Number of ticks simulated -system.cpu.commit.COM:branches 1724 # Number of branches committed -system.cpu.commit.COM:branches_0 862 # Number of branches committed -system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 145 # number cycles where commit BW limit reached +sim_insts 12773 # Number of instructions simulated +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 14251500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4733 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5548 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 2102 # Number of branches committed +system.cpu.commit.COM:branches_0 1051 # Number of branches committed +system.cpu.commit.COM:branches_1 1051 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12623 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7897 6256.04% - 1 2220 1758.69% - 2 993 786.66% - 3 507 401.65% - 4 332 263.01% - 5 219 173.49% - 6 199 157.65% - 7 111 87.93% - 8 145 114.87% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5640 # Number of instructions committed -system.cpu.commit.COM:count_1 5641 # Number of instructions committed -system.cpu.commit.COM:loads 1958 # Number of loads committed -system.cpu.commit.COM:loads_0 979 # Number of loads committed -system.cpu.commit.COM:loads_1 979 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::samples 22837 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 16880 73.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 326 1.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 268 1.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 122 0.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 22837 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.560800 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.272250 # Number of insts commited each cycle +system.cpu.commit.COM:count 12807 # Number of instructions committed +system.cpu.commit.COM:count_0 6403 # Number of instructions committed +system.cpu.commit.COM:count_1 6404 # Number of instructions committed +system.cpu.commit.COM:loads 2370 # Number of loads committed +system.cpu.commit.COM:loads_0 1185 # Number of loads committed +system.cpu.commit.COM:loads_1 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 3582 # Number of memory references committed -system.cpu.commit.COM:refs_0 1791 # Number of memory references committed -system.cpu.commit.COM:refs_1 1791 # Number of memory references committed +system.cpu.commit.COM:refs 4100 # Number of memory references committed +system.cpu.commit.COM:refs_0 2050 # Number of memory references committed +system.cpu.commit.COM:refs_1 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 885 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions +system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8502 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5623 # Number of Instructions Simulated -system.cpu.committedInsts_1 5624 # Number of Instructions Simulated -system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 2.263383 # CPI: Cycles Per Instruction -system.cpu.cpi_1 2.262980 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.131591 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 12116.724739 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10527.918782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.093212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.063982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 197 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 9139.837398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8686.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.378695 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6386 # Number of Instructions Simulated +system.cpu.committedInsts_1 6387 # Number of Instructions Simulated +system.cpu.committedInsts_total 12773 # Number of Instructions Simulated +system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction +system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.266082 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4703 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4703 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3801 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9098500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9098500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.191792 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 902 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 531 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 531 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3585500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3585500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.078886 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 371 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 371 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4703 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4703 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3801 # number of overall hits -system.cpu.dcache.overall_hits_0 3801 # number of overall hits +system.cpu.dcache.overall_hits 4550 # number of overall hits +system.cpu.dcache.overall_hits_0 4550 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9098500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9098500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.191792 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 902 # number of overall misses -system.cpu.dcache.overall_misses_0 902 # number of overall misses +system.cpu.dcache.overall_misses 1105 # number of overall misses +system.cpu.dcache.overall_misses_0 1105 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 531 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 531 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3585500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3585500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.078886 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 371 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 371 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -195,173 +189,166 @@ system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 214.045910 # Cycle average of tags in use -system.cpu.dcache.total_refs 3853 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use +system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2156 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 253 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 362 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22792 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 17306 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3860 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1667 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 387 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 5201 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 6300 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 5076 # DTB hits -system.cpu.dtb.misses 125 # DTB misses -system.cpu.dtb.read_accesses 3261 # DTB read accesses +system.cpu.dtb.hits 6155 # DTB hits +system.cpu.dtb.misses 145 # DTB misses +system.cpu.dtb.read_accesses 4144 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3178 # DTB read hits -system.cpu.dtb.read_misses 83 # DTB read misses -system.cpu.dtb.write_accesses 1940 # DTB write accesses +system.cpu.dtb.read_hits 4056 # DTB read hits +system.cpu.dtb.read_misses 88 # DTB read misses +system.cpu.dtb.write_accesses 2156 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1898 # DTB write hits -system.cpu.dtb.write_misses 42 # DTB write misses -system.cpu.fetch.Branches 4127 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3105 # Number of cache lines fetched -system.cpu.fetch.Cycles 7305 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 481 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 25026 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1246 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.324271 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3105 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1272 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.966371 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 12676 -system.cpu.fetch.rateDist.min_value 0 - 0 8531 6730.04% - 1 309 243.77% - 2 245 193.28% - 3 260 205.11% - 4 342 269.80% - 5 308 242.98% - 6 324 255.60% - 7 261 205.90% - 8 2096 1653.52% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 10171.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7742.694805 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.226731 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 704 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 704 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.198390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 616 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 616 # number of ReadReq MSHR misses +system.cpu.dtb.write_hits 2099 # DTB write hits +system.cpu.dtb.write_misses 57 # DTB write misses +system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched +system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 22904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 17622 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 416 1.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 353 1.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 477 2.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 425 1.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 349 1.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 442 1.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 261 1.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2559 11.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.897727 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3105 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3105 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2401 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2401 # number of demand (read+write) hits +system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 7161000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.226731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 704 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 704 # number of demand (read+write) misses +system.cpu.icache.demand_misses 841 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.198390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 616 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 616 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3105 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3105 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2401 # number of overall hits -system.cpu.icache.overall_hits_0 2401 # number of overall hits +system.cpu.icache.overall_hits 3272 # number of overall hits +system.cpu.icache.overall_hits_0 3272 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 7161000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 7161000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.226731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 704 # number of overall misses -system.cpu.icache.overall_misses_0 704 # number of overall misses +system.cpu.icache.overall_misses 841 # number of overall misses +system.cpu.icache.overall_misses_0 841 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4769500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4769500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.198390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 616 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 616 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -369,116 +356,107 @@ system.cpu.icache.overall_mshr_uncacheable_latency_1 0 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 6 # number of replacements system.cpu.icache.replacements_0 6 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 616 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 313.697202 # Cycle average of tags in use -system.cpu.icache.total_refs 2401 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use +system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 51 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2444 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1228 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1216 # Number of branches executed -system.cpu.iew.EXEC:nop 128 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 67 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate -system.cpu.iew.EXEC:refs 5219 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2580 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2639 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1956 # Number of stores executed -system.cpu.iew.EXEC:stores_0 977 # Number of stores executed -system.cpu.iew.EXEC:stores_1 979 # Number of stores executed +system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3160 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed +system.cpu.iew.EXEC:nop 135 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate +system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2175 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10432 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5228 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5204 # num instructions consuming a value -system.cpu.iew.WB:count 15495 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7763 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7732 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.540838 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.769893 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.770945 # average fanout of values written-back +system.cpu.iew.WB:consumers 11901 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value +system.cpu.iew.WB:count 18426 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8037 # num instructions producing a value -system.cpu.iew.WB:producers_0 4025 # num instructions producing a value -system.cpu.iew.WB:producers_1 4012 # num instructions producing a value -system.cpu.iew.WB:rate 1.217490 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.609963 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.607527 # insts written-back per cycle -system.cpu.iew.WB:sent 15706 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7855 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7851 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1023 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 34 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4011 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 445 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2321 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19928 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3263 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1603 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1660 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 892 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 16126 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 9240 # num instructions producing a value +system.cpu.iew.WB:producers_0 4646 # num instructions producing a value +system.cpu.iew.WB:producers_1 4594 # num instructions producing a value +system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle +system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1667 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 996 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 351 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 53 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 67 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1057 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 346 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 133 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 810 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 213 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.441817 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.441895 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.883712 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8497 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5747 67.64% # Type of FU issued + IntAlu 6830 67.10% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +465,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1738 20.45% # Type of FU issued - MemWrite 1007 11.85% # Type of FU issued + MemRead 2173 21.35% # Type of FU issued + MemWrite 1171 11.50% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8521 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5702 66.92% # Type of FU issued + IntAlu 6842 67.01% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +482,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1797 21.09% # Type of FU issued - MemWrite 1017 11.94% # Type of FU issued + MemRead 2230 21.84% # Type of FU issued + MemWrite 1134 11.11% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 17018 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 11449 67.28% # Type of FU issued + IntAlu 13672 67.05% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +499,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3535 20.77% # Type of FU issued - MemWrite 2024 11.89% # Type of FU issued + MemRead 4403 21.59% # Type of FU issued + MemWrite 2305 11.30% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 83 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 97 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010577 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004877 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005700 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 9 5.00% # attempts to use FU when none available + IntAlu 13 7.56% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,136 +521,138 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 107 59.44% # attempts to use FU when none available - MemWrite 64 35.56% # attempts to use FU when none available + MemRead 96 55.81% # attempts to use FU when none available + MemWrite 63 36.63% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 12676 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6060 4780.69% - 1 2068 1631.43% - 2 1684 1328.49% - 3 1173 925.37% - 4 835 658.73% - 5 514 405.49% - 6 255 201.17% - 7 73 57.59% - 8 14 11.04% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.337157 # Inst issue rate -system.cpu.iq.iqInstsAdded 19755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17018 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7576 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4636 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 3160 # ITB accesses +system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% +system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 22904 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 +system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate +system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 4162 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 3105 # ITB hits -system.cpu.itb.misses 55 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses_0 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6844.827586 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3844.827586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 992500 # number of ReadExReq miss cycles +system.cpu.itb.hits 4113 # ITB hits +system.cpu.itb.misses 49 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses_0 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 557500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 557500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses_0 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 6525.277435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3525.277435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997540 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997540 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 811 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 811 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses_0 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6103.448276 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3103.448276 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 177000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 177000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses_0 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 90000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 90000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses_0 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 958 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 958 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6284500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6284500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3416500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3416500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 958 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 958 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency @@ -680,26 +660,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_hits_0 2 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6284500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6284500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 956 # number of overall misses -system.cpu.l2cache.overall_misses_0 956 # number of overall misses +system.cpu.l2cache.overall_misses 969 # number of overall misses +system.cpu.l2cache.overall_misses_0 969 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3416500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3416500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -707,45 +687,45 @@ system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 782 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 419.781607 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 12727 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 743 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 17661 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 854 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 27553 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21741 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 16306 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3686 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1667 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 906 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8204 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1282 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 58 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 32 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1303 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 28504 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2494 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr deleted file mode 100644 index 0ce82a0be..000000000 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ /dev/null @@ -1,5 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout deleted file mode 100644 index 9d1a14d46..000000000 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ /dev/null @@ -1,15 +0,0 @@ -Hello world! -Hello world! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:35 2008 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 6363000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index c6ceaa121..102ce19a3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout new file mode 100755 index 000000000..f1994d462 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -0,0 +1,26 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:29:06 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:30:50 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +STTW: Passed +Done +Exiting @ tick 27756500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 29c5e75be..67e62423e 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,275 +1,257 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 2713 # Number of BTB hits -global.BPredUnit.BTBLookups 6851 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2011 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 7546 # Number of conditional branches predicted -global.BPredUnit.lookups 7546 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 33487 # Simulator instruction rate (inst/s) -host_mem_usage 153160 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 49468437 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2926 # Number of stores inserted to the mem dependence unit. +host_inst_rate 66771 # Simulator instruction rate (inst/s) +host_mem_usage 203496 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 128111456 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10411 # Number of instructions simulated -sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15392500 # Number of ticks simulated -system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 88 # number cycles where commit BW limit reached +sim_insts 14449 # Number of instructions simulated +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27756500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 4398 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 9844 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11413 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 11413 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 3359 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 27698 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22133 7990.83% - 1 3105 1121.02% - 2 1159 418.44% - 3 591 213.37% - 4 306 110.48% - 5 82 29.61% - 6 196 70.76% - 7 38 13.72% - 8 88 31.77% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 10976 # Number of instructions committed -system.cpu.commit.COM:loads 1462 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::samples 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 34594 80.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 4804 11.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1741 4.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 720 1.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 413 0.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 144 0.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 196 0.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 51 0.12% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 103 0.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.354838 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 0.957636 # Number of insts commited each cycle +system.cpu.commit.COM:count 15175 # Number of instructions committed +system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2760 # Number of memory references committed +system.cpu.commit.COM:refs 3674 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2011 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13116 # The number of squashed insts skipped by commit -system.cpu.committedInsts 10411 # Number of Instructions Simulated -system.cpu.committedInsts_total 10411 # Number of Instructions Simulated -system.cpu.cpi 2.957065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.957065 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9364.130435 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7068.181818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2205 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 861500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.040052 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 466500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.028733 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses +system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit +system.cpu.committedInsts 14449 # Number of Instructions Simulated +system.cpu.committedInsts_total 14449 # Number of Instructions Simulated +system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9880.434783 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6966.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1062 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2272500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.178019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 230 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 125 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 731500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 21.736842 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3589 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9732.919255 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3267 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3134000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.089719 # miss rate for demand accesses -system.cpu.dcache.demand_misses 322 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 151 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1198000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047646 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses +system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3589 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9732.919255 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3267 # number of overall hits -system.cpu.dcache.overall_miss_latency 3134000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.089719 # miss rate for overall accesses -system.cpu.dcache.overall_misses 322 # number of overall misses -system.cpu.dcache.overall_mshr_hits 151 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1198000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047646 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 4728 # number of overall hits +system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses +system.cpu.dcache.overall_misses 558 # number of overall misses +system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.780967 # Cycle average of tags in use -system.cpu.dcache.total_refs 3304 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use +system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4065 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 37568 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 13467 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 10101 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2901 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 65 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 7546 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4905 # Number of cache lines fetched -system.cpu.fetch.Cycles 16129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 41611 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2098 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.245111 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4905 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2713 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.351621 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 30599 -system.cpu.fetch.rateDist.min_value 0 - 0 19398 6339.42% - 1 4890 1598.09% - 2 619 202.29% - 3 711 232.36% - 4 788 257.52% - 5 642 209.81% - 6 612 200.01% - 7 196 64.05% - 8 2743 896.43% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 4905 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8897.590361 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6462.162162 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4490 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3692500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.084608 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 415 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.075433 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses +system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched +system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 47090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 30448 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 7532 15.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1217 2.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 1059 2.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 1060 2.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1193 2.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 711 1.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 327 0.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3543 7.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 47090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.236929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.372442 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.135135 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4905 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8897.590361 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency -system.cpu.icache.demand_hits 4490 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3692500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.084608 # miss rate for demand accesses -system.cpu.icache.demand_misses 415 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.075433 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency +system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses +system.cpu.icache.demand_misses 535 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4905 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8897.590361 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency +system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4490 # number of overall hits -system.cpu.icache.overall_miss_latency 3692500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.084608 # miss rate for overall accesses -system.cpu.icache.overall_misses 415 # number of overall misses -system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2391000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.075433 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses +system.cpu.icache.overall_hits 6821 # number of overall hits +system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses +system.cpu.icache.overall_misses 535 # number of overall misses +system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 370 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 230.770092 # Cycle average of tags in use -system.cpu.icache.total_refs 4490 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use +system.cpu.icache.total_refs 6821 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3077 # Number of branches executed -system.cpu.iew.EXEC:nop 1794 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.558825 # Inst execution rate -system.cpu.iew.EXEC:refs 4529 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2104 # Number of stores executed +system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4842 # Number of branches executed +system.cpu.iew.EXEC:nop 2091 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate +system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2454 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9158 # num instructions consuming a value -system.cpu.iew.WB:count 16580 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.828347 # average fanout of values written-back +system.cpu.iew.WB:consumers 13039 # num instructions consuming a value +system.cpu.iew.WB:count 23891 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7586 # num instructions producing a value -system.cpu.iew.WB:rate 0.538556 # insts written-back per cycle -system.cpu.iew.WB:sent 16781 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2212 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 612 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2926 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 24197 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2425 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2802 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 17204 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 10787 # num instructions producing a value +system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle +system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2901 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1596 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1628 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 689 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1523 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.338173 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.338173 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 20006 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 14491 72.43% # Type of FU issued + IntAlu 21395 73.22% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +260,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2890 14.45% # Type of FU issued - MemWrite 2625 13.12% # Type of FU issued + MemRead 4720 16.15% # Type of FU issued + MemWrite 3105 10.63% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 187 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009347 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 51 27.27% # attempts to use FU when none available + IntAlu 40 23.12% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,129 +278,129 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 24 12.83% # attempts to use FU when none available - MemWrite 112 59.89% # attempts to use FU when none available + MemRead 20 11.56% # attempts to use FU when none available + MemWrite 113 65.32% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 30599 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 21747 7107.10% - 1 3624 1184.35% - 2 2137 698.39% - 3 1557 508.84% - 4 751 245.43% - 5 397 129.74% - 6 290 94.77% - 7 60 19.61% - 8 36 11.77% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.649841 # Inst issue rate -system.cpu.iq.iqInstsAdded 21791 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20006 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 10183 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 8044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5755.813953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2755.813953 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 495000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% +system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 47090 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 +system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate +system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 237000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5417.824074 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2417.824074 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2340500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990826 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 432 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990826 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5631.578947 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2631.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 107000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 50000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 522 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5473.938224 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2835500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992337 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 518 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1281500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992337 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 522 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5473.938224 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2835500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992337 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 518 # number of overall misses +system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 503 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1281500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992337 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 518 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 257.005987 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 30786 # number of cpu cycles simulated -system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 14813 # Number of cycles rename is idle -system.cpu.rename.RENAME:RenameLookups 51330 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 29671 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 24234 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8843 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2901 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 14366 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 3812 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 646 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4446 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 683 # count of temporary serializing insts renamed -system.cpu.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 3415 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 55514 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed +system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr deleted file mode 100644 index eb1796ead..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index a1a3cadc4..c81ee3264 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index da5a7c7d1..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2595 # Simulator instruction rate (inst/s) -host_mem_usage 173616 # Number of bytes of host memory used -host_seconds 4.23 # Real time elapsed on the host -host_tick_rate 1303618 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5514000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11029 # number of cpu cycles simulated -system.cpu.num_insts 10976 # Number of instructions executed -system.cpu.num_refs 2770 # Number of memory references -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout index ee061a6c6..cb610b0c6 100644..100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py quick/02.insttest/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -9,16 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 27 2008 17:54:12 -M5 started Wed Feb 27 18:07:27 2008 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 15392500 because target called exit() +Exiting @ tick 7618500 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 186158b96..d9897842c 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1240763 # Simulator instruction rate (inst/s) -host_mem_usage 175872 # Number of bytes of host memory used -host_seconds 1292.50 # Real time elapsed on the host -host_tick_rate 738827746 # Simulator tick rate (ticks/s) +host_inst_rate 61727 # Simulator instruction rate (inst/s) +host_mem_usage 193528 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 30956425 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1603680167 # Number of instructions simulated -sim_seconds 0.954932 # Number of seconds simulated -sim_ticks 954931687500 # Number of ticks simulated +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7618500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1909863376 # number of cpu cycles simulated -system.cpu.num_insts 1603680167 # Number of instructions executed -system.cpu.num_refs 607157396 # Number of memory references +system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index 320065be7..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout deleted file mode 100644 index c0bb8f23f..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,24 +0,0 @@ -Begining test of difficult SPARC instructions... -LDSTUB: Passed -SWAP: Passed -CAS FAIL: Passed -CAS WORK: Passed -CASX FAIL: Passed -CASX WORK: Passed -LDTX: Passed -LDTW: Passed -STTW: Passed -Done -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5514000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index f4a82a8e3..8777df95f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index a0c51dd80..65fc22a94 100644..100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:17:34 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py quick/02.insttest/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -9,16 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 12:26:21 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 25237000 because target called exit() +Exiting @ tick 42735000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 882e0c177..323f23c0d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,234 +1,207 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23807 # Simulator instruction rate (inst/s) -host_mem_usage 194964 # Number of bytes of host memory used -host_seconds 0.46 # Real time elapsed on the host -host_tick_rate 54716973 # Simulator tick rate (ticks/s) +host_inst_rate 71328 # Simulator instruction rate (inst/s) +host_mem_usage 200972 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 200611199 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25237000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1458000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000043 # Number of seconds simulated +sim_ticks 42735000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2835000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.081269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2520000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 18.436620 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2595 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4293000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.057734 # miss rate for demand accesses -system.cpu.dcache.demand_misses 159 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses +system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.057734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 159 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2595 # number of overall hits -system.cpu.dcache.overall_miss_latency 4293000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.057734 # miss rate for overall accesses -system.cpu.dcache.overall_misses 159 # number of overall misses +system.cpu.dcache.overall_hits 3513 # number of overall hits +system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses +system.cpu.dcache.overall_misses 155 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.057734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 159 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 99.913779 # Cycle average of tags in use -system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use +system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26908.127208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23908.127208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7615000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6766000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 37.911661 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26908.127208 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency -system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7615000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses -system.cpu.icache.demand_misses 283 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency +system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses +system.cpu.icache.demand_misses 280 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6766000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26908.127208 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency +system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10729 # number of overall hits -system.cpu.icache.overall_miss_latency 7615000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses -system.cpu.icache.overall_misses 283 # number of overall misses +system.cpu.icache.overall_hits 14941 # number of overall hits +system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses +system.cpu.icache.overall_misses 280 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6766000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 154.924957 # Cycle average of tags in use -system.cpu.icache.total_refs 10729 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use +system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2024000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 968000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 337 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994065 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3685000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994065 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 335 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 391000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 187000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006289 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 425 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9729000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995294 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995294 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 425 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9729000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995294 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 423 # number of overall misses +system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 416 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995294 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 176.975795 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 50474 # number of cpu cycles simulated -system.cpu.num_insts 10976 # Number of instructions executed -system.cpu.num_refs 2770 # Number of memory references -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.numCycles 85470 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index eb1796ead..000000000 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index aaa49012b..56dec3815 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -35,7 +35,8 @@ side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -45,15 +46,18 @@ do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu0.interrupts itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu0.tracer width=1 @@ -68,16 +72,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -86,8 +88,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -108,16 +108,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -126,8 +124,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -136,6 +132,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=AlphaInterrupts + [system.cpu0.itb] type=AlphaITB size=48 @@ -145,7 +144,8 @@ type=ExeTracer [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=1 defer_registration=false @@ -155,15 +155,18 @@ do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu1.interrupts itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu1.tracer width=1 @@ -178,16 +181,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -196,8 +197,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -218,16 +217,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -236,8 +233,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -246,6 +241,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=AlphaInterrupts + [system.cpu1.itb] type=AlphaITB size=48 @@ -264,6 +262,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -283,6 +282,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -300,10 +300,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -313,16 +314,14 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -331,8 +330,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -349,16 +346,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -367,8 +362,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -383,6 +376,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.membus.responder.pio @@ -407,19 +401,13 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -431,12 +419,20 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.toL2Bus.responder.pio @@ -460,10 +456,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu0 +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -473,30 +480,25 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu0 -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -865,16 +867,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -945,7 +953,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr new file mode 100755 index 000000000..5a1d0bef0 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: 97861500: Trying to launch CPU number 1! +For more information see: http://www.m5sim.org/warn/8f7d2563 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout new file mode 100755 index 000000000..8c40366bc --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:50 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index df1b8566f..8ed468432 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1110947 # Simulator instruction rate (inst/s) -host_mem_usage 261416 # Number of bytes of host memory used -host_seconds 56.81 # Real time elapsed on the host -host_tick_rate 32921847339 # Simulator tick rate (ticks/s) +host_inst_rate 2804596 # Simulator instruction rate (inst/s) +host_mem_usage 292704 # Number of bytes of host memory used +host_seconds 22.52 # Real time elapsed on the host +host_tick_rate 83058483755 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63114046 # Number of instructions simulated -sim_seconds 1.870335 # Number of seconds simulated -sim_ticks 1870335151500 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8975647 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7292074 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683573 # number of ReadReq misses -system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5746071 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5372265 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses +sim_insts 63154034 # Number of instructions simulated +sim_seconds 1.870336 # Number of seconds simulated +sim_ticks 1870335522500 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses +system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625595 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14721718 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12664339 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057379 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,67 +46,58 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14721718 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12664339 # number of overall hits +system.cpu0.dcache.overall_hits 12672559 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057379 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2057371 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1978971 # number of replacements -system.cpu0.dcache.sampled_refs 1979483 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1978962 # number of replacements +system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 504.827578 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115252 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 396793 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15082956 # DTB hits +system.cpu0.dtb.hits 15091429 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9148379 # DTB read hits +system.cpu0.dtb.read_hits 9154530 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5934577 # DTB write hits +system.cpu0.dtb.write_hits 5936899 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57190139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56305276 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 884863 # number of ReadReq misses +system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 63.637672 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57190139 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.demand_hits 56305276 # number of demand (read+write) hits +system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses -system.cpu0.icache.demand_misses 884863 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_misses 885000 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,51 +105,42 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57190139 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56305276 # number of overall hits +system.cpu0.icache.overall_hits 56345132 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses -system.cpu0.icache.overall_misses 884863 # number of overall misses +system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_misses 885000 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 884267 # number of replacements -system.cpu0.icache.sampled_refs 884779 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 884404 # number of replacements +system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use -system.cpu0.icache.total_refs 56305276 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use +system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles -system.cpu0.itb.accesses 3858846 # ITB accesses +system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles +system.cpu0.itb.accesses 3859041 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855361 # ITB hits +system.cpu0.itb.hits 3855556 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183273 # number of callpals executed +system.cpu0.kern.callpal 183291 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3762 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168018 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168035 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed @@ -168,45 +150,45 @@ system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # nu system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197102 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174851 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 71004 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101696 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 101705 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141425 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1870334944000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125190500 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17106650000 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.980748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684599 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1156 -system.cpu0.kern.mode_good_user 1157 +system.cpu0.kern.ipl_used_31 0.684617 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1157 +system.cpu0.kern.mode_good_user 1158 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1157 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7091 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163047 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1869377939000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 957004000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.swap_context 3763 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed @@ -238,10 +220,10 @@ system.cpu0.kern.syscall_98 2 0.88% 97.35% # nu system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.numCycles 3740670191 # number of cpu cycles simulated -system.cpu0.num_insts 57182083 # Number of instructions executed -system.cpu0.num_refs 15322406 # Number of memory references +system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles +system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.num_insts 57222076 # Number of instructions executed +system.cpu0.num_refs 15330887 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses @@ -255,12 +237,12 @@ system.cpu1.dcache.StoreCondReq_hits 13438 # nu system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses +system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -269,10 +251,10 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -284,32 +266,23 @@ system.cpu1.dcache.overall_accesses 1884270 # nu system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1812115 # number of overall hits +system.cpu1.dcache.overall_hits 1812118 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 72155 # number of overall misses +system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 72152 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 62341 # number of replacements -system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 62338 # number of replacements +system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 30850 # number of writebacks +system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 30848 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations system.cpu1.dtb.hits 1914885 # DTB hits @@ -322,25 +295,25 @@ system.cpu1.dtb.write_accesses 103280 # DT system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses -system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -348,35 +321,26 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_hits 5832136 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses -system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103630 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 103097 # number of replacements -system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 103091 # number of replacements +system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 427.126316 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.itb.accesses 1469938 # ITB accesses @@ -403,7 +367,7 @@ system.cpu1.kern.callpal_imb 38 0.12% 100.00% # nu system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl @@ -414,8 +378,8 @@ system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # nu system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1870124056000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1859122637500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl @@ -433,9 +397,9 @@ system.cpu1.kern.mode_switch_good 1.608089 # fr system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed @@ -456,8 +420,8 @@ system.cpu1.kern.syscall_74 8 8.00% 97.00% # nu system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.numCycles 3740248139 # number of cpu cycles simulated -system.cpu1.num_insts 5931963 # Number of instructions executed +system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.num_insts 5931958 # Number of instructions executed system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). @@ -513,49 +477,40 @@ system.iocache.overall_mshr_miss_rate 0 # ms system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41695 # number of replacements system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.435434 # Cycle average of tags in use +system.iocache.tagsinuse 0.435437 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759614 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354068 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 964534 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1759731 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 964536 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses -system.l2c.Writeback_accesses 427643 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427643 # number of Writeback hits +system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses +system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427641 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.789371 # Average number of references to valid blocks. +system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030394 # number of demand (read+write) accesses +system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1759614 # number of demand (read+write) hits +system.l2c.demand_hits 1759731 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses -system.l2c.demand_misses 1270780 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses +system.l2c.demand_misses 1270783 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -563,36 +518,27 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030394 # number of overall (read+write) accesses +system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1759614 # number of overall hits +system.l2c.overall_hits 1759731 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses -system.l2c.overall_misses 1270780 # number of overall misses +system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses +system.l2c.overall_misses 1270783 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1056801 # number of replacements -system.l2c.sampled_refs 1091450 # Sample count of references to valid blocks. +system.l2c.replacements 1056803 # number of replacements +system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30522.435313 # Cycle average of tags in use -system.l2c.total_refs 1953009 # Total number of references to valid blocks. +system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use +system.l2c.total_refs 1952499 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123879 # number of writebacks +system.l2c.writebacks 123882 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr deleted file mode 100644 index 4e60f8a9d..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ /dev/null @@ -1,6 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... -warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout deleted file mode 100644 index 5f45dab42..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 13 2008 00:33:19 -M5 started Wed Feb 13 00:38:27 2008 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1870335151500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal index c2aeea3f1..6129834bd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal @@ -60,6 +60,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -71,6 +72,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index f47a4495c..15e3ec649 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -35,7 +35,8 @@ side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -45,15 +46,18 @@ do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -68,16 +72,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -86,8 +88,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -108,16 +108,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -126,8 +124,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -136,6 +132,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaITB size=48 @@ -154,6 +153,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -173,6 +173,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -190,10 +191,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -203,16 +205,14 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -221,8 +221,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -239,16 +237,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -257,8 +253,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -273,6 +267,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.membus.responder.pio @@ -297,19 +292,13 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -321,12 +310,20 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 default=system.toL2Bus.responder.pio @@ -350,10 +347,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -363,30 +371,25 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -755,16 +758,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -835,7 +844,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr new file mode 100755 index 000000000..83c71fc5c --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout new file mode 100755 index 000000000..778e7a3b4 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:52 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 082e17724..749efa0bc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1474278 # Simulator instruction rate (inst/s) -host_mem_usage 260680 # Number of bytes of host memory used -host_seconds 40.70 # Real time elapsed on the host -host_tick_rate 44928072322 # Simulator tick rate (ticks/s) +host_inst_rate 2844723 # Simulator instruction rate (inst/s) +host_mem_usage 291452 # Number of bytes of host memory used +host_seconds 21.11 # Real time elapsed on the host +host_tick_rate 86676065750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59995479 # Number of instructions simulated -sim_seconds 1.828355 # Number of seconds simulated -sim_ticks 1828355496000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits +sim_insts 60038305 # Number of instructions simulated +sim_seconds 1.829332 # Number of seconds simulated +sim_ticks 1829332258000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7801378 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721676 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses -system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866562 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 13552150 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121093 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,67 +46,58 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13552150 # number of overall hits +system.cpu.dcache.overall_hits 13560932 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121093 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121129 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2042665 # number of replacements -system.cpu.dcache.sampled_refs 2043177 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029602 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428885 # number of writebacks +system.cpu.dcache.writebacks 428893 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053818 # DTB hits +system.cpu.dtb.hits 16062925 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703850 # DTB read hits +system.cpu.dtb.read_hits 9710427 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6349968 # DTB write hits +system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087262 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920055 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229474 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 59087262 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920055 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,42 +105,33 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087262 # number of overall hits +system.cpu.icache.overall_hits 59129922 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920055 # number of overall misses +system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_misses 920221 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 919428 # number of replacements -system.cpu.icache.sampled_refs 919940 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919594 # number of replacements +system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use -system.cpu.icache.total_refs 59087262 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use +system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979217 # ITB accesses +system.cpu.idle_fraction 0.983585 # Percentage of idle cycles +system.cpu.itb.accesses 4979654 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974211 # ITB hits +system.cpu.itb.hits 4974648 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192139 # number of callpals executed +system.cpu.kern.callpal 192180 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -157,50 +139,50 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal_swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1866 1.02% 42.14% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105623 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149035 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355288500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087557500 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80238000 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1908 -system.cpu.kern.mode_good_user 1737 +system.cpu.kern.ipl_used_31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1909 +system.cpu.kern.mode_good_user 1738 system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1737 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5949 # number of protection mode switches +system.cpu.kern.mode_switch_user 1738 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056192000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -233,10 +215,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 3656710883 # number of cpu cycles simulated -system.cpu.num_insts 59995479 # Number of instructions executed -system.cpu.num_refs 16302129 # Number of memory references +system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles +system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.num_insts 60038305 # Number of instructions executed +system.cpu.num_refs 16311238 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -291,49 +273,40 @@ system.iocache.overall_mshr_miss_rate 0 # ms system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41686 # number of replacements system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.226223 # Cycle average of tags in use +system.iocache.tagsinuse 1.225570 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658874 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696454 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361965 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962420 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1696652 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 962419 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses +system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428893 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.726821 # Average number of references to valid blocks. +system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963216 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1696454 # number of demand (read+write) hits +system.l2c.demand_hits 1696652 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427496 # miss rate for demand accesses -system.l2c.demand_misses 1266762 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses +system.l2c.demand_misses 1266765 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -341,36 +314,27 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963216 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1696454 # number of overall hits +system.l2c.overall_hits 1696652 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427496 # miss rate for overall accesses -system.l2c.overall_misses 1266762 # number of overall misses +system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses +system.l2c.overall_misses 1266765 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050727 # number of replacements -system.l2c.sampled_refs 1081066 # Sample count of references to valid blocks. +system.l2c.replacements 1050724 # number of replacements +system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30223.986648 # Cycle average of tags in use -system.l2c.total_refs 1866807 # Total number of references to valid blocks. +system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use +system.l2c.total_refs 1867269 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119145 # number of writebacks +system.l2c.writebacks 119147 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr deleted file mode 100644 index 7e35fafed..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout deleted file mode 100644 index 830f4d057..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 13 2008 00:33:19 -M5 started Wed Feb 13 00:37:45 2008 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1828355496000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal index 7930e9e46..f17158b67 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 1181dac96..f8e47e1b8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -35,7 +35,8 @@ side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -45,11 +46,13 @@ do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu0.interrupts itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 @@ -66,16 +69,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -84,8 +85,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -106,16 +105,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -124,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -134,6 +129,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=AlphaInterrupts + [system.cpu0.itb] type=AlphaITB size=48 @@ -143,7 +141,8 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=1 defer_registration=false @@ -153,11 +152,13 @@ do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu1.interrupts itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 @@ -174,16 +175,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -192,8 +191,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -214,16 +211,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -232,8 +227,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -242,6 +235,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=AlphaInterrupts + [system.cpu1.itb] type=AlphaITB size=48 @@ -260,6 +256,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -279,6 +276,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -300,7 +298,7 @@ header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -310,16 +308,14 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -328,8 +324,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -346,16 +340,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -364,8 +356,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -405,19 +395,13 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -429,6 +413,13 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder @@ -459,10 +450,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu0 +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -472,30 +474,25 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu0 -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -864,16 +861,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -944,7 +947,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr new file mode 100755 index 000000000..e077a7fd9 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: 591544000: Trying to launch CPU number 1! +For more information see: http://www.m5sim.org/warn/8f7d2563 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout new file mode 100755 index 000000000..6b56db972 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:51 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1972135461000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 85a08a7e2..4a6754053 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,246 +1,228 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 647923 # Simulator instruction rate (inst/s) -host_mem_usage 252928 # Number of bytes of host memory used -host_seconds 97.63 # Real time elapsed on the host -host_tick_rate 20205445341 # Simulator tick rate (ticks/s) +host_inst_rate 1382701 # Simulator instruction rate (inst/s) +host_mem_usage 289788 # Number of bytes of host memory used +host_seconds 42.97 # Real time elapsed on the host +host_tick_rate 45890646030 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63257216 # Number of instructions simulated -sim_seconds 1.972680 # Number of seconds simulated -sim_ticks 1972679592000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192278 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 13965.504894 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10965.504894 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175522 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 234006000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.087145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16756 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 183738000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.087145 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16756 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 9119152 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 21251.410270 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18251.386941 # average ReadReq mshr miss latency +sim_insts 59420593 # Number of instructions simulated +sim_seconds 1.972135 # Number of seconds simulated +sim_ticks 1972135461000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 192630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14259.465279 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 175911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.086793 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16719 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 8488393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7426037 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 35981081500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.185666 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1693115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 30901697000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.185666 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1693115 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 857399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191314 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 26686.254525 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 23686.254525 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 162861 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 759304000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.148724 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28453 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 673945000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.148724 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28453 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5834436 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 26949.612638 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 23949.612638 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7449690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.122367 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1038703 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 191666 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 163357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.147700 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 28309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 5847430 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5455075 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 10223632000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.065021 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379361 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 9085549000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.065021 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379361 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1211657000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_hits 5468175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.064858 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 379255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.692591 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990826 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14953588 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 22294.450454 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12881112 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 46204713500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.138594 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2072476 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.098910 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1417958 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 39987246000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.138594 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 2072476 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14953588 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 22294.450454 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 19294.431395 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12881112 # number of overall hits -system.cpu0.dcache.overall_miss_latency 46204713500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.138594 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2072476 # number of overall misses +system.cpu0.dcache.overall_hits 12917865 # number of overall hits +system.cpu0.dcache.overall_miss_latency 47885794500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.098910 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1417958 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 39987246000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.138594 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 2072476 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2069056000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_miss_latency 43631879500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1992967 # number of replacements -system.cpu0.dcache.sampled_refs 1993479 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1338610 # number of replacements +system.cpu0.dcache.sampled_refs 1339122 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.888732 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13341539 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 66395000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403713 # number of writebacks -system.cpu0.dtb.accesses 719861 # DTB accesses +system.cpu0.dcache.tagsinuse 503.609177 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13378935 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 403520 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 15321442 # DTB hits -system.cpu0.dtb.misses 8487 # DTB misses -system.cpu0.dtb.read_accesses 524202 # DTB read accesses +system.cpu0.dtb.hits 14704826 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 9294921 # DTB read hits -system.cpu0.dtb.read_misses 7689 # DTB read misses +system.cpu0.dtb.read_hits 8664724 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6026521 # DTB write hits +system.cpu0.dtb.write_hits 6040102 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57943269 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14213.482115 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11212.730813 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 57028190 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13006459000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.015793 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 915079 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10260534500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.015793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 915079 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_accesses 54164416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 53248092 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.016917 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 916324 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 62.327526 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 58.118732 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57943269 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14213.482115 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency -system.cpu0.icache.demand_hits 57028190 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13006459000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015793 # miss rate for demand accesses -system.cpu0.icache.demand_misses 915079 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency +system.cpu0.icache.demand_hits 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.016917 # miss rate for demand accesses +system.cpu0.icache.demand_misses 916324 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10260534500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.015793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 915079 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 10703476000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57943269 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14213.482115 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11212.730813 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 54164416 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 57028190 # number of overall hits -system.cpu0.icache.overall_miss_latency 13006459000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015793 # miss rate for overall accesses -system.cpu0.icache.overall_misses 915079 # number of overall misses +system.cpu0.icache.overall_hits 53248092 # number of overall hits +system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.016917 # miss rate for overall accesses +system.cpu0.icache.overall_misses 916324 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10260534500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.015793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 915079 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 10703476000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 914464 # number of replacements -system.cpu0.icache.sampled_refs 914976 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 915684 # number of replacements +system.cpu0.icache.sampled_refs 916195 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 507.411447 # Cycle average of tags in use -system.cpu0.icache.total_refs 57028190 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 49269353000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 508.642782 # Cycle average of tags in use +system.cpu0.icache.total_refs 53248092 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.932800 # Percentage of idle cycles -system.cpu0.itb.accesses 3949472 # ITB accesses +system.cpu0.idle_fraction 0.933160 # Percentage of idle cycles +system.cpu0.itb.accesses 3953747 # ITB accesses system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3945631 # ITB hits +system.cpu0.itb.hits 3949906 # ITB hits system.cpu0.itb.misses 3841 # ITB misses -system.cpu0.kern.callpal 187580 # number of callpals executed +system.cpu0.kern.callpal 188012 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 94 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3867 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 171680 91.52% 93.66% # number of callpals executed -system.cpu0.kern.callpal_rdps 6661 3.55% 97.22% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.13% # number of callpals executed +system.cpu0.kern.callpal_swpipl 172068 91.52% 93.65% # number of callpals executed +system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rti 4704 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202457 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178500 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72488 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 202896 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178906 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72641 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 131 0.07% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1977 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 7 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 103897 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144346 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 71119 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 104141 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144662 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 71272 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1977 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 7 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 71112 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1972678821000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1900126420500 96.32% 96.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 86973000 0.00% 96.33% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 568583000 0.03% 96.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 5546500 0.00% 96.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 71891298000 3.64% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981114 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 71266 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1972134703000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1908230091000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 96186500 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 576952000 0.03% 96.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 63226031000 3.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981154 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684447 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1228 -system.cpu0.kern.mode_good_user 1229 +system.cpu0.kern.ipl_used_31 0.684322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1231 +system.cpu0.kern.mode_good_user 1232 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7227 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1229 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1232 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.169918 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170098 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1969223377000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3455442000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1968330503000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3804198000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3868 # number of times the context was actually changed +system.cpu0.kern.swap_context 3869 # number of times the context was actually changed system.cpu0.kern.syscall 224 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed @@ -272,239 +254,221 @@ system.cpu0.kern.syscall_98 2 0.89% 97.77% # nu system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.067200 # Percentage of non-idle cycles -system.cpu0.numCycles 3945359184 # number of cpu cycles simulated -system.cpu0.num_insts 57934492 # Number of instructions executed -system.cpu0.num_refs 15562811 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 12625 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 12190.944882 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9190.944882 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11609 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 12386000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.080475 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 9338000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.080475 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1030298 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 13948.255862 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10948.131577 # average ReadReq mshr miss latency +system.cpu0.not_idle_fraction 0.066840 # Percentage of non-idle cycles +system.cpu0.numCycles 3944270922 # number of cpu cycles simulated +system.cpu0.num_insts 54155641 # Number of instructions executed +system.cpu0.num_refs 14946215 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13303.501946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 11306 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.083347 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 1028 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 1020543 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 994091 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 505024500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035142 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 36207 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 396399000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035142 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 36207 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 13393500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12560 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 22874.692875 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 19874.692875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 10118 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 55860000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.194427 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2442 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 48534000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.194427 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2442 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 657926 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 26378.844865 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 23378.844865 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 984803 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035021 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 35740 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 12270 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 9848 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.197392 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2422 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 650008 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 631072 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 708377500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040816 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26854 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 627815500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040816 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26854 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 305665000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_hits 623656 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.040541 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26352 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.077708 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 30.141759 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1688224 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 19241.718336 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1625163 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 1213402000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037353 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 63061 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.037169 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 62092 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1024214500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037353 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 63061 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1688224 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 19241.718336 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 16241.646977 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1625163 # number of overall hits -system.cpu1.dcache.overall_miss_latency 1213402000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037353 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 63061 # number of overall misses +system.cpu1.dcache.overall_hits 1608459 # number of overall hits +system.cpu1.dcache.overall_miss_latency 2003684500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.037169 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 62092 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1024214500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037353 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 63061 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 319058500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_miss_latency 1817405000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 54390 # number of replacements -system.cpu1.dcache.sampled_refs 54808 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 53724 # number of replacements +system.cpu1.dcache.sampled_refs 54120 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 387.947804 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1648499 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1956976796000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 27227 # number of writebacks +system.cpu1.dcache.tagsinuse 388.878897 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1631272 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1954643578000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 26831 # number of writebacks system.cpu1.dtb.accesses 302878 # DTB accesses system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1712100 # DTB hits +system.cpu1.dtb.hits 1693851 # DTB hits system.cpu1.dtb.misses 3106 # DTB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1039743 # DTB read hits +system.cpu1.dtb.read_hits 1029710 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 672357 # DTB write hits +system.cpu1.dtb.write_hits 664141 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5325914 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14299.912084 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11299.461372 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5236056 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1284961500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016872 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 89858 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015347000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016872 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 89858 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 5268142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5180706 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1278070500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.016597 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 87436 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 58.288501 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 59.270387 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5325914 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14299.912084 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5236056 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1284961500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016872 # miss rate for demand accesses -system.cpu1.icache.demand_misses 89858 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1278070500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.016597 # miss rate for demand accesses +system.cpu1.icache.demand_misses 87436 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015347000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016872 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 89858 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 1015724000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 87436 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5325914 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14299.912084 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11299.461372 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 5268142 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5236056 # number of overall hits -system.cpu1.icache.overall_miss_latency 1284961500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016872 # miss rate for overall accesses -system.cpu1.icache.overall_misses 89858 # number of overall misses +system.cpu1.icache.overall_hits 5180706 # number of overall hits +system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.016597 # miss rate for overall accesses +system.cpu1.icache.overall_misses 87436 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015347000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016872 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 89858 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 1015724000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 89318 # number of replacements -system.cpu1.icache.sampled_refs 89830 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 86896 # number of replacements +system.cpu1.icache.sampled_refs 87408 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.412997 # Cycle average of tags in use -system.cpu1.icache.total_refs 5236056 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1957297672000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 419.405627 # Cycle average of tags in use +system.cpu1.icache.total_refs 5180706 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1967880295000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.995045 # Percentage of idle cycles -system.cpu1.itb.accesses 1398451 # ITB accesses +system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles +system.cpu1.itb.accesses 1397517 # ITB accesses system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1397205 # ITB hits +system.cpu1.itb.hits 1396271 # ITB hits system.cpu1.itb.misses 1246 # ITB misses -system.cpu1.kern.callpal 29654 # number of callpals executed +system.cpu1.kern.callpal 29503 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 7 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 369 1.24% 1.28% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.03% 1.31% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24277 81.87% 83.20% # number of callpals executed -system.cpu1.kern.callpal_rdps 2191 7.39% 90.59% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.01% 90.60% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 90.62% # number of callpals executed -system.cpu1.kern.callpal_rti 2588 8.73% 99.35% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24144 81.84% 83.16% # number of callpals executed +system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed +system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36198 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2401 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 28931 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9254 31.99% 31.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1971 6.81% 38.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 94 0.32% 39.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17612 60.88% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20463 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9246 45.18% 45.18% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1971 9.63% 54.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 94 0.46% 55.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9152 44.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1972666579000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1919200833000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 508731500 0.03% 97.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 56757500 0.00% 97.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 52900257000 2.68% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999136 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36053 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 28810 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9173 31.84% 31.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17566 60.97% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20310 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9165 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9074 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1927968787500 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 511194500 0.03% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 43145271000 2.19% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.519646 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 533 -system.cpu1.kern.mode_good_user 515 -system.cpu1.kern.mode_good_idle 18 -system.cpu1.kern.mode_switch_kernel 882 # number of protection mode switches -system.cpu1.kern.mode_switch_user 515 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2077 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.612975 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.604308 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.516566 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 532 +system.cpu1.kern.mode_good_user 516 +system.cpu1.kern.mode_good_idle 16 +system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches +system.cpu1.kern.mode_switch_user 516 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.008666 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3978131000 0.20% 0.20% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1616488000 0.08% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1966135435000 99.72% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 370 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 4596640000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1703543000 0.09% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1964670722000 99.68% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 366 # number of times the context was actually changed system.cpu1.kern.syscall 102 # number of syscalls executed system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed @@ -527,10 +491,10 @@ system.cpu1.kern.syscall_90 1 0.98% 95.10% # nu system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.004955 # Percentage of non-idle cycles -system.cpu1.numCycles 3945333218 # number of cpu cycles simulated -system.cpu1.num_insts 5322724 # Number of instructions executed -system.cpu1.num_refs 1722033 # Number of memory references +system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles +system.cpu1.numCycles 3943367734 # number of cpu cycles simulated +system.cpu1.num_insts 5264952 # Number of instructions executed +system.cpu1.num_refs 1703740 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -543,163 +507,145 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 113562.488636 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 61562.488636 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19986998 # number of ReadReq miss cycles +system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 176 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10834998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses 178 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 115053.879621 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 63053.711494 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4780718806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2620007820 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4173.944424 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6169.706090 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 2771 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 11566000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64528956 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41728 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 115047.589245 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency +system.iocache.demand_accesses 41730 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4800705804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41728 # number of demand (read+write) misses +system.iocache.demand_misses 41730 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2630842818 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41728 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 115047.589245 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 63047.421827 # average overall mshr miss latency +system.iocache.overall_accesses 41730 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4800705804 # number of overall miss cycles +system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41728 # number of overall misses +system.iocache.overall_misses 41730 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2630842818 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.iocache.replacements 41696 # number of replacements -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.replacements 41698 # number of replacements +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.554980 # Cycle average of tags in use +system.iocache.tagsinuse 0.582075 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1766170681000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 307159 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 23004.538366 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11004.538366 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 7066051000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 306814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52002.656333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 307159 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3380143000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 306814 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 307159 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2746067 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 23012.790348 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11012.812299 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2090305 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.275832 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782997 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 22162928000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.350709 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 963070 # number of ReadReq misses +system.l2c.ReadReq_hits 1782886 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.147069 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307419 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 10605988000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.350705 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 963059 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 779852500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127459 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 22445.817871 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11007.104245 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2860921500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.147064 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 127238 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 50741.170091 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6456205000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127459 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1402954500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 127238 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5090187000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 127459 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 127238 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1370781000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430940 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430940 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430351 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.813929 # Average number of references to valid blocks. +system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3053226 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 23010.794904 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency -system.l2c.demand_hits 1782997 # number of demand (read+write) hits -system.l2c.demand_miss_latency 29228979000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.416028 # miss rate for demand accesses -system.l2c.demand_misses 1270229 # number of demand (read+write) misses +system.l2c.demand_accesses 2397119 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency +system.l2c.demand_hits 1782886 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.256238 # miss rate for demand accesses +system.l2c.demand_misses 614233 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 13986131000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.416025 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1270218 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.256233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3053226 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 23010.794904 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency +system.l2c.overall_accesses 2397119 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782997 # number of overall hits -system.l2c.overall_miss_latency 29228979000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.416028 # miss rate for overall accesses -system.l2c.overall_misses 1270229 # number of overall misses +system.l2c.overall_hits 1782886 # number of overall hits +system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.256238 # miss rate for overall accesses +system.l2c.overall_misses 614233 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 13986131000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.416025 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1270218 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2150633500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.256233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1055829 # number of replacements -system.l2c.sampled_refs 1087019 # Sample count of references to valid blocks. +system.l2c.replacements 399005 # number of replacements +system.l2c.sampled_refs 430732 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30866.493853 # Cycle average of tags in use -system.l2c.total_refs 1971775 # Total number of references to valid blocks. -system.l2c.warmup_cycle 7281125000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123132 # number of writebacks +system.l2c.tagsinuse 30859.505450 # Cycle average of tags in use +system.l2c.total_refs 1961635 # Total number of references to valid blocks. +system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 123162 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr deleted file mode 100644 index b0bbb3d67..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ /dev/null @@ -1,6 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... -warn: 478619000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout deleted file mode 100644 index 84f4de778..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 27 2008 17:52:52 -M5 started Wed Feb 27 18:02:58 2008 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1972679592000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal new file mode 100644 index 000000000..7399f4d84 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -0,0 +1,113 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 +
Got Configuration 623 +
memsize 8000000 pages 4000 +
First free page after ROM 0xFFFFFC0000018000 +
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 +
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 +
CPU Clock at 2000 MHz IntrClockFrequency=1024 +
Booting with 2 processor(s) +
KSP: 0x20043FE8 PTBR 0x20 +
KSP: 0x20043FE8 PTBR 0x20 +
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 +
Memory cluster 0 [0 - 392] +
Memory cluster 1 [392 - 15992] +
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 +
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 +
Bootstraping CPU 1 with sp=0xFFFFFC0000076000 +
unix_boot_mem ends at FFFFFC0000078000 +
k_argc = 0 +
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) +
CallbackFixup 0 18000, t7=FFFFFC000070C000 +
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 +
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 +
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM +
Major Options: SMP LEGACY_START VERBOSE_MCHECK +
Command line: root=/dev/hda1 console=ttyS0 +
memcluster 0, usage 1, start 0, end 392 +
memcluster 1, usage 0, start 392, end 16384 +
freeing pages 1069:16384 +
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles +
SMP: 2 CPUs probed -- cpu_present_mask = 3 +
Built 1 zonelists +
Kernel command line: root=/dev/hda1 console=ttyS0 +
PID hash table entries: 1024 (order: 10, 32768 bytes) +
Using epoch = 1900 +
Console: colour dummy device 80x25 +
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) +
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) +
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) +
Mount-cache hash table entries: 512 +
SMP starting up secondaries. +
Slave CPU 1 console command START
+SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 +
Brought up 2 CPUs +
SMP: Total of 2 processors activated (8000.15 BogoMIPS). +
NET: Registered protocol family 16 +
EISA bus registered +
pci: enabling save/restore of SRM state +
SCSI subsystem initialized +
srm_env: version 0.0.5 loaded successfully +
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). +
Initializing Cryptographic API +
rtc: Standard PC (1900) epoch (1900) detected +
Real Time Clock Driver v1.12 +
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled +
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 +
io scheduler noop registered +
io scheduler anticipatory registered +
io scheduler deadline registered +
io scheduler cfq registered +
loop: loaded (max 8 devices) +
nbd: registered device at major 43 +
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64 +
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 +
eth0: enabling optical transceiver +
eth0: using 64 bit addressing. +
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg +
tun: Universal TUN/TAP device driver, 1.6 +
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> +
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 +
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx +
PIIX4: IDE controller at PCI slot 0000:00:00.0 +
PIIX4: chipset revision 0 +
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64 +
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA +
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA +
hda: M5 IDE Disk, ATA DISK drive +
hdb: M5 IDE Disk, ATA DISK drive +
ide0 at 0x8410-0x8417,0x8422 on irq 31 +
hda: max request size: 128KiB +
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) +
hda: cache flushes not supported +
hda: hda1 +
hdb: max request size: 128KiB +
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) +
hdb: cache flushes not supported +
hdb: unknown partition table +
mice: PS/2 mouse device common for all mice +
NET: Registered protocol family 2 +
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) +
TCP established hash table entries: 16384 (order: 5, 262144 bytes) +
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) +
TCP: Hash tables configured (established 16384 bind 16384) +
TCP reno registered +
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack +
ip_tables: (C) 2000-2002 Netfilter core team +
arp_tables: (C) 2002 David S. Miller +
TCP bic registered +
Initializing IPsec netlink socket +
NET: Registered protocol family 1 +
NET: Registered protocol family 17 +
NET: Registered protocol family 15 +
Bridge firewalling registered +
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> +
All bugs added by David S. Miller <davem@redhat.com> +
VFS: Mounted root (ext2 filesystem) readonly. +
Freeing unused kernel memory: 224k freed +
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended +
loading script...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 1b52231ed..468bf0248 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -5,7 +5,7 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -35,7 +35,8 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer +checker=Null clock=500 cpu_id=0 defer_registration=false @@ -45,11 +46,13 @@ do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 @@ -66,16 +69,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -84,8 +85,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -106,16 +105,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -124,8 +121,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -134,6 +129,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaITB size=48 @@ -152,6 +150,7 @@ image=system.disk0.image type=CowDiskImage children=child child=system.disk0.image.child +image_file= read_only=false table_size=65536 @@ -171,6 +170,7 @@ image=system.disk2.image type=CowDiskImage children=child child=system.disk2.image.child +image_file= read_only=false table_size=65536 @@ -192,7 +192,7 @@ header_cycles=1 responder_set=true width=64 default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma [system.iocache] type=BaseCache @@ -202,16 +202,14 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -220,8 +218,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -238,16 +234,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -256,8 +250,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -297,19 +289,13 @@ pio=system.membus.default [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] -[system.sim_console] -type=SimConsole -append_name=true -intr_control=system.intrctrl -number=0 -output=console -port=3456 - [system.simple_disk] type=SimpleDisk children=disk @@ -321,6 +307,13 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.toL2Bus] type=Bus children=responder @@ -351,10 +344,21 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system +[system.tsunami.backdoor] +type=AlphaBackdoor +cpu=system.cpu +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.port[25] + [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -364,30 +368,25 @@ system=system tsunami=system.tsunami pio=system.iobus.port[1] -[system.tsunami.console] -type=AlphaConsole -cpu=system.cpu -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -sim_console=system.sim_console -system=system -pio=system.iobus.port[25] - [system.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -756,16 +755,22 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -836,7 +841,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=system.tsunami -sim_console=system.sim_console system=system +terminal=system.terminal pio=system.iobus.port[24] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr new file mode 100755 index 000000000..83c71fc5c --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout new file mode 100755 index 000000000..ba86a45b9 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:52 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1930164593000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index fcddfbde2..cbf231e85 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,241 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 827411 # Simulator instruction rate (inst/s) -host_mem_usage 316168 # Number of bytes of host memory used -host_seconds 72.58 # Real time elapsed on the host -host_tick_rate 26612603617 # Simulator tick rate (ticks/s) +host_inst_rate 1953289 # Simulator instruction rate (inst/s) +host_mem_usage 288556 # Number of bytes of host memory used +host_seconds 28.78 # Real time elapsed on the host +host_tick_rate 67077404616 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60056349 # Number of instructions simulated -sim_seconds 1.931640 # Number of seconds simulated -sim_ticks 1931639667000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200273 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14106.217767 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11106.217767 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183016 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 243431000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17257 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 191660000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086167 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17257 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9530772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21143.101090 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18143.074712 # average ReadReq mshr miss latency +sim_insts 56205703 # Number of instructions simulated +sim_seconds 1.930165 # Number of seconds simulated +sim_ticks 1930164593000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7805869 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36469798500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.180983 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1724903 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31295044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.180983 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1724903 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 837553000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 27003.604806 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 24003.604806 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169292 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 809028000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150362 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29960 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 719148000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150362 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29960 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6154055 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27005.969289 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24005.969289 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5753421 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10819509500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 400634 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9617607500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400634 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1174669000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.859082 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15684827 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22248.169757 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13559290 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 47289308000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135515 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2125537 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1471029 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 40912651500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.135515 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2125537 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15684827 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22248.169757 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15048990 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13559290 # number of overall hits -system.cpu.dcache.overall_miss_latency 47289308000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135515 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2125537 # number of overall misses +system.cpu.dcache.overall_hits 13577961 # number of overall hits +system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1471029 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 40912651500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.135515 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2125537 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2012222000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2046082 # number of replacements -system.cpu.dcache.sampled_refs 2046594 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1391606 # number of replacements +system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.986722 # Cycle average of tags in use -system.cpu.dcache.total_refs 14037756 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 66420000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430195 # number of writebacks -system.cpu.dtb.accesses 1020787 # DTB accesses +system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use +system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430459 # number of writebacks +system.cpu.dtb.accesses 1020784 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16064922 # DTB hits -system.cpu.dtb.misses 11471 # DTB misses -system.cpu.dtb.read_accesses 728856 # DTB read accesses +system.cpu.dtb.hits 15429793 # DTB hits +system.cpu.dtb.misses 11466 # DTB misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9711464 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.read_hits 9069700 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6353458 # DTB write hits +system.cpu.dtb.write_hits 6360093 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60068188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14221.050037 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11220.318707 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 59139059 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13213190000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.015468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 929129 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10425123500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.015468 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 929129 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 56217537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 55286436 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.016562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 931101 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 63.660961 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60068188 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14221.050037 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency -system.cpu.icache.demand_hits 59139059 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13213190000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015468 # miss rate for demand accesses -system.cpu.icache.demand_misses 929129 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency +system.cpu.icache.demand_hits 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_misses 931101 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10425123500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.015468 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 929129 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60068188 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14221.050037 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency +system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59139059 # number of overall hits -system.cpu.icache.overall_miss_latency 13213190000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015468 # miss rate for overall accesses -system.cpu.icache.overall_misses 929129 # number of overall misses +system.cpu.icache.overall_hits 55286436 # number of overall hits +system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_misses 931101 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10425123500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.015468 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 929129 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 928458 # number of replacements -system.cpu.icache.sampled_refs 928969 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930429 # number of replacements +system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 507.298573 # Cycle average of tags in use -system.cpu.icache.total_refs 59139059 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 48981308000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use +system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929252 # Percentage of idle cycles -system.cpu.itb.accesses 4979997 # ITB accesses +system.cpu.idle_fraction 0.929209 # Percentage of idle cycles +system.cpu.itb.accesses 4982987 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974991 # ITB hits -system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192947 # number of callpals executed +system.cpu.itb.hits 4977977 # ITB hits +system.cpu.itb.misses 5010 # ITB misses +system.cpu.kern.callpal 193221 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175999 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal_rdps 6835 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed +system.cpu.kern.callpal_swpipl 176257 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5159 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212042 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183224 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74910 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1934 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106249 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149151 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73543 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73543 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1931638909000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1859511291500 96.27% 96.27% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 87343500 0.00% 96.27% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 557262000 0.03% 96.30% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 71483012000 3.70% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981751 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183502 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75001 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106426 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149343 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1930163835000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 96331500 0.00% 96.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 565310500 0.03% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981774 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.692176 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1905 -system.cpu.kern.mode_good_user 1736 -system.cpu.kern.mode_good_idle 169 -system.cpu.kern.mode_switch_kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch_user 1736 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2093 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.403299 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322553 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.691880 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1911 +system.cpu.kern.mode_good_user 1744 +system.cpu.kern.mode_good_idle 167 +system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches +system.cpu.kern.mode_switch_user 1744 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.402910 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.322968 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 45112475000 2.34% 2.34% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5048233000 0.26% 2.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1881478199000 97.40% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 5539986000 0.29% 2.80% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4172 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -267,10 +249,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.070748 # Percentage of non-idle cycles -system.cpu.numCycles 3863279334 # number of cpu cycles simulated -system.cpu.num_insts 60056349 # Number of instructions executed -system.cpu.num_refs 16313052 # Number of memory references +system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles +system.cpu.numCycles 3860329186 # number of cpu cycles simulated +system.cpu.num_insts 56205703 # Number of instructions executed +system.cpu.num_refs 15677891 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -284,161 +266,143 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 113566.462428 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 61566.462428 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19646998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10650998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 115104.611234 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 63104.539180 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4782826806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2622119812 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4196.454414 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6163.674943 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 2764 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 11599000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64546004 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 115098.233769 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4802473804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2632770810 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 115098.233769 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4802473804 # number of overall miss cycles +system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2632770810 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.333347 # Cycle average of tags in use +system.iocache.tagsinuse 1.353399 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1766149259000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304436 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 23005.373872 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11005.373872 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 7003664000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 304636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304436 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3350432000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304436 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2671270 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 23012.722595 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11012.722595 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1708534 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 22155176500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.360404 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962736 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 10602344500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.360404 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 962736 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126158 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 23005.275131 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11006.915931 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2902299500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 1710971 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307593 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126158 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1388610500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126158 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1061281000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430195 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430195 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430459 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.743066 # Average number of references to valid blocks. +system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2975706 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 23010.957076 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency -system.l2c.demand_hits 1708534 # number of demand (read+write) hits -system.l2c.demand_miss_latency 29158840500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.425839 # miss rate for demand accesses -system.l2c.demand_misses 1267172 # number of demand (read+write) misses +system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency +system.l2c.demand_hits 1710971 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses +system.l2c.demand_misses 612229 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 13952776500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.425839 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1267172 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2975706 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 23010.957076 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency +system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1708534 # number of overall hits -system.l2c.overall_miss_latency 29158840500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.425839 # miss rate for overall accesses -system.l2c.overall_misses 1267172 # number of overall misses +system.l2c.overall_hits 1710971 # number of overall hits +system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses +system.l2c.overall_misses 612229 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 13952776500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.425839 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1267172 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1811383000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050085 # number of replacements -system.l2c.sampled_refs 1081030 # Sample count of references to valid blocks. +system.l2c.replacements 394928 # number of replacements +system.l2c.sampled_refs 425903 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30869.828292 # Cycle average of tags in use -system.l2c.total_refs 1884307 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5029142000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 118653 # number of writebacks +system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use +system.l2c.total_refs 1889545 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119060 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr deleted file mode 100644 index 408213e67..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb on port 7004 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout deleted file mode 100644 index fee547a1f..000000000 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:18:14 -M5 started Sun Feb 24 13:19:10 2008 -M5 executing on tater -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1931639667000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal new file mode 100644 index 000000000..ff644ed3f --- /dev/null +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -0,0 +1,108 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 +
Got Configuration 623 +
memsize 8000000 pages 4000 +
First free page after ROM 0xFFFFFC0000018000 +
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 +
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 +
CPU Clock at 2000 MHz IntrClockFrequency=1024 +
Booting with 1 processor(s) +
KSP: 0x20043FE8 PTBR 0x20 +
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 +
Memory cluster 0 [0 - 392] +
Memory cluster 1 [392 - 15992] +
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 +
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 +
unix_boot_mem ends at FFFFFC0000076000 +
k_argc = 0 +
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) +
CallbackFixup 0 18000, t7=FFFFFC000070C000 +
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 +
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM +
Major Options: SMP LEGACY_START VERBOSE_MCHECK +
Command line: root=/dev/hda1 console=ttyS0 +
memcluster 0, usage 1, start 0, end 392 +
memcluster 1, usage 0, start 392, end 16384 +
freeing pages 1069:16384 +
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles +
SMP: 1 CPUs probed -- cpu_present_mask = 1 +
Built 1 zonelists +
Kernel command line: root=/dev/hda1 console=ttyS0 +
PID hash table entries: 1024 (order: 10, 32768 bytes) +
Using epoch = 1900 +
Console: colour dummy device 80x25 +
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) +
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) +
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) +
Mount-cache hash table entries: 512 +
SMP mode deactivated. +
Brought up 1 CPUs +
SMP: Total of 1 processors activated (4002.20 BogoMIPS). +
NET: Registered protocol family 16 +
EISA bus registered +
pci: enabling save/restore of SRM state +
SCSI subsystem initialized +
srm_env: version 0.0.5 loaded successfully +
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). +
Initializing Cryptographic API +
rtc: Standard PC (1900) epoch (1900) detected +
Real Time Clock Driver v1.12 +
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled +
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 +
io scheduler noop registered +
io scheduler anticipatory registered +
io scheduler deadline registered +
io scheduler cfq registered +
loop: loaded (max 8 devices) +
nbd: registered device at major 43 +
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64 +
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 +
eth0: enabling optical transceiver +
eth0: using 64 bit addressing. +
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg +
tun: Universal TUN/TAP device driver, 1.6 +
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> +
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 +
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx +
PIIX4: IDE controller at PCI slot 0000:00:00.0 +
PIIX4: chipset revision 0 +
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64 +
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA +
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA +
hda: M5 IDE Disk, ATA DISK drive +
hdb: M5 IDE Disk, ATA DISK drive +
ide0 at 0x8410-0x8417,0x8422 on irq 31 +
hda: max request size: 128KiB +
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) +
hda: cache flushes not supported +
hda: hda1 +
hdb: max request size: 128KiB +
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) +
hdb: cache flushes not supported +
hdb: unknown partition table +
mice: PS/2 mouse device common for all mice +
NET: Registered protocol family 2 +
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) +
TCP established hash table entries: 16384 (order: 5, 262144 bytes) +
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) +
TCP: Hash tables configured (established 16384 bind 16384) +
TCP reno registered +
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack +
ip_tables: (C) 2000-2002 Netfilter core team +
arp_tables: (C) 2002 David S. Miller +
TCP bic registered +
Initializing IPsec netlink socket +
NET: Registered protocol family 1 +
NET: Registered protocol family 17 +
NET: Registered protocol family 15 +
Bridge firewalling registered +
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> +
All bugs added by David S. Miller <davem@redhat.com> +
VFS: Mounted root (ext2 filesystem) readonly. +
Freeing unused kernel memory: 224k freed +
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended +
loading script...
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr index 7ded22db8..7ded22db8 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simout index ee0eb672e..ee0eb672e 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/simout diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt index 119cc8e9d..119cc8e9d 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 9db92d8dc..014feb13e 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -47,7 +52,10 @@ type=ExeTracer [system.cpu.workload] type=EioProcess chkpt= +errout=cerr file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 output=cout system=system @@ -56,6 +64,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -63,7 +72,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr new file mode 100755 index 000000000..c0312fe31 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here + +gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout new file mode 100755 index 000000000..103b40a61 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +49508 bytes wasted +>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index 064beb313..1e8dfa007 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1676309 # Simulator instruction rate (inst/s) -host_mem_usage 188356 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 837474668 # Simulator tick rate (ticks/s) +host_inst_rate 4171159 # Simulator instruction rate (inst/s) +host_mem_usage 191588 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 2080999983 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr deleted file mode 100644 index 4e444fa6b..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... - -gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout deleted file mode 100644 index fee99ba99..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ /dev/null @@ -1,15 +0,0 @@ -main dictionary has 1245 entries -49508 bytes wasted ->M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Aug 14 2007 17:58:14 -M5 started Tue Aug 14 17:58:32 2007 -M5 executing on nacho -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 766b954c1..84839b10d 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -163,6 +155,7 @@ type=ExeTracer [system.cpu.workload] type=EioProcess chkpt= +errout=cerr file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 @@ -182,7 +175,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr new file mode 100755 index 000000000..c0312fe31 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here + +gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout new file mode 100755 index 000000000..d93e92292 --- /dev/null +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +49508 bytes wasted +>Exiting @ tick 737389000 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index f4cb30fc4..66e101984 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 922979 # Simulator instruction rate (inst/s) -host_mem_usage 193036 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host -host_tick_rate 1305530646 # Simulator tick rate (ticks/s) +host_inst_rate 1619389 # Simulator instruction rate (inst/s) +host_mem_usage 199040 # Number of bytes of host memory used +host_seconds 0.31 # Real time elapsed on the host +host_tick_rate 2386410783 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000708 # Number of seconds simulated -sim_ticks 707548000 # Number of ticks simulated +sim_seconds 0.000737 # Number of seconds simulated +sim_ticks 737389000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 8505000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 7560000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7464000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,46 +37,37 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16902000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 15024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180149 # number of overall hits -system.cpu.dcache.overall_miss_latency 16902000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses system.cpu.dcache.overall_misses 626 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 15024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 289.353429 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 56340 # DTB write hits system.cpu.dtb.write_misses 10 # DTB write misses system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10881000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 9672000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10881000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9672000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499617 # number of overall hits -system.cpu.icache.overall_miss_latency 10881000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9672000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 266.476324 # Cycle average of tags in use +system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,30 +142,30 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 500020 # ITB hits system.cpu.itb.misses 13 # ITB misses system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3197000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1529000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 16514000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7898000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3956000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1892000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -195,51 +177,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19711000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19711000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 373.323140 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1415096 # number of cpu cycles simulated +system.cpu.numCycles 1474778 # number of cpu cycles simulated system.cpu.num_insts 500001 # Number of instructions executed system.cpu.num_refs 182222 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr deleted file mode 100644 index 9e24842c0..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr +++ /dev/null @@ -1,4 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 -warn: Entering event queue @ 0. Starting simulation... - -gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout deleted file mode 100644 index 870de60ce..000000000 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ /dev/null @@ -1,15 +0,0 @@ -main dictionary has 1245 entries -49508 bytes wasted ->M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 12:58:24 2008 -M5 executing on tater -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 707548000 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini new file mode 100644 index 000000000..af926f81c --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -0,0 +1,529 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +mem_mode=atomic +physmem=system.physmem + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu0.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu1] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu1.tracer +width=1 +workload=system.cpu1.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu1.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu2] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu2.tracer +width=1 +workload=system.cpu2.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.port[6] + +[system.cpu2.dtb] +type=AlphaDTB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.port[5] + +[system.cpu2.itb] +type=AlphaITB +size=48 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu2.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu3] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu3.tracer +width=1 +workload=system.cpu3.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.port[8] + +[system.cpu3.dtb] +type=AlphaDTB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.port[7] + +[system.cpu3.itb] +type=AlphaITB +size=48 + +[system.cpu3.tracer] +type=ExeTracer + +[system.cpu3.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.mem_side system.physmem.port[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:1073741823 +zero=false +port=system.membus.port[1] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr new file mode 100755 index 000000000..75c83d350 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -0,0 +1,11 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout new file mode 100755 index 000000000..0c841053d --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -0,0 +1,23 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:11 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt new file mode 100644 index 000000000..aecd60ac7 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -0,0 +1,547 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 4658528 # Simulator instruction rate (inst/s) +host_mem_usage 1123612 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host +host_tick_rate 582033733 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2000004 # Number of instructions simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 250015500 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180140 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180793 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180775 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124443 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124435 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56350 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56340 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499556 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500032 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500019 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 500032 # number of cpu cycles simulated +system.cpu0.num_insts 500001 # Number of instructions executed +system.cpu0.num_refs 182222 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180140 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180793 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180775 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124443 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124435 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56350 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56340 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499556 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500032 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 500019 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 500032 # number of cpu cycles simulated +system.cpu1.num_insts 500001 # Number of instructions executed +system.cpu1.num_refs 182222 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499556 # number of overall hits +system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500032 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500019 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 500032 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180140 # number of overall hits +system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180793 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180775 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124443 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124435 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56350 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56340 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499556 # number of overall hits +system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500032 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500019 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 500032 # number of cpu cycles simulated +system.cpu3.num_insts 500001 # Number of instructions executed +system.cpu3.num_refs 182222 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini new file mode 100644 index 000000000..2d269877c --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -0,0 +1,517 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +mem_mode=timing +physmem=system.physmem + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu1] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu1.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu1.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu2] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu2.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.port[6] + +[system.cpu2.dtb] +type=AlphaDTB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.port[5] + +[system.cpu2.itb] +type=AlphaITB +size=48 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu2.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu3] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu3.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.port[8] + +[system.cpu3.dtb] +type=AlphaDTB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.port[7] + +[system.cpu3.itb] +type=AlphaITB +size=48 + +[system.cpu3.tracer] +type=ExeTracer + +[system.cpu3.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.mem_side system.physmem.port[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr new file mode 100755 index 000000000..75c83d350 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -0,0 +1,11 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout new file mode 100755 index 000000000..edab14950 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -0,0 +1,23 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 738387000 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt new file mode 100644 index 000000000..1fb750134 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -0,0 +1,637 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1521087 # Simulator instruction rate (inst/s) +host_mem_usage 206108 # Number of bytes of host memory used +host_seconds 1.32 # Real time elapsed on the host +host_tick_rate 561475161 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1999941 # Number of instructions simulated +sim_seconds 0.000738 # Number of seconds simulated +sim_ticks 738387000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180136 # number of overall hits +system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180789 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180771 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124440 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124432 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56349 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56339 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499537 # number of overall hits +system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use +system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500013 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500000 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 1476774 # number of cpu cycles simulated +system.cpu0.num_insts 499981 # Number of instructions executed +system.cpu0.num_refs 182218 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180133 # number of overall hits +system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180786 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180768 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124437 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124429 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56349 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56339 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499531 # number of overall hits +system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use +system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500007 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 499994 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 1476774 # number of cpu cycles simulated +system.cpu1.num_insts 499975 # Number of instructions executed +system.cpu1.num_refs 182214 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499557 # number of overall hits +system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use +system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500033 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500020 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 1476774 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180137 # number of overall hits +system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180790 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180772 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124441 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124433 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56349 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56339 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499540 # number of overall hits +system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use +system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500016 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500003 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 1476774 # number of cpu cycles simulated +system.cpu3.num_insts 499984 # Number of instructions executed +system.cpu3.num_refs 182219 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 178284000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/test.py b/tests/quick/30.eio-mp/test.py new file mode 100644 index 000000000..3dbb7614a --- /dev/null +++ b/tests/quick/30.eio-mp/test.py @@ -0,0 +1,33 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) + +for i in xrange(nb_cores): + root.system.cpu[i].workload = process() + root.system.cpu[i].max_insts_any_thread = 500000 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index e04a78cce..f9dfac7de 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -33,16 +33,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -51,8 +49,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -85,16 +81,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -103,8 +97,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -137,16 +129,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -155,8 +145,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -189,16 +177,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -207,8 +193,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -241,16 +225,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -259,8 +241,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -293,16 +273,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -311,8 +289,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -345,16 +321,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -363,8 +337,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -397,16 +369,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=12 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -415,8 +385,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -428,7 +396,9 @@ mem_side=system.toL2Bus.port[8] [system.funcmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional @@ -441,16 +411,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -459,8 +427,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=65536 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 @@ -482,7 +448,9 @@ port=system.l2c.mem_side system.physmem.port[0] [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[1] diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr new file mode 100755 index 000000000..b09f497b8 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr @@ -0,0 +1,74 @@ +system.cpu3: completed 10000 read accesses @26226880 +system.cpu6: completed 10000 read accesses @26416342 +system.cpu2: completed 10000 read accesses @26427251 +system.cpu5: completed 10000 read accesses @26798889 +system.cpu0: completed 10000 read accesses @26886521 +system.cpu7: completed 10000 read accesses @27109446 +system.cpu1: completed 10000 read accesses @27197408 +system.cpu4: completed 10000 read accesses @27318359 +system.cpu3: completed 20000 read accesses @53279230 +system.cpu6: completed 20000 read accesses @53417084 +system.cpu2: completed 20000 read accesses @53757092 +system.cpu0: completed 20000 read accesses @53888320 +system.cpu5: completed 20000 read accesses @53947132 +system.cpu4: completed 20000 read accesses @54390092 +system.cpu1: completed 20000 read accesses @54397720 +system.cpu7: completed 20000 read accesses @54632966 +system.cpu6: completed 30000 read accesses @80144176 +system.cpu3: completed 30000 read accesses @80518264 +system.cpu0: completed 30000 read accesses @80638600 +system.cpu5: completed 30000 read accesses @80869702 +system.cpu1: completed 30000 read accesses @81289158 +system.cpu2: completed 30000 read accesses @81358716 +system.cpu7: completed 30000 read accesses @81981296 +system.cpu4: completed 30000 read accesses @82043104 +system.cpu6: completed 40000 read accesses @107087547 +system.cpu0: completed 40000 read accesses @107662142 +system.cpu3: completed 40000 read accesses @107722516 +system.cpu5: completed 40000 read accesses @107884124 +system.cpu1: completed 40000 read accesses @107981413 +system.cpu7: completed 40000 read accesses @108415286 +system.cpu2: completed 40000 read accesses @108655120 +system.cpu4: completed 40000 read accesses @109427858 +system.cpu6: completed 50000 read accesses @133583246 +system.cpu0: completed 50000 read accesses @133832383 +system.cpu5: completed 50000 read accesses @134755386 +system.cpu1: completed 50000 read accesses @134792594 +system.cpu7: completed 50000 read accesses @134914312 +system.cpu3: completed 50000 read accesses @134993978 +system.cpu2: completed 50000 read accesses @135362549 +system.cpu4: completed 50000 read accesses @135394370 +system.cpu0: completed 60000 read accesses @160410176 +system.cpu6: completed 60000 read accesses @160667590 +system.cpu7: completed 60000 read accesses @161466346 +system.cpu1: completed 60000 read accesses @161592434 +system.cpu5: completed 60000 read accesses @161656374 +system.cpu4: completed 60000 read accesses @161882626 +system.cpu2: completed 60000 read accesses @162062631 +system.cpu3: completed 60000 read accesses @162154299 +system.cpu6: completed 70000 read accesses @187592265 +system.cpu1: completed 70000 read accesses @188138542 +system.cpu7: completed 70000 read accesses @188373105 +system.cpu0: completed 70000 read accesses @188690782 +system.cpu3: completed 70000 read accesses @189309687 +system.cpu2: completed 70000 read accesses @189360790 +system.cpu4: completed 70000 read accesses @189391126 +system.cpu5: completed 70000 read accesses @189902895 +system.cpu6: completed 80000 read accesses @214739574 +system.cpu1: completed 80000 read accesses @215665444 +system.cpu0: completed 80000 read accesses @216021457 +system.cpu7: completed 80000 read accesses @216394344 +system.cpu3: completed 80000 read accesses @216537382 +system.cpu4: completed 80000 read accesses @216775798 +system.cpu2: completed 80000 read accesses @216868662 +system.cpu5: completed 80000 read accesses @217401619 +system.cpu6: completed 90000 read accesses @241415090 +system.cpu1: completed 90000 read accesses @242558992 +system.cpu0: completed 90000 read accesses @242897388 +system.cpu7: completed 90000 read accesses @243372191 +system.cpu3: completed 90000 read accesses @243630762 +system.cpu5: completed 90000 read accesses @243633950 +system.cpu4: completed 90000 read accesses @243710816 +system.cpu2: completed 90000 read accesses @243974160 +system.cpu6: completed 100000 read accesses @268915439 +hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout new file mode 100755 index 000000000..9d66255a0 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:22:11 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py quick/50.memtest/alpha/linux/memtest +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index f7b90230a..7f0400045 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,731 +1,650 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 323140 # Number of bytes of host memory used -host_seconds 197.60 # Real time elapsed on the host -host_tick_rate 574221 # Simulator tick rate (ticks/s) +host_mem_usage 326140 # Number of bytes of host memory used +host_seconds 207.97 # Real time elapsed on the host +host_tick_rate 1293031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000113 # Number of seconds simulated -sim_ticks 113467820 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 16813.519915 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 15809.702810 # average ReadReq mshr miss latency +sim_seconds 0.000269 # Number of seconds simulated +sim_ticks 268915439 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7364 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 627699139 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.835246 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37333 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 590223635 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835246 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37333 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 316695188 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24294 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 20338.524830 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 19334.650285 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 955 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 474680831 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.960690 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23339 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 451251403 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.960690 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23339 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 201005657 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1600.079607 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.402132 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 70069 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 112115978 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 68991 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 18169.501088 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 17165.661887 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8319 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 1102379970 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.879419 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60672 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 1041475038 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.879419 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60672 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 68991 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 18169.501088 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 17165.661887 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8319 # number of overall hits -system.cpu0.l1c.overall_miss_latency 1102379970 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.879419 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60672 # number of overall misses +system.cpu0.l1c.overall_hits 8674 # number of overall hits +system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60767 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 1041475038 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.879419 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60672 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 517700845 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l1c.replacements 27892 # number of replacements -system.cpu0.l1c.sampled_refs 28232 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 28158 # number of replacements +system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 346.353469 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11353 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 11056 # number of writebacks +system.cpu0.l1c.writebacks 11054 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99413 # number of read accesses completed -system.cpu0.num_writes 54273 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44637 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 16885.597031 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 15881.726361 # average ReadReq mshr miss latency +system.cpu0.num_reads 99578 # number of read accesses completed +system.cpu0.num_writes 53795 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7453 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 627874040 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.833031 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37184 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 590546113 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833031 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37184 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 318748024 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24256 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 20197.502675 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 19193.799580 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 895 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 471833860 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.963102 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23361 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 448386352 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.963102 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23361 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 199243328 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1599.721775 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.408930 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 69990 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 111964527 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68893 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 18163.480056 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 17159.674044 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8348 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 1099707900 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.878827 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60545 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 1038932465 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.878827 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60545 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 68893 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 18163.480056 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 17159.674044 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8348 # number of overall hits -system.cpu1.l1c.overall_miss_latency 1099707900 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.878827 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60545 # number of overall misses +system.cpu1.l1c.overall_hits 8551 # number of overall hits +system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60450 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 1038932465 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.878827 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60545 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 517991352 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l1c.replacements 27678 # number of replacements -system.cpu1.l1c.sampled_refs 28017 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27563 # number of replacements +system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 343.577416 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11457 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10919 # number of writebacks +system.cpu1.l1c.writebacks 10923 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99570 # number of read accesses completed -system.cpu1.num_writes 53662 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44913 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 16880.348216 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 15876.450165 # average ReadReq mshr miss latency +system.cpu1.num_reads 99680 # number of read accesses completed +system.cpu1.num_writes 54175 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7600 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 629856433 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.830784 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37313 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 592397985 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.830784 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37313 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 314233420 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24350 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 20273.649648 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 19269.817033 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 925 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 474910243 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.962012 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23425 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 451395464 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.962012 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23425 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 201676231 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1601.319797 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.408037 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 70035 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 112148432 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 69263 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 18189.052587 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 17185.179772 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8525 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 1104766676 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.876918 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60738 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 1043793449 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.876918 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60738 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 69263 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 18189.052587 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 17185.179772 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8525 # number of overall hits -system.cpu2.l1c.overall_miss_latency 1104766676 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.876918 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60738 # number of overall misses +system.cpu2.l1c.overall_hits 8437 # number of overall hits +system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60562 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 1043793449 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.876918 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60738 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 515909651 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.l1c.replacements 27950 # number of replacements -system.cpu2.l1c.sampled_refs 28294 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27725 # number of replacements +system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 344.355959 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11545 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10956 # number of writebacks +system.cpu2.l1c.writebacks 10868 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99987 # number of read accesses completed -system.cpu2.num_writes 53946 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44879 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 16871.980218 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 15868.081622 # average ReadReq mshr miss latency +system.cpu2.num_reads 99153 # number of read accesses completed +system.cpu2.num_writes 52976 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7573 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 629426094 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.831257 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37306 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 591974653 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.831257 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37306 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 315451568 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24230 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 20326.119616 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 19322.374206 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 922 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 473761196 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.961948 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23308 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 450365898 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961948 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23308 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 202979355 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1601.528078 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.416658 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69967 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 112054115 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69109 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 18200.206058 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 17196.366368 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8495 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 1103187290 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.877078 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60614 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 1042340551 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.877078 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60614 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 69109 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 18200.206058 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 17196.366368 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8495 # number of overall hits -system.cpu3.l1c.overall_miss_latency 1103187290 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.877078 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60614 # number of overall misses +system.cpu3.l1c.overall_hits 8535 # number of overall hits +system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60533 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 1042340551 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.877078 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60614 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 518430923 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.l1c.replacements 27588 # number of replacements +system.cpu3.l1c.replacements 27562 # number of replacements system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 346.019907 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11631 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10783 # number of writebacks +system.cpu3.l1c.writebacks 10850 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99559 # number of read accesses completed -system.cpu3.num_writes 53870 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44804 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 16848.729876 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 15844.831650 # average ReadReq mshr miss latency +system.cpu3.num_reads 99282 # number of read accesses completed +system.cpu3.num_writes 53764 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7584 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 627109726 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.830729 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37220 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 589744634 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.830729 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37220 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 313232793 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24193 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 20495.832426 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 19492.129507 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 866 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 478106283 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.964205 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23327 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 454692905 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.964205 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23327 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 192427965 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1603.347065 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.413043 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 69889 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 112056323 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68997 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 18253.852528 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 17250.029547 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8450 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 1105216009 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.877531 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60547 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 1044437539 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.877531 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60547 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68997 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 18253.852528 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 17250.029547 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8450 # number of overall hits -system.cpu4.l1c.overall_miss_latency 1105216009 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.877531 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60547 # number of overall misses +system.cpu4.l1c.overall_hits 8435 # number of overall hits +system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60418 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 1044437539 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.877531 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60547 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 505660758 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu4.l1c.replacements 27638 # number of replacements -system.cpu4.l1c.sampled_refs 27985 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27721 # number of replacements +system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 346.668579 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11559 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10780 # number of writebacks +system.cpu4.l1c.writebacks 10846 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99517 # number of read accesses completed -system.cpu4.num_writes 53554 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 45330 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 16742.272952 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 15738.453990 # average ReadReq mshr miss latency +system.cpu4.num_reads 99301 # number of read accesses completed +system.cpu4.num_writes 53586 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7653 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 630798618 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.831171 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37677 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 592977731 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831171 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37677 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 317163872 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24208 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 20252.552363 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 19248.677491 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 928 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 471479419 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.961666 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23280 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 448109212 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961666 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23280 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 202581548 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1592.994331 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.413221 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 70383 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 112119720 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 69538 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 18082.878701 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 17079.038388 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8581 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 1102278037 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.876600 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60957 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 1041086943 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.876600 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60957 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 69538 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 18082.878701 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 17079.038388 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8581 # number of overall hits -system.cpu5.l1c.overall_miss_latency 1102278037 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.876600 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60957 # number of overall misses +system.cpu5.l1c.overall_hits 8362 # number of overall hits +system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60470 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 1041086943 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.876600 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60957 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 519745420 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu5.l1c.replacements 28012 # number of replacements -system.cpu5.l1c.sampled_refs 28365 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 27632 # number of replacements +system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 347.429877 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11721 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10901 # number of writebacks +system.cpu5.l1c.writebacks 10950 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 53842 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 45124 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 16852.177623 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 15848.333619 # average ReadReq mshr miss latency +system.cpu5.num_reads 99024 # number of read accesses completed +system.cpu5.num_writes 53903 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7719 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 630355704 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.828938 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37405 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 592806919 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.828938 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 313955648 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24360 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 20279.291722 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 19275.372628 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 913 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 475488553 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.962521 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23447 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 451949662 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962521 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23447 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 198611435 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1598.405866 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.418615 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 70240 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 112272028 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 69484 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 18172.685483 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 17168.812545 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8632 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 1105844257 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.875770 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60852 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 1044756581 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.875770 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60852 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 69484 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 18172.685483 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 17168.812545 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8632 # number of overall hits -system.cpu6.l1c.overall_miss_latency 1105844257 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.875770 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60852 # number of overall misses +system.cpu6.l1c.overall_hits 8396 # number of overall hits +system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60973 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 1044756581 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.875770 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60852 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 512567083 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu6.l1c.replacements 27959 # number of replacements -system.cpu6.l1c.sampled_refs 28310 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 28139 # number of replacements +system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 344.892132 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11851 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 11044 # number of writebacks +system.cpu6.l1c.writebacks 11130 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99626 # number of read accesses completed -system.cpu6.num_writes 53905 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44909 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 16826.619219 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 15822.802503 # average ReadReq mshr miss latency +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 54239 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7759 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 625108904 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.827228 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37150 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 587817113 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.827228 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37150 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 317908383 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24427 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 20228.908213 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 19225.075071 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 916 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 475601861 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.962501 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23511 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 452000740 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.962501 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23511 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 197920310 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1598.930420 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.421584 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 70034 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 111979493 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 69336 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 18145.278927 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 17141.455845 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8675 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 1100710765 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.874885 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60661 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 1039817853 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.874885 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60661 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 69336 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 18145.278927 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 17141.455845 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8675 # number of overall hits -system.cpu7.l1c.overall_miss_latency 1100710765 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.874885 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60661 # number of overall misses +system.cpu7.l1c.overall_hits 8481 # number of overall hits +system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60440 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 1039817853 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.874885 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60661 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 515828693 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu7.l1c.replacements 27690 # number of replacements -system.cpu7.l1c.sampled_refs 28049 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 27627 # number of replacements +system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 343.299146 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11825 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10985 # number of writebacks +system.cpu7.l1c.writebacks 10984 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99331 # number of read accesses completed -system.cpu7.num_writes 53962 # number of write accesses completed -system.l2c.ReadExReq_accesses 75034 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 19990.930951 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 10006.831093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 1499999513 # number of ReadExReq miss cycles +system.cpu7.num_reads 99634 # number of read accesses completed +system.cpu7.num_writes 53744 # number of write accesses completed +system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 75034 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 354 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 747310146 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.995282 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74680 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 139261 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 19959.179983 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 10007.689712 # average ReadReq mshr miss latency +system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 91062 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 962012516 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.346106 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 48199 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 611 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 476245938 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.341718 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 47588 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 793404880 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18516 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 11019.424390 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 10007.005085 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 204035662 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 89906 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 48016 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18516 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 30 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 184989496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 0.998380 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18486 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 430707040 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 86799 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 86799 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs 2909.833333 # average number of cycles each access was blocked +system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 86929 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.988478 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 6 # number of cycles access was blocked +system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 17459 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 214295 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 19978.512484 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency -system.l2c.demand_hits 91062 # number of demand (read+write) hits -system.l2c.demand_miss_latency 2462012029 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.575062 # miss rate for demand accesses -system.l2c.demand_misses 123233 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 965 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 1223556084 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.570559 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 122268 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 213064 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency +system.l2c.demand_hits 89906 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses +system.l2c.demand_misses 123158 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 214295 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 19978.512484 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency +system.l2c.overall_accesses 213064 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 91062 # number of overall hits -system.l2c.overall_miss_latency 2462012029 # number of overall miss cycles -system.l2c.overall_miss_rate 0.575062 # miss rate for overall accesses -system.l2c.overall_misses 123233 # number of overall misses -system.l2c.overall_mshr_hits 965 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 1223556084 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.570559 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 122268 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1224111920 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits 89906 # number of overall hits +system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles +system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses +system.l2c.overall_misses 123158 # number of overall misses +system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 74376 # number of replacements -system.l2c.sampled_refs 74986 # Sample count of references to valid blocks. +system.l2c.replacements 73303 # number of replacements +system.l2c.sampled_refs 73894 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 633.319008 # Cycle average of tags in use -system.l2c.total_refs 149108 # Total number of references to valid blocks. +system.l2c.tagsinuse 633.737828 # Cycle average of tags in use +system.l2c.total_refs 148204 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 47583 # number of writebacks +system.l2c.writebacks 47216 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr deleted file mode 100644 index f89b5d5ce..000000000 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ /dev/null @@ -1,74 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... -system.cpu2: completed 10000 read accesses @10889862 -system.cpu6: completed 10000 read accesses @10965571 -system.cpu0: completed 10000 read accesses @10999807 -system.cpu1: completed 10000 read accesses @11061066 -system.cpu3: completed 10000 read accesses @11070068 -system.cpu5: completed 10000 read accesses @11143240 -system.cpu7: completed 10000 read accesses @11205415 -system.cpu4: completed 10000 read accesses @11436114 -system.cpu5: completed 20000 read accesses @22318031 -system.cpu2: completed 20000 read accesses @22337080 -system.cpu0: completed 20000 read accesses @22381736 -system.cpu6: completed 20000 read accesses @22509672 -system.cpu1: completed 20000 read accesses @22762640 -system.cpu7: completed 20000 read accesses @22874302 -system.cpu3: completed 20000 read accesses @22934916 -system.cpu4: completed 20000 read accesses @22955693 -system.cpu2: completed 30000 read accesses @33671766 -system.cpu5: completed 30000 read accesses @33722420 -system.cpu0: completed 30000 read accesses @33817843 -system.cpu1: completed 30000 read accesses @34138032 -system.cpu3: completed 30000 read accesses @34173736 -system.cpu6: completed 30000 read accesses @34210820 -system.cpu7: completed 30000 read accesses @34282426 -system.cpu4: completed 30000 read accesses @34509982 -system.cpu2: completed 40000 read accesses @45029426 -system.cpu5: completed 40000 read accesses @45134036 -system.cpu0: completed 40000 read accesses @45316016 -system.cpu3: completed 40000 read accesses @45518533 -system.cpu6: completed 40000 read accesses @45639311 -system.cpu1: completed 40000 read accesses @45681507 -system.cpu7: completed 40000 read accesses @45794833 -system.cpu4: completed 40000 read accesses @46027115 -system.cpu2: completed 50000 read accesses @56302892 -system.cpu5: completed 50000 read accesses @56333031 -system.cpu3: completed 50000 read accesses @56769550 -system.cpu0: completed 50000 read accesses @56860279 -system.cpu1: completed 50000 read accesses @56989965 -system.cpu7: completed 50000 read accesses @57056302 -system.cpu6: completed 50000 read accesses @57079409 -system.cpu4: completed 50000 read accesses @57116196 -system.cpu2: completed 60000 read accesses @67583365 -system.cpu5: completed 60000 read accesses @67785565 -system.cpu3: completed 60000 read accesses @68057386 -system.cpu0: completed 60000 read accesses @68158806 -system.cpu4: completed 60000 read accesses @68296537 -system.cpu6: completed 60000 read accesses @68386914 -system.cpu7: completed 60000 read accesses @68429516 -system.cpu1: completed 60000 read accesses @68460666 -system.cpu2: completed 70000 read accesses @79111322 -system.cpu5: completed 70000 read accesses @79209430 -system.cpu4: completed 70000 read accesses @79635720 -system.cpu0: completed 70000 read accesses @79745526 -system.cpu3: completed 70000 read accesses @79788385 -system.cpu1: completed 70000 read accesses @79799686 -system.cpu7: completed 70000 read accesses @79866566 -system.cpu6: completed 70000 read accesses @79989630 -system.cpu5: completed 80000 read accesses @90523593 -system.cpu2: completed 80000 read accesses @90753657 -system.cpu4: completed 80000 read accesses @91052610 -system.cpu6: completed 80000 read accesses @91127936 -system.cpu0: completed 80000 read accesses @91167181 -system.cpu1: completed 80000 read accesses @91235432 -system.cpu3: completed 80000 read accesses @91277914 -system.cpu7: completed 80000 read accesses @91382669 -system.cpu2: completed 90000 read accesses @101882254 -system.cpu5: completed 90000 read accesses @101888287 -system.cpu1: completed 90000 read accesses @102242250 -system.cpu4: completed 90000 read accesses @102331682 -system.cpu6: completed 90000 read accesses @102446126 -system.cpu3: completed 90000 read accesses @102480895 -system.cpu0: completed 90000 read accesses @102517256 -system.cpu7: completed 90000 read accesses @102831150 -system.cpu5: completed 100000 read accesses @113467820 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout deleted file mode 100644 index 3088b7501..000000000 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 27 2008 17:52:16 -M5 started Wed Feb 27 17:56:37 2008 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 113467820 because maximum number of loads reached diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 151c1ae57..a2a52df64 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -5,7 +5,7 @@ dummy=0 [drivesys] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.dev/configs/boot/netperf-server.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -35,7 +35,8 @@ side_b=drivesys.membus.port[0] [drivesys.cpu] type=AtomicSimpleCPU -children=dtb itb tracer +children=dtb interrupts itb tracer +checker=Null clock=1 cpu_id=0 defer_registration=false @@ -45,15 +46,18 @@ do_statistics_insts=true dtb=drivesys.cpu.dtb function_trace=false function_trace_start=0 +interrupts=drivesys.cpu.interrupts itb=drivesys.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=drivesys tracer=drivesys.cpu.tracer width=1 @@ -64,6 +68,9 @@ icache_port=drivesys.membus.port[2] type=AlphaDTB size=64 +[drivesys.cpu.interrupts] +type=AlphaInterrupts + [drivesys.cpu.itb] type=AlphaITB size=48 @@ -82,6 +89,7 @@ image=drivesys.disk0.image type=CowDiskImage children=child child=drivesys.disk0.image.child +image_file= read_only=false table_size=65536 @@ -101,6 +109,7 @@ image=drivesys.disk2.image type=CowDiskImage children=child child=drivesys.disk2.image.child +image_file= read_only=false table_size=65536 @@ -118,10 +127,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=drivesys.tsunami.pciconfig.pio -port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.console.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.tsunami.ide.config drivesys.tsunami.ide.dma +port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.tsunami.ide.config drivesys.tsunami.ide.dma [drivesys.membus] type=Bus @@ -129,6 +139,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=drivesys.membus.responder.pio @@ -153,19 +164,13 @@ pio=drivesys.membus.default [drivesys.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=drivesys.membus.port[1] -[drivesys.sim_console] -type=SimConsole -append_name=true -intr_control=drivesys.intrctrl -number=0 -output=console -port=3456 - [drivesys.simple_disk] type=SimpleDisk children=disk @@ -177,12 +182,30 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[drivesys.terminal] +type=Terminal +intr_control=drivesys.intrctrl +number=0 +output=true +port=3456 + [drivesys.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=drivesys.intrctrl system=drivesys +[drivesys.tsunami.backdoor] +type=AlphaBackdoor +cpu=drivesys.cpu +disk=drivesys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +terminal=drivesys.terminal +pio=drivesys.iobus.port[25] + [drivesys.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -192,30 +215,25 @@ system=drivesys tsunami=drivesys.tsunami pio=drivesys.iobus.port[1] -[drivesys.tsunami.console] -type=AlphaConsole -cpu=drivesys.cpu -disk=drivesys.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=drivesys.tsunami -sim_console=drivesys.sim_console -system=drivesys -pio=drivesys.iobus.port[25] - [drivesys.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -585,16 +603,22 @@ pio=drivesys.iobus.port[22] [drivesys.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -665,8 +689,8 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=drivesys.tsunami -sim_console=drivesys.sim_console system=drivesys +terminal=drivesys.terminal pio=drivesys.iobus.port[24] [etherdump] @@ -685,7 +709,7 @@ int1=drivesys.tsunami.ethernet.interface [testsys] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console @@ -694,7 +718,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.dev/configs/boot/netperf-stream-client.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -715,7 +739,8 @@ side_b=testsys.membus.port[0] [testsys.cpu] type=AtomicSimpleCPU -children=dtb itb tracer +children=dtb interrupts itb tracer +checker=Null clock=1 cpu_id=0 defer_registration=false @@ -725,15 +750,18 @@ do_statistics_insts=true dtb=testsys.cpu.dtb function_trace=false function_trace_start=0 +interrupts=testsys.cpu.interrupts itb=testsys.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 profile=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=testsys tracer=testsys.cpu.tracer width=1 @@ -744,6 +772,9 @@ icache_port=testsys.membus.port[2] type=AlphaDTB size=64 +[testsys.cpu.interrupts] +type=AlphaInterrupts + [testsys.cpu.itb] type=AlphaITB size=48 @@ -762,6 +793,7 @@ image=testsys.disk0.image type=CowDiskImage children=child child=testsys.disk0.image.child +image_file= read_only=false table_size=65536 @@ -781,6 +813,7 @@ image=testsys.disk2.image type=CowDiskImage children=child child=testsys.disk2.image.child +image_file= read_only=false table_size=65536 @@ -798,10 +831,11 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=true width=64 default=testsys.tsunami.pciconfig.pio -port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.console.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.tsunami.ide.config testsys.tsunami.ide.dma +port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.tsunami.ide.config testsys.tsunami.ide.dma [testsys.membus] type=Bus @@ -809,6 +843,7 @@ children=responder block_size=64 bus_id=1 clock=1000 +header_cycles=1 responder_set=false width=64 default=testsys.membus.responder.pio @@ -833,19 +868,13 @@ pio=testsys.membus.default [testsys.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=testsys.membus.port[1] -[testsys.sim_console] -type=SimConsole -append_name=true -intr_control=testsys.intrctrl -number=0 -output=console -port=3456 - [testsys.simple_disk] type=SimpleDisk children=disk @@ -857,12 +886,30 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[testsys.terminal] +type=Terminal +intr_control=testsys.intrctrl +number=0 +output=true +port=3456 + [testsys.tsunami] type=Tsunami -children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=testsys.intrctrl system=testsys +[testsys.tsunami.backdoor] +type=AlphaBackdoor +cpu=testsys.cpu +disk=testsys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +terminal=testsys.terminal +pio=testsys.iobus.port[25] + [testsys.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 @@ -872,30 +919,25 @@ system=testsys tsunami=testsys.tsunami pio=testsys.iobus.port[1] -[testsys.tsunami.console] -type=AlphaConsole -cpu=testsys.cpu -disk=testsys.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=testsys.tsunami -sim_console=testsys.sim_console -system=testsys -pio=testsys.iobus.port[25] - [testsys.tsunami.ethernet] type=NSGigE BAR0=1 +BAR0LegacyIO=false BAR0Size=256 BAR1=0 +BAR1LegacyIO=false BAR1Size=4096 BAR2=0 +BAR2LegacyIO=false BAR2Size=0 BAR3=0 +BAR3LegacyIO=false BAR3Size=0 BAR4=0 +BAR4LegacyIO=false BAR4Size=0 BAR5=0 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -1265,16 +1307,22 @@ pio=testsys.iobus.port[22] [testsys.tsunami.ide] type=IdeController BAR0=1 +BAR0LegacyIO=false BAR0Size=8 BAR1=1 +BAR1LegacyIO=false BAR1Size=4 BAR2=1 +BAR2LegacyIO=false BAR2Size=8 BAR3=1 +BAR3LegacyIO=false BAR3Size=4 BAR4=1 +BAR4LegacyIO=false BAR4Size=16 BAR5=1 +BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 @@ -1345,7 +1393,7 @@ type=Uart8250 pio_addr=8804615848952 pio_latency=1000 platform=testsys.tsunami -sim_console=testsys.sim_console system=testsys +terminal=testsys.terminal pio=testsys.iobus.port[24] diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal index 89c68d228..5501b27d6 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr new file mode 100755 index 000000000..c18ca3505 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Obsolete M5 ivlb instruction encountered. +For more information see: http://www.m5sim.org/warn/fcbd217d +hack: be nice to actually delete the event here diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout new file mode 100755 index 000000000..70f17d877 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:15:24 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:15:51 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 4300236804024 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 9f3e96104..267fa9175 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -39,8 +39,8 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572412849 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199572093137 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl @@ -59,8 +59,8 @@ drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # f drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.16% 1.40% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 108485080 98.60% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed drivesys.cpu.kern.syscall 22 # number of syscalls executed drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed @@ -76,7 +76,7 @@ drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # nu drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles -drivesys.cpu.numCycles 199572412849 # number of cpu cycles simulated +drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated drivesys.cpu.num_insts 1958129 # Number of instructions executed drivesys.cpu.num_refs 626223 # Number of memory references drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -91,7 +91,7 @@ drivesys.disk2.dma_read_txs 0 # Nu drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. -drivesys.tsunami.ethernet.coalescedRxDesc 1 # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post @@ -105,7 +105,7 @@ drivesys.tsunami.ethernet.descDMAWrites 13 # Nu drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 16 # number of posts to CPU drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU @@ -139,76 +139,76 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 129173906 # Simulator instruction rate (inst/s) -host_mem_usage 476620 # Number of bytes of host memory used -host_seconds 2.12 # Real time elapsed on the host -host_tick_rate 94522664540 # Simulator tick rate (ticks/s) +host_inst_rate 151383583 # Simulator instruction rate (inst/s) +host_mem_usage 478624 # Number of bytes of host memory used +host_seconds 1.81 # Real time elapsed on the host +host_tick_rate 110738300112 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294782 # Number of instructions simulated +sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163322 # DTB hits +testsys.cpu.dtb.hits 1163288 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658456 # DTB read hits +testsys.cpu.dtb.read_hits 658435 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504866 # DTB write hits +testsys.cpu.dtb.write_hits 504853 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249851 # ITB accesses +testsys.cpu.itb.accesses 1249822 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248354 # ITB hits +testsys.cpu.itb.hits 1248325 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13125 # number of callpals executed +testsys.cpu.kern.callpal 13122 # number of callpals executed testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11077 84.40% 87.89% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed -testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed +testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed +testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12507 # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7057 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199570420798 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569805534 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 566608 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716310 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 655 -testsys.cpu.kern.mode_good_user 650 +testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 654 +testsys.cpu.kern.mode_good_user 649 testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 650 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 380 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 1.608612 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.595455 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013158 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1822940 2.12% 2.12% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065616 1.24% 3.36% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 83000460 96.64% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed @@ -233,9 +233,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 199570420361 # number of cpu cycles simulated -testsys.cpu.num_insts 3560518 # Number of instructions executed -testsys.cpu.num_refs 1173605 # Number of memory references +testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated +testsys.cpu.num_insts 3560411 # Number of instructions executed +testsys.cpu.num_refs 1173571 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -255,14 +255,14 @@ testsys.tsunami.ethernet.coalescedRxOrn 0 # av testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU @@ -381,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 134363216323 # Simulator instruction rate (inst/s) -host_mem_usage 476620 # Number of bytes of host memory used +host_inst_rate 133483805176 # Simulator instruction rate (inst/s) +host_mem_usage 478624 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 362870729 # Simulator tick rate (ticks/s) +host_tick_rate 360871442 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294782 # Number of instructions simulated +sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr deleted file mode 100644 index 891b3e205..000000000 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ /dev/null @@ -1,6 +0,0 @@ -Listening for testsys connection on port 3456 -Listening for drivesys connection on port 3457 -0: testsys.remote_gdb.listener: listening for remote gdb on port 7000 -0: drivesys.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... -warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout deleted file mode 100644 index 324ab7868..000000000 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ /dev/null @@ -1,13 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Aug 21 2007 15:42:55 -M5 started Tue Aug 21 15:45:44 2007 -M5 executing on nacho -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4300235844056 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal index c1cb6aad0..ecae2497e 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/run.py b/tests/run.py index 9b77ff9d2..df26c88c5 100644 --- a/tests/run.py +++ b/tests/run.py @@ -26,10 +26,15 @@ # # Authors: Steve Reinhardt -import os, sys +import os +import sys +import m5 + +# Since we're in batch mode, dont allow tcp socket connections +m5.disableAllListeners() # single "path" arg encodes everything we need to know about test -(category, name, isa, opsys, config) = sys.argv[1].split('/') +(category, name, isa, opsys, config) = sys.argv[1].split('/')[-5:] # find path to directory containing this file tests_root = os.path.dirname(__file__) @@ -57,8 +62,7 @@ execfile(os.path.join(tests_root, 'configs', config + '.py')) # set default maxtick... script can override # -1 means run forever -from m5 import MaxTick -maxtick = MaxTick +maxtick = m5.MaxTick # tweak configuration for specific test |