diff options
Diffstat (limited to 'tests')
42 files changed, 12788 insertions, 12780 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index d98200efd..ca493d5ab 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.vram system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index f49caea0a..167ce3cc3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:01:45 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:28:00 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x40cab00 0x40cab00 - 0: system.cpu1.isa: ISA system set to: 0x40cab00 0x40cab00 + 0: system.cpu0.isa: ISA system set to: 0x5a2b680 0x5a2b680 + 0: system.cpu1.isa: ISA system set to: 0x5a2b680 0x5a2b680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2843718094000 because m5_exit instruction encountered +Exiting @ tick 2843665155500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index ffa50b552..a43b4e79e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,157 +1,175 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.843718 # Number of seconds simulated -sim_ticks 2843718094000 # Number of ticks simulated -final_tick 2843718094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.843665 # Number of seconds simulated +sim_ticks 2843665155500 # Number of ticks simulated +final_tick 2843665155500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161241 # Simulator instruction rate (inst/s) -host_op_rate 195251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3650642703 # Simulator tick rate (ticks/s) -host_mem_usage 606904 # Number of bytes of host memory used -host_seconds 778.96 # Real time elapsed on the host -sim_insts 125601128 # Number of instructions simulated -sim_ops 152093417 # Number of ops (including micro ops) simulated +host_inst_rate 158211 # Simulator instruction rate (inst/s) +host_op_rate 191554 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3597700350 # Simulator tick rate (ticks/s) +host_mem_usage 605956 # Number of bytes of host memory used +host_seconds 790.41 # Real time elapsed on the host +sim_insts 125052080 # Number of instructions simulated +sim_ops 151406456 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 10240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1341052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10709120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 541088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1237760 # Number of bytes read from this memory -system.physmem.bytes_read::total 13841180 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 411264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 443200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7176832 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 1364476 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 533600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1164672 # Number of bytes read from this memory +system.physmem.bytes_read::total 13841116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 419072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 26240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 445312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7174080 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9512912 # Number of bytes written to this memory +system.physmem.bytes_written::total 9510160 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 21479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 167330 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 19340 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 112138 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 21845 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 168230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 8361 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 18198 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216816 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112095 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 152798 # Number of write requests responded to by this memory +system.physmem.num_writes::total 152755 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 3601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 471584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3765887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 190275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 435261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4867283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 144622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2523749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 815248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 479830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3786212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 187645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 409567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4867351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 147370 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 9228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2522829 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 815263 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3345237 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2523749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 815586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3344332 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2522829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 815601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 477810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3765887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 190289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 435261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8212520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 216817 # Number of read requests accepted -system.physmem.writeReqs 152798 # Number of write requests accepted -system.physmem.readBursts 216817 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 152798 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13860672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue -system.physmem.bytesWritten 9527424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13841180 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9512912 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13461 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14081 # Per bank write bursts -system.physmem.perBankRdBursts::1 13907 # Per bank write bursts -system.physmem.perBankRdBursts::2 14464 # Per bank write bursts -system.physmem.perBankRdBursts::3 13988 # Per bank write bursts -system.physmem.perBankRdBursts::4 16210 # Per bank write bursts -system.physmem.perBankRdBursts::5 13087 # Per bank write bursts -system.physmem.perBankRdBursts::6 13697 # Per bank write bursts -system.physmem.perBankRdBursts::7 13930 # Per bank write bursts -system.physmem.perBankRdBursts::8 13098 # Per bank write bursts -system.physmem.perBankRdBursts::9 13410 # Per bank write bursts -system.physmem.perBankRdBursts::10 13015 # Per bank write bursts -system.physmem.perBankRdBursts::11 11706 # Per bank write bursts -system.physmem.perBankRdBursts::12 12947 # Per bank write bursts -system.physmem.perBankRdBursts::13 13659 # Per bank write bursts -system.physmem.perBankRdBursts::14 12722 # Per bank write bursts -system.physmem.perBankRdBursts::15 12652 # Per bank write bursts -system.physmem.perBankWrBursts::0 9756 # Per bank write bursts -system.physmem.perBankWrBursts::1 10039 # Per bank write bursts -system.physmem.perBankWrBursts::2 10215 # Per bank write bursts -system.physmem.perBankWrBursts::3 9785 # Per bank write bursts -system.physmem.perBankWrBursts::4 9214 # Per bank write bursts -system.physmem.perBankWrBursts::5 9161 # Per bank write bursts -system.physmem.perBankWrBursts::6 9492 # Per bank write bursts -system.physmem.perBankWrBursts::7 9434 # Per bank write bursts -system.physmem.perBankWrBursts::8 9026 # Per bank write bursts -system.physmem.perBankWrBursts::9 9356 # Per bank write bursts -system.physmem.perBankWrBursts::10 9095 # Per bank write bursts -system.physmem.perBankWrBursts::11 8550 # Per bank write bursts -system.physmem.perBankWrBursts::12 9129 # Per bank write bursts -system.physmem.perBankWrBursts::13 9225 # Per bank write bursts -system.physmem.perBankWrBursts::14 8893 # Per bank write bursts -system.physmem.perBankWrBursts::15 8496 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 486056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3786212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 187659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 409567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8211683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 216816 # Number of read requests accepted +system.physmem.writeReqs 152755 # Number of write requests accepted +system.physmem.readBursts 216816 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 152755 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13860032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16192 # Total number of bytes read from write queue +system.physmem.bytesWritten 9524672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13841116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9510160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 253 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13536 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13436 # Per bank write bursts +system.physmem.perBankRdBursts::1 13084 # Per bank write bursts +system.physmem.perBankRdBursts::2 14401 # Per bank write bursts +system.physmem.perBankRdBursts::3 13747 # Per bank write bursts +system.physmem.perBankRdBursts::4 15799 # Per bank write bursts +system.physmem.perBankRdBursts::5 12797 # Per bank write bursts +system.physmem.perBankRdBursts::6 13572 # Per bank write bursts +system.physmem.perBankRdBursts::7 13744 # Per bank write bursts +system.physmem.perBankRdBursts::8 13565 # Per bank write bursts +system.physmem.perBankRdBursts::9 13602 # Per bank write bursts +system.physmem.perBankRdBursts::10 13295 # Per bank write bursts +system.physmem.perBankRdBursts::11 11895 # Per bank write bursts +system.physmem.perBankRdBursts::12 13378 # Per bank write bursts +system.physmem.perBankRdBursts::13 13725 # Per bank write bursts +system.physmem.perBankRdBursts::14 13486 # Per bank write bursts +system.physmem.perBankRdBursts::15 13037 # Per bank write bursts +system.physmem.perBankWrBursts::0 9315 # Per bank write bursts +system.physmem.perBankWrBursts::1 9418 # Per bank write bursts +system.physmem.perBankWrBursts::2 10151 # Per bank write bursts +system.physmem.perBankWrBursts::3 9572 # Per bank write bursts +system.physmem.perBankWrBursts::4 8971 # Per bank write bursts +system.physmem.perBankWrBursts::5 8910 # Per bank write bursts +system.physmem.perBankWrBursts::6 9379 # Per bank write bursts +system.physmem.perBankWrBursts::7 9378 # Per bank write bursts +system.physmem.perBankWrBursts::8 9384 # Per bank write bursts +system.physmem.perBankWrBursts::9 9425 # Per bank write bursts +system.physmem.perBankWrBursts::10 9360 # Per bank write bursts +system.physmem.perBankWrBursts::11 8832 # Per bank write bursts +system.physmem.perBankWrBursts::12 9377 # Per bank write bursts +system.physmem.perBankWrBursts::13 9192 # Per bank write bursts +system.physmem.perBankWrBursts::14 9288 # Per bank write bursts +system.physmem.perBankWrBursts::15 8871 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2843715756500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 2843662895000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 216230 # Read request sizes (log2) +system.physmem.readPktSize::6 216229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148362 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 79662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148319 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62843 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 208 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -179,633 +197,612 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 253.241254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.538036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.020470 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46699 50.56% 50.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18860 20.42% 70.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6817 7.38% 78.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3583 3.88% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3053 3.31% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2112 2.29% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1277 1.38% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1140 1.23% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8814 9.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92355 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7471 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.988355 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 530.902810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7470 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 252.591884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.134462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.650054 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46986 50.75% 50.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18789 20.30% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6843 7.39% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3586 3.87% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3022 3.26% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1307 1.41% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1131 1.22% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8795 9.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92579 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7460 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.029759 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 529.579779 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7459 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7471 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7471 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.925847 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.607688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.837629 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6200 82.99% 82.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 464 6.21% 89.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 76 1.02% 90.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 210 2.81% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 192 2.57% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 15 0.20% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 27 0.36% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.20% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 29 0.39% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.13% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.12% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.08% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.18% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.05% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 14 0.19% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.11% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7471 # Writes before turning the bus around for reads -system.physmem.totQLat 7621074500 # Total ticks spent queuing -system.physmem.totMemAccLat 11681818250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1082865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35189.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7460 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7460 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.949464 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.624141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.915893 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6155 82.51% 82.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 493 6.61% 89.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 89 1.19% 90.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 200 2.68% 92.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 188 2.52% 95.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.23% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 27 0.36% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 16 0.21% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 36 0.48% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.13% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.05% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 168 2.25% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.13% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7460 # Writes before turning the bus around for reads +system.physmem.totQLat 7660076750 # Total ticks spent queuing +system.physmem.totMemAccLat 11720633000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1082815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35371.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53939.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 54121.12 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing -system.physmem.readRowHits 183248 # Number of row buffer hits during reads -system.physmem.writeRowHits 89836 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.34 # Row buffer hit rate for writes -system.physmem.avgGap 7693723.89 # Average gap between requests -system.physmem.pageHitRate 74.72 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2710028687250 # Time in different power states -system.physmem.memoryStateTime::REF 94957980000 # Time in different power states +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 183124 # Number of row buffer hits during reads +system.physmem.writeRowHits 89683 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.25 # Row buffer hit rate for writes +system.physmem.avgGap 7694496.85 # Average gap between requests +system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2709761139750 # Time in different power states +system.physmem.memoryStateTime::REF 94956160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 38731176500 # Time in different power states +system.physmem.memoryStateTime::ACT 38946040250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 365654520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 332549280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 199513875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 181450500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 884239200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 805030200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 499582080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 465069600 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 185737808880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 185737808880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82126203345 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81336736530 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1634190168750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1634882683500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1904003170650 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1903741328490 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.547151 # Core power per rank (mW) -system.physmem.averagePower::1 669.455073 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 1280 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 450 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 450 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 450 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 238282 # Transaction distribution -system.membus.trans_dist::ReadResp 238282 # Transaction distribution -system.membus.trans_dist::WriteReq 31054 # Transaction distribution -system.membus.trans_dist::WriteResp 31054 # Transaction distribution -system.membus.trans_dist::Writeback 112138 # Transaction distribution +system.physmem.actEnergy::0 358880760 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 341016480 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 195817875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 186070500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 862524000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 826667400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 486609120 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 477763920 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 185734248960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 185734248960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 81966350835 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81438405435 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1634297688000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1634760798000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1903902119550 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1903764970695 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.524448 # Core power per rank (mW) +system.physmem.averagePower::1 669.476219 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 238011 # Transaction distribution +system.membus.trans_dist::ReadResp 238011 # Transaction distribution +system.membus.trans_dist::WriteReq 30931 # Transaction distribution +system.membus.trans_dist::WriteResp 30931 # Transaction distribution +system.membus.trans_dist::Writeback 112095 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 80328 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40430 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13461 # Transaction distribution -system.membus.trans_dist::ReadExReq 30145 # Transaction distribution -system.membus.trans_dist::ReadExResp 13182 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79719 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39980 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13536 # Transaction distribution +system.membus.trans_dist::ReadExReq 30379 # Transaction distribution +system.membus.trans_dist::ReadExResp 13328 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 705796 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 827846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72718 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72718 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704855 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 826435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 899141 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21034796 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21227006 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21031980 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21223190 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23546302 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 124500 # Total snoops (count) -system.membus.snoop_fanout::samples 499399 # Request fanout histogram +system.membus.pkt_size::total 23542486 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123442 # Total snoops (count) +system.membus.snoop_fanout::samples 498376 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 499399 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 498376 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 499399 # Request fanout histogram -system.membus.reqLayer0.occupancy 87896996 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 498376 # Request fanout histogram +system.membus.reqLayer0.occupancy 87914995 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12141500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11673499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1620346498 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1620072999 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2120331885 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2120142312 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38636884 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38549614 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 151104 # number of replacements -system.l2c.tags.tagsinuse 64343.342453 # Cycle average of tags in use -system.l2c.tags.total_refs 537709 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 215892 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.490639 # Average number of references to valid blocks. +system.l2c.tags.replacements 151709 # number of replacements +system.l2c.tags.tagsinuse 64474.290498 # Cycle average of tags in use +system.l2c.tags.total_refs 529875 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 216478 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.447708 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13312.566907 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.661228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033237 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3627.484276 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 40388.691608 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.364745 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 878.502916 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6044.037536 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.203134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001246 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.055351 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.616283 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000158 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.013405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.092225 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.981801 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 46495 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 18259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 432 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6889 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2341 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15618 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.709457 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000519 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.278610 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6702696 # Number of tag accesses -system.l2c.tags.data_accesses 6702696 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 575 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 36632 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 209337 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 45 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 12148 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 48809 # number of ReadReq hits -system.l2c.ReadReq_hits::total 307807 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 253703 # number of Writeback hits -system.l2c.Writeback_hits::total 253703 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 11935 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 1029 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12964 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 208 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 174 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 382 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 3683 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 1200 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4883 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 575 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 40315 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 209337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 45 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 13348 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 48809 # number of demand (read+write) hits -system.l2c.demand_hits::total 312690 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 575 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits -system.l2c.overall_hits::cpu0.inst 40315 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 209337 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 139 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 45 # number of overall hits -system.l2c.overall_hits::cpu1.inst 13348 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 48809 # number of overall hits -system.l2c.overall_hits::total 312690 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 160 # number of ReadReq misses +system.l2c.tags.occ_blocks::writebacks 12364.739343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831819 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030523 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3875.049948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42732.474457 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.614781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 756.297533 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4653.252093 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.188671 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059129 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.652046 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011540 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071003 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983800 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 46265 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 18457 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6570 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39426 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2643 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15559 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.705948 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.281631 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6643854 # Number of tag accesses +system.l2c.tags.data_accesses 6643854 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 549 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 36725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207902 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 47 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11423 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45111 # number of ReadReq hits +system.l2c.ReadReq_hits::total 301987 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 252491 # number of Writeback hits +system.l2c.Writeback_hits::total 252491 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 11970 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 853 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12823 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 185 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 180 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 3516 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 1122 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4638 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 40241 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 207902 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 47 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 12545 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 45111 # number of demand (read+write) hits +system.l2c.demand_hits::total 306625 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 549 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 114 # number of overall hits +system.l2c.overall_hits::cpu0.inst 40241 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 207902 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 116 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 47 # number of overall hits +system.l2c.overall_hits::cpu1.inst 12545 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 45111 # number of overall hits +system.l2c.overall_hits::total 306625 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 11021 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 167331 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2011 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq misses -system.l2c.ReadReq_misses::total 199878 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 8877 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 2752 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11629 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 464 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1248 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1712 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 6943 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 6359 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 13302 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 160 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 11298 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1836 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18199 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199730 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 9030 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 470 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1259 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1729 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 7024 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 6416 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 13440 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17964 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 167331 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8370 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) misses -system.l2c.demand_misses::total 213180 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 160 # number of overall misses +system.l2c.demand_misses::cpu0.inst 18322 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8252 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 18199 # number of demand (read+write) misses +system.l2c.demand_misses::total 213170 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17964 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 167331 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8370 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 19340 # number of overall misses -system.l2c.overall_misses::total 213180 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13245499 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 18322 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 168230 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses +system.l2c.overall_misses::cpu1.inst 8252 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 18199 # number of overall misses +system.l2c.overall_misses::total 213170 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 927632991 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1117750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 171510999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 21228443106 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 10247078 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 3439358 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 13686436 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1071455 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1047955 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2119410 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 585218901 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 465754979 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1050973880 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 13245499 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 956701998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 150016000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 21240863385 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 10890561 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 2732384 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 13622945 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1227450 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 930960 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2158410 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 595061904 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 477250480 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1072312384 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1512851892 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1117750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 637265978 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22279416986 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 13245499 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1551763902 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 627266480 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22313175769 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1512851892 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1117750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 637265978 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22279416986 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 735 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 123 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 47653 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376668 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 153 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 14159 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68149 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 507685 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 253703 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 253703 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 20812 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 3781 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 24593 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 672 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 1422 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 1551763902 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1343500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 627266480 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22313175769 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 700 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 115 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 48023 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376132 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 131 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13259 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63310 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 501717 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 252491 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 252491 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 21000 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 3518 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24518 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 655 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 1439 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 10626 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 7559 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18185 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 735 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 123 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 58279 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376668 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 153 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 21718 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68149 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 525870 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 735 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 123 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 58279 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376668 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 153 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 21718 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68149 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 525870 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008130 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.231276 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.142030 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.393705 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.426533 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.727850 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.472858 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.690476 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.877637 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.817574 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.653397 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.841249 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.731482 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.008130 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.308241 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.385395 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.405385 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.008130 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.308241 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.385395 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.405385 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average ReadReq miss latency +system.l2c.ReadExReq_accesses::cpu0.inst 10540 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 7538 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18078 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 700 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 115 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 58563 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376132 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 131 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 20797 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63310 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 519795 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 700 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 115 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 58563 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376132 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 131 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 20797 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63310 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 519795 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008696 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.235262 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.138472 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.398093 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.757533 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.476996 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.717557 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.874913 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.825692 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.666414 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.851154 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.743445 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.008696 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.312860 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.396788 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.410104 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.008696 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.312860 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.396788 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.410104 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84169.584520 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85286.424167 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 106207.001801 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1154.340205 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1249.766715 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1176.922865 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2309.170259 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 839.707532 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1237.973131 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84289.053867 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73243.431200 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 79008.711472 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84678.881041 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81708.061002 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 106347.886572 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1206.042193 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1025.284803 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1164.852074 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2611.595745 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 739.444003 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1248.357432 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84718.380410 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74384.426434 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 79785.147619 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 104509.883601 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 104673.151799 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 104509.883601 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 27 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 104673.151799 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 758 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 36.095238 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112138 # number of writebacks -system.l2c.writebacks::total 112138 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 160 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 112095 # number of writebacks +system.l2c.writebacks::total 112095 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 11020 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2011 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 199876 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 8877 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2752 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11629 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 464 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1248 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1712 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 6943 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 6359 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 13302 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 160 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 11298 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1836 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 199729 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9030 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11695 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 470 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1259 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1729 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 7024 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 6416 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 13440 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17963 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 8370 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 213178 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 160 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 18322 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 8252 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 213169 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17963 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 8370 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 213178 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 18322 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 8252 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 213169 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 790589241 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 946250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146552499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 18767530106 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 89623803 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 27822731 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 117446534 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4677961 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12575743 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 17253704 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 498567599 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 385443021 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 884010620 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 816212498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 127225500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 18781676635 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91207456 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26838142 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 118045598 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4758966 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12646753 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 17405719 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 507430588 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396239520 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 903670108 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1289156840 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 946250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 531995520 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 19651540726 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1323643086 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 523465020 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 19685346743 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1289156840 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 946250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 531995520 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 19651540726 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5455196250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 328328000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5783524250 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4031988000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 216852500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4248840500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9487184250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 545180500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10032364750 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.231255 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.142030 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.393701 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.426533 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.727850 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.472858 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.690476 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.877637 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817574 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.653397 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.841249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.731482 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.405382 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.405382 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 1323643086 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 523465020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 19685346743 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518668247 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263087751 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5781755998 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4095979500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150492500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4246472000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614647747 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413580251 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10028227998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235262 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138472 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.398091 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.757533 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.476996 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.717557 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.874913 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.825692 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.666414 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.851154 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.743445 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.410102 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.410102 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71741.310436 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72875.434610 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 93895.865967 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10096.181480 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10110.003997 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10099.452575 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10081.812500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.717147 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.098131 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 71808.670459 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60613.779053 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 66456.970380 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72243.981059 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69294.934641 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 94035.801686 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10100.493466 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.597373 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.680889 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10125.459574 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10045.077840 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10066.928282 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72242.395786 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61758.029925 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67237.359226 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -853,50 +850,50 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 675950 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 675935 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31054 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31054 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 253703 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 93172 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40812 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 133984 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39254 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39254 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372089 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 383613 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1755702 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 42006746 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8315748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 50322494 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 294957 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1100978 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033136 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.178992 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 668242 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 668227 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30931 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30931 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 252491 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 92430 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40345 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 132775 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 38935 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 38935 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370727 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368021 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1738748 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41983735 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7870623 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49854358 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 291977 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1090667 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033442 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.179788 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1064496 96.69% 96.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36482 3.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1054193 96.66% 96.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36474 3.34% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1100978 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1599263913 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1090667 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1589069612 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2370465695 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2362873368 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 831346703 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 802585372 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31024 # Transaction distribution -system.iobus.trans_dist::ReadResp 31024 # Transaction distribution -system.iobus.trans_dist::WriteReq 59407 # Transaction distribution +system.iobus.trans_dist::ReadReq 31012 # Transaction distribution +system.iobus.trans_dist::ReadResp 31012 # Transaction distribution +system.iobus.trans_dist::WriteReq 59405 # Transaction distribution system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 35 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -919,9 +916,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -944,9 +941,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -987,23 +984,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326680325 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326655076 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36847116 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36825386 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 34854856 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17109626 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1616877 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20006820 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14503231 # Number of BTB hits +system.cpu0.branchPred.lookups 34893743 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17129146 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1674704 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20005904 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14465623 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.491435 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10748202 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 771222 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.306770 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10813555 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 822515 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1027,25 +1024,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23968692 # DTB read hits -system.cpu0.dtb.read_misses 61651 # DTB read misses -system.cpu0.dtb.write_hits 17871018 # DTB write hits -system.cpu0.dtb.write_misses 6619 # DTB write misses +system.cpu0.dtb.read_hits 23970791 # DTB read hits +system.cpu0.dtb.read_misses 62431 # DTB read misses +system.cpu0.dtb.write_hits 17948475 # DTB write hits +system.cpu0.dtb.write_misses 6765 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3502 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1211 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1921 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3473 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1381 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1976 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 566 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24030343 # DTB read accesses -system.cpu0.dtb.write_accesses 17877637 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24033222 # DTB read accesses +system.cpu0.dtb.write_accesses 17955240 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41839710 # DTB hits -system.cpu0.dtb.misses 68270 # DTB misses -system.cpu0.dtb.accesses 41907980 # DTB accesses +system.cpu0.dtb.hits 41919266 # DTB hits +system.cpu0.dtb.misses 69196 # DTB misses +system.cpu0.dtb.accesses 41988462 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1067,8 +1064,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 70097291 # ITB inst hits -system.cpu0.itb.inst_misses 3844 # ITB inst misses +system.cpu0.itb.inst_hits 70366530 # ITB inst hits +system.cpu0.itb.inst_misses 3846 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1081,79 +1078,79 @@ system.cpu0.itb.flush_entries 2220 # Nu system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7362 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7369 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70101135 # ITB inst accesses -system.cpu0.itb.hits 70097291 # DTB hits -system.cpu0.itb.misses 3844 # DTB misses -system.cpu0.itb.accesses 70101135 # DTB accesses -system.cpu0.numCycles 227722348 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70370376 # ITB inst accesses +system.cpu0.itb.hits 70366530 # DTB hits +system.cpu0.itb.misses 3846 # DTB misses +system.cpu0.itb.accesses 70370376 # DTB accesses +system.cpu0.numCycles 229133691 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 109201964 # Number of instructions committed -system.cpu0.committedOps 132004483 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8817575 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1858 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5459726684 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.085332 # CPI: cycles per instruction -system.cpu0.ipc 0.479540 # IPC: instructions per cycle +system.cpu0.committedInsts 109191897 # Number of instructions committed +system.cpu0.committedOps 132018821 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8795011 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1826 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5458210303 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.098450 # CPI: cycles per instruction +system.cpu0.ipc 0.476542 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1864 # number of quiesce instructions executed -system.cpu0.tickCycles 192189087 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 35533261 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 1960423 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.796865 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 68128653 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1960935 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.742943 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed +system.cpu0.tickCycles 193242697 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 35890994 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 1983122 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.796419 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 68375163 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1983634 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.469647 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796865 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796419 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999602 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999602 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 142140155 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 142140155 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 68128653 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 68128653 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 68128653 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 68128653 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 68128653 # number of overall hits -system.cpu0.icache.overall_hits::total 68128653 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1960950 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1960950 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1960950 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1960950 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1960950 # number of overall misses -system.cpu0.icache.overall_misses::total 1960950 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16347715808 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16347715808 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16347715808 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16347715808 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16347715808 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16347715808 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70089603 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70089603 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70089603 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70089603 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70089603 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70089603 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027978 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.027978 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027978 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.027978 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027978 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.027978 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8336.630617 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8336.630617 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8336.630617 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8336.630617 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 142701293 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 142701293 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 68375163 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 68375163 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 68375163 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 68375163 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 68375163 # number of overall hits +system.cpu0.icache.overall_hits::total 68375163 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1983656 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1983656 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1983656 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1983656 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1983656 # number of overall misses +system.cpu0.icache.overall_misses::total 1983656 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16542962894 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16542962894 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16542962894 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16542962894 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16542962894 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16542962894 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70358819 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70358819 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70358819 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70358819 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70358819 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70358819 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028193 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028193 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028193 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028193 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028193 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028193 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.632927 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.632927 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8339.632927 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8339.632927 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1162,366 +1159,376 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1960950 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1960950 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1960950 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1960950 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1960950 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1960950 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13404270692 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13404270692 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13404270692 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13404270692 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13404270692 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13404270692 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276968500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276968500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276968500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 276968500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027978 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6835.600445 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1983656 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1983656 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1983656 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1983656 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1983656 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13565509604 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13565509604 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13565509604 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13565509604 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13565509604 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13565509604 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028193 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028193 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028193 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.640169 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2745512 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2644445 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28520 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28520 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 513053 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 701523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 70947 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 94006 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 290299 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 280446 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3928023 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2381529 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11804 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166842 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6488198 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 125696704 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86351322 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17688 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313268 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 212378982 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1094951 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4365889 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.223377 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.416509 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2764616 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2669805 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28812 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28812 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 518092 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 696796 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 70569 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42644 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 93797 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 291655 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 282058 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3973433 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393866 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11794 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6546649 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127149824 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86895095 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17624 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313964 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 214376507 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1084116 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4385551 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.219745 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.414074 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3390648 77.66% 77.66% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 975241 22.34% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3421847 78.03% 78.03% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 963704 21.97% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4365889 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2254798560 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4385551 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2275908733 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 118870000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 119359000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2947700808 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2981732395 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1230574902 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1235696460 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7385992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7392491 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 88548223 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 89085972 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17144913 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425558 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16187872 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8427 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17333419 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425629 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16380209 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9025 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6267 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 516786 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1326511 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6465 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512088 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329549 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 410501 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16214.104593 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2982888 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 426752 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.989746 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2824483316500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4342.913069 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.461328 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076713 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2208.018647 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9615.634836 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.265070 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002897 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134767 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.586892 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989630 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8959 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7283 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2957 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 667 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 409658 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16201.472263 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3013143 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 425913 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.074550 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2824446064500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4208.967244 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.817277 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.069510 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2196.768436 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.849796 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.256895 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134080 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594962 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.988859 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8953 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7296 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2849 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5159 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 779 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3107 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3633 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 224 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546814 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444519 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 54811525 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 54811525 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77296 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4241 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2365837 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2447374 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 513053 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 513053 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4545 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 4545 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2277 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2277 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 221177 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 221177 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77296 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4241 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 2587014 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2668551 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77296 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4241 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 2587014 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2668551 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1021 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 181 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94620 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 95822 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 28011 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 28011 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 18233 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18233 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46900 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 46900 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1021 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 181 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 141520 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 142722 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1021 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 181 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 141520 # number of overall misses -system.cpu0.l2cache.overall_misses::total 142722 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 34165499 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4027498 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2870753873 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 2908946870 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 500227988 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 500227988 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 361106760 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 361106760 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 90500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 90500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1915708255 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1915708255 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 34165499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4027498 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4786462128 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 4824655125 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 34165499 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4027498 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4786462128 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 4824655125 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78317 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4422 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2460457 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 2543196 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 513053 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 513053 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32556 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 32556 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20510 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20510 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 268077 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 268077 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78317 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4422 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 2728534 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2811273 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78317 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4422 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 2728534 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2811273 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040932 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.038456 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.037678 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.860394 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.860394 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888981 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888981 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.174950 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174950 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040932 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051867 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.050768 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040932 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051867 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.050768 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22251.370166 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30339.821105 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30357.818351 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17858.269537 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17858.269537 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19805.120386 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19805.120386 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 40846.657889 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 40846.657889 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 33804.564993 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 33804.564993 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 27297 # number of cycles access was blocked +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3166 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 286 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546448 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.445312 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 55304097 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 55304097 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77521 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390628 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2472389 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 518092 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 518092 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4676 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 4676 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2297 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2297 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223112 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 223112 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77521 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4240 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 2613740 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2695501 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77521 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4240 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 2613740 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2695501 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 970 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 166 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94231 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 95367 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27951 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27951 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17951 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 17951 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46376 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 46376 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 970 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 166 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 140607 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 141743 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 970 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 166 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 140607 # number of overall misses +system.cpu0.l2cache.overall_misses::total 141743 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31913749 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3705999 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2892277884 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 2927897632 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 496957551 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 496957551 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 355013747 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 355013747 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 117000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 117000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1927567955 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1927567955 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31913749 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3705999 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4819845839 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 4855465587 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31913749 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3705999 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4819845839 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 4855465587 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78491 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4406 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2484859 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 2567756 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 518092 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 518092 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32627 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 32627 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20248 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20248 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269488 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269488 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78491 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4406 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 2754347 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2837244 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78491 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4406 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 2754347 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2837244 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037676 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037922 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.037140 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856683 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856683 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.886557 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.886557 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.172089 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.172089 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037676 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051049 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.049958 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037676 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051049 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.049958 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22325.295181 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30693.486050 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30701.370831 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17779.598261 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17779.598261 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19776.822851 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19776.822851 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 58500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 58500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41563.911398 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41563.911398 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 34255.417107 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 34255.417107 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 26197 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 390 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 374 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 69.992308 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 70.045455 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 214261 # number of writebacks -system.cpu0.l2cache.writebacks::total 214261 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7719 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 7719 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3119 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3119 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10838 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 10838 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10838 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 10838 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1021 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 181 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86901 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 88103 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 516784 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 28011 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 28011 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 18233 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18233 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43781 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43781 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 1021 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 181 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 130682 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 131884 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1021 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 181 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 130682 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 648668 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2760498 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2099218995 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2128978496 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21179021871 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 474290503 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 474290503 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 241043533 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 241043533 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 69500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 69500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189749710 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189749710 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2760498 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3288968705 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 3318728206 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2760498 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3288968705 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 24497750077 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6107809749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6107809749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4518638513 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4518638513 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10626448262 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10626448262 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035319 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034643 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 214192 # number of writebacks +system.cpu0.l2cache.writebacks::total 214192 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7707 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 7707 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3080 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3080 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10787 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 10787 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10787 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 10787 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 970 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 166 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86524 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 87660 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 512085 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27951 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27951 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17951 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17951 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43296 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43296 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 970 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 166 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129820 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 130956 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 970 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 166 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129820 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 643041 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2543999 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121731252 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149385000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21314968847 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476593305 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476593305 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237494522 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237494522 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 89000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 89000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1192659250 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1192659250 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2543999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3314390502 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3342044250 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2543999 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3314390502 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24657013097 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176307748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176307748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587485503 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587485503 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763793251 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763793251 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034820 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034139 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.860394 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.860394 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888981 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888981 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.163315 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163315 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046913 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856683 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856683 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.886557 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.886557 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160660 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160660 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046156 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230738 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24156.442331 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24164.653826 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40982.348275 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16932.294563 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16932.294563 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13220.179510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13220.179510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27175.023640 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27175.023640 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25163.994162 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37766.238009 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226643 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24521.881235 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24519.564225 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41623.888313 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17051.028765 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17051.028765 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13230.155535 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13230.155535 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27546.638258 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27546.638258 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25520.359892 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38344.387212 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1529,98 +1536,98 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 712097 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.191982 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40404438 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 712609 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.699309 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306793500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 497.191982 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.971078 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.971078 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 714989 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.379861 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40475201 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715501 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.569035 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.379861 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965586 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965586 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83631959 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83631959 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 22807107 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22807107 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 16791710 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16791710 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 380026 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 380026 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 361110 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361110 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 39598817 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 39598817 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 39598817 # number of overall hits -system.cpu0.dcache.overall_hits::total 39598817 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 535335 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 535335 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 529873 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 529873 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6515 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6515 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20510 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20510 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1065208 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1065208 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1065208 # number of overall misses -system.cpu0.dcache.overall_misses::total 1065208 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6583386279 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6583386279 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 7974270273 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7974270273 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 107544752 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 107544752 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 444281550 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 444281550 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 99500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 99500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 14557656552 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14557656552 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 14557656552 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14557656552 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23342442 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23342442 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17321583 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17321583 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 386541 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386541 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 381620 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381620 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 40664025 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40664025 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 40664025 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40664025 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.022934 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.022934 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030590 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030590 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016855 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016855 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.053745 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053745 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026195 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026195 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026195 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026195 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12297.694488 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12297.694488 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15049.399145 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15049.399145 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16507.252801 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16507.252801 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21661.704047 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21661.704047 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83786238 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83786238 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 22803865 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22803865 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862785 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16862785 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381543 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 381543 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362585 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362585 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 39666650 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 39666650 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 39666650 # number of overall hits +system.cpu0.dcache.overall_hits::total 39666650 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 537471 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 537471 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 532850 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 532850 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6422 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6422 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20250 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20250 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 1070321 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1070321 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 1070321 # number of overall misses +system.cpu0.dcache.overall_misses::total 1070321 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609205728 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6609205728 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8024129751 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8024129751 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 106247249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 106247249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438093543 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 438093543 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 14633335479 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 14633335479 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 14633335479 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 14633335479 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23341336 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23341336 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395635 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17395635 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387965 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387965 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 40736971 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40736971 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 40736971 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40736971 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023027 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.023027 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030631 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030631 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016553 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016553 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052895 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052895 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026274 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026274 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026274 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026274 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12296.860162 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12296.860162 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15058.890403 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15058.890403 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16544.261756 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16544.261756 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21634.249037 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21634.249037 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13666.491945 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13666.491945 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13671.912892 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13671.912892 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1629,74 +1636,76 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 513055 # number of writebacks -system.cpu0.dcache.writebacks::total 513055 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42339 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42339 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 229244 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 229244 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 271583 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 271583 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 271583 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 271583 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 492996 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 492996 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 300629 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 300629 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6515 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6515 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20510 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20510 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 793625 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 793625 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 793625 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 793625 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5093716162 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5093716162 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4246170249 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4246170249 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94499248 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94499248 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 402814450 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 402814450 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 93500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 93500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9339886411 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9339886411 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9339886411 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9339886411 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6120470998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6120470998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4732689487 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4732689487 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10853160485 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10853160485 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021120 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021120 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017356 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017356 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016855 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016855 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.053745 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053745 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.019517 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019517 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10332.165295 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10332.165295 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14124.286908 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14124.286908 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14504.873062 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.873062 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19639.904924 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19639.904924 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 518095 # number of writebacks +system.cpu0.dcache.writebacks::total 518095 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42683 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 42683 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230741 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 230741 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273424 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 273424 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273424 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 273424 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494788 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 494788 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302109 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 302109 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6421 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6421 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20250 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20250 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796897 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 796897 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796897 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 796897 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5118044180 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118044180 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4273159157 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4273159157 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 93352250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93352250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397142457 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397142457 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9391203337 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9391203337 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9391203337 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9391203337 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191390497 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191390497 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803718496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803718496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995108993 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995108993 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021198 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021198 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017367 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017367 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016550 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016550 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052895 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052895 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.019562 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019562 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10343.913312 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10343.913312 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14144.428524 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14144.428524 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14538.584333 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14538.584333 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19611.973185 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19611.973185 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1704,15 +1713,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4191050 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2447557 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 261619 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2683528 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1692147 # Number of BTB hits +system.cpu1.branchPred.lookups 4041852 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2340524 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 248983 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2647417 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1629039 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.056804 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 827495 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 59633 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 61.533147 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 795039 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 55831 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1736,25 +1745,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4177995 # DTB read hits -system.cpu1.dtb.read_misses 21525 # DTB read misses -system.cpu1.dtb.write_hits 3468676 # DTB write hits -system.cpu1.dtb.write_misses 1889 # DTB write misses +system.cpu1.dtb.read_hits 4061119 # DTB read hits +system.cpu1.dtb.read_misses 20366 # DTB read misses +system.cpu1.dtb.write_hits 3327004 # DTB write hits +system.cpu1.dtb.write_misses 1507 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2064 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 236 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 360 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2038 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 134 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4199520 # DTB read accesses -system.cpu1.dtb.write_accesses 3470565 # DTB write accesses +system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4081485 # DTB read accesses +system.cpu1.dtb.write_accesses 3328511 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7646671 # DTB hits -system.cpu1.dtb.misses 23414 # DTB misses -system.cpu1.dtb.accesses 7670085 # DTB accesses +system.cpu1.dtb.hits 7388123 # DTB hits +system.cpu1.dtb.misses 21873 # DTB misses +system.cpu1.dtb.accesses 7409996 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1776,8 +1785,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7954981 # ITB inst hits -system.cpu1.itb.inst_misses 2237 # ITB inst misses +system.cpu1.itb.inst_hits 7667797 # ITB inst hits +system.cpu1.itb.inst_misses 2228 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1790,78 +1799,78 @@ system.cpu1.itb.flush_entries 1156 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1890 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7957218 # ITB inst accesses -system.cpu1.itb.hits 7954981 # DTB hits -system.cpu1.itb.misses 2237 # DTB misses -system.cpu1.itb.accesses 7957218 # DTB accesses -system.cpu1.numCycles 42108230 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7670025 # ITB inst accesses +system.cpu1.itb.hits 7667797 # DTB hits +system.cpu1.itb.misses 2228 # DTB misses +system.cpu1.itb.accesses 7670025 # DTB accesses +system.cpu1.numCycles 40526065 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 16399164 # Number of instructions committed -system.cpu1.committedOps 20088934 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1607897 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2744 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5644728223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.567706 # CPI: cycles per instruction -system.cpu1.ipc 0.389453 # IPC: instructions per cycle +system.cpu1.committedInsts 15860183 # Number of instructions committed +system.cpu1.committedOps 19387635 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1556469 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2802 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5646205885 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.555208 # CPI: cycles per instruction +system.cpu1.ipc 0.391358 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed -system.cpu1.tickCycles 30601119 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 11507111 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 921368 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.459165 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7030999 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 921880 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.626805 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 71222254500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459165 # Average occupied blocks per requestor +system.cpu1.kern.inst.quiesce 2803 # number of quiesce instructions executed +system.cpu1.tickCycles 29467033 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 11059032 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 893075 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.459055 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6772156 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 893587 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.578620 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459055 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16827638 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16827638 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 7030999 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7030999 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7030999 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7030999 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7030999 # number of overall hits -system.cpu1.icache.overall_hits::total 7030999 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 921880 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 921880 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 921880 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 921880 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 921880 # number of overall misses -system.cpu1.icache.overall_misses::total 921880 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7511609427 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7511609427 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7511609427 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7511609427 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7511609427 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7511609427 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7952879 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7952879 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7952879 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7952879 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7952879 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7952879 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115918 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.115918 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115918 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.115918 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115918 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.115918 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8148.142304 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8148.142304 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8148.142304 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8148.142304 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 16225073 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16225073 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6772156 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6772156 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6772156 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6772156 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6772156 # number of overall hits +system.cpu1.icache.overall_hits::total 6772156 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 893587 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 893587 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 893587 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 893587 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 893587 # number of overall misses +system.cpu1.icache.overall_misses::total 893587 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266352748 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7266352748 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7266352748 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7266352748 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7266352748 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7266352748 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7665743 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7665743 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7665743 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7665743 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7665743 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7665743 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116569 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.116569 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116569 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.116569 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116569 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.116569 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8131.667927 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8131.667927 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8131.667927 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8131.667927 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1870,362 +1879,362 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 921880 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 921880 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 921880 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 921880 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 921880 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 921880 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6126335573 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6126335573 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6126335573 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6126335573 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6126335573 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6126335573 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10451250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10451250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10451250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10451250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.115918 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.115918 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.115918 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6645.480510 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893587 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 893587 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 893587 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 893587 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 893587 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 893587 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923590752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923590752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923590752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5923590752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923590752 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5923590752 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116569 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.116569 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.116569 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.002830 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1617912 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1172300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2534 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2534 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 119069 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 160310 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84990 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41555 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86189 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 79780 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67226 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1843990 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 788213 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6991 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 54848 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2694042 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59007680 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25579748 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10764 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100400 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 84698592 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 851885 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2136582 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.360548 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.480160 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1582924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1137885 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2119 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2119 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 115746 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 150971 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85149 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 76810 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 64398 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787404 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 768912 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6948 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51790 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2615054 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57196928 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24920351 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10668 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 94516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 82222463 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 838516 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2085340 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.363825 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.481099 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1366242 63.95% 63.95% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 770340 36.05% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1326642 63.62% 63.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 758698 36.38% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2136582 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 806533923 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2085340 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 782793185 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80269000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78444000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1384243177 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1341767498 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 391135835 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 381370915 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4300499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4282497 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 29750249 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 28163996 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7297386 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43768 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7137149 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1402 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7065047 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40428 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914930 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1457 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2677 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 112390 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 731398 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2607 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105625 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724673 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85101 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15525.587179 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1172424 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100275 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.692087 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 79629 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15528.716598 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1138081 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 94994 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.980557 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5967.757550 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.503310 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.105046 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2342.307731 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7188.913541 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.364243 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001618 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142963 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.438776 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.947607 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10134 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5006 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6712 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3286 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6912.222509 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 24.793124 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.117245 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2315.760796 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6275.822923 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.421889 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001513 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.141343 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383046 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.947798 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10144 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5192 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6818 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3193 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2980 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1783 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.618530 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.305542 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 22015192 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 22015192 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24492 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2447 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1023306 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1050245 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 119069 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 119069 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1895 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1895 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 736 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 736 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 30109 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 30109 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24492 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2447 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1053415 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1080354 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24492 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2447 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1053415 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1080354 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 608 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 244 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 73509 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 74361 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28314 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28314 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22589 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22589 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32639 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32639 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 608 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 244 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 106148 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 107000 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 608 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 244 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 106148 # number of overall misses -system.cpu1.l2cache.overall_misses::total 107000 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13309748 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4879000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1671503870 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1689692618 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 534018919 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 534018919 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 443647551 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443647551 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 303500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 303500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1129954380 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1129954380 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13309748 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4879000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2801458250 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2819646998 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13309748 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4879000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2801458250 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2819646998 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25100 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2691 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1096815 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1124606 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 119069 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 119069 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 30209 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30209 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23325 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23325 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 62748 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62748 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 25100 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2691 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1159563 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1187354 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 25100 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2691 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1159563 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1187354 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090673 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067020 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.066122 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.937270 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937270 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968446 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968446 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.520160 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.520160 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090673 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091541 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.090116 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090673 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091541 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.090116 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19995.901639 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22738.764913 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22722.833448 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18860.596136 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18860.596136 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19639.981894 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19639.981894 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1854 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.619141 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.316895 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21374644 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21374644 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23037 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2415 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993214 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 1018666 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 115746 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 115746 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1782 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1782 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 772 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 772 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27747 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27747 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23037 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2415 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 1020961 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1046413 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23037 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2415 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 1020961 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1046413 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 592 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 252 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72082 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 72926 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28135 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28135 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22404 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22404 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32295 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32295 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 592 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 252 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 104377 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 105221 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 592 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 252 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 104377 # number of overall misses +system.cpu1.l2cache.overall_misses::total 105221 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13156500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5072997 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1619935379 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1638164876 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531136882 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 531136882 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440134565 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440134565 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 329000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 329000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1130691878 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1130691878 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13156500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5072997 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750627257 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2768856754 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13156500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5072997 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750627257 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2768856754 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23629 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2667 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065296 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1091592 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 115746 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 115746 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29917 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29917 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23176 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23176 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60042 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 60042 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23629 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2667 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 1125338 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1151634 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23629 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2667 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 1125338 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1151634 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.094488 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067664 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.066807 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.940435 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.940435 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.966690 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.966690 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537873 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537873 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.094488 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092752 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.091367 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.094488 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092752 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.091367 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20130.940476 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22473.507658 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22463.385843 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18878.154683 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18878.154683 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19645.356410 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19645.356410 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34619.761022 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34619.761022 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 26351.841103 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 26351.841103 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35011.360211 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35011.360211 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 26314.678192 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 26314.678192 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 4757 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 187 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 158 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.096257 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.107595 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 39442 # number of writebacks -system.cpu1.l2cache.writebacks::total 39442 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1735 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 1735 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 340 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 340 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2075 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 2075 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2075 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 2075 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 608 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 244 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 71774 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 72626 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 112390 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28314 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28314 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22589 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22589 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 32299 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 32299 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 608 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 244 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 104073 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 104925 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 608 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 244 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 104073 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 217315 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3171000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1134657222 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1146878474 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3172675528 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 408265220 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 408265220 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 310198725 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 310198725 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 254500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 254500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 858509328 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 858509328 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3171000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1993166550 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2005387802 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3171000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1993166550 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 5178063330 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 388960005 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 388960005 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 260468006 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 260468006 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 649428011 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 649428011 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.065439 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.064579 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 38299 # number of writebacks +system.cpu1.l2cache.writebacks::total 38299 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1547 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1547 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 321 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 321 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1868 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1868 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1868 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1868 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 592 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 252 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70535 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 71379 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 105624 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28135 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28135 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22404 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22404 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31974 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 31974 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 592 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 252 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102509 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 103353 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 592 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 252 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102509 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 208977 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3308997 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1095971987 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1108291484 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2952900698 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404207806 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404207806 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308121722 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308121722 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 273000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 273000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 864621339 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 864621339 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3308997 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960593326 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 1972912823 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3308997 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960593326 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4925813521 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316590752 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316590752 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186920002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186920002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503510754 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503510754 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066212 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065390 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.937270 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937270 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968446 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968446 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.514742 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.514742 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.088369 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.940435 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.940435 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.966690 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966690 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.532527 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.532527 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089745 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183025 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15808.749993 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15791.568777 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28229.162096 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14419.199689 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14419.199689 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13732.291159 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13732.291159 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181461 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15537.988048 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15526.856414 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27956.720991 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14366.724933 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14366.724933 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13752.978129 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13752.978129 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 26580.059073 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26580.059073 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19112.583293 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23827.454755 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27041.387971 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27041.387971 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19089.071657 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23571.079693 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2233,97 +2242,97 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 193696 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.979850 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7249545 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 194043 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.360508 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 107387908500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 469.979850 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.917929 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.917929 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 347 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 67 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.677734 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15373685 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15373685 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3863317 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3863317 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 3184030 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3184030 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 91016 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 91016 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 71184 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71184 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 7047347 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 7047347 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 7047347 # number of overall hits -system.cpu1.dcache.overall_hits::total 7047347 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 184713 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 184713 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 145139 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145139 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5273 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5273 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23325 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23325 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 329852 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 329852 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 329852 # number of overall misses -system.cpu1.dcache.overall_misses::total 329852 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2791622179 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2791622179 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3393821873 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3393821873 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 95816000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 95816000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 543674761 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 543674761 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 324500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 324500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 6185444052 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6185444052 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 6185444052 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6185444052 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 4048030 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4048030 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3329169 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3329169 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 96289 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96289 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 94509 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94509 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 7377199 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7377199 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 7377199 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7377199 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045630 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045630 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043596 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043596 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054762 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054762 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.246802 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246802 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044712 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044712 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044712 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044712 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15113.295648 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15113.295648 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23383.252420 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23383.252420 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18171.060118 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18171.060118 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23308.671426 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23308.671426 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 188481 # number of replacements +system.cpu1.dcache.tags.tagsinuse 475.009191 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6997616 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 188846 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.054616 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 475.009191 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927752 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.927752 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14853075 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14853075 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 3751603 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3751603 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051213 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3051213 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88863 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88863 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69198 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 69198 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 6802816 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6802816 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 6802816 # number of overall hits +system.cpu1.dcache.overall_hits::total 6802816 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 182008 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 182008 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 139434 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 139434 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5163 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5163 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23176 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23176 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 321442 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 321442 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 321442 # number of overall misses +system.cpu1.dcache.overall_misses::total 321442 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2744686684 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2744686684 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3345931004 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3345931004 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93833250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 93833250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540125753 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 540125753 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 353500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 353500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 6090617688 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6090617688 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 6090617688 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6090617688 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3933611 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3933611 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3190647 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3190647 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94026 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 94026 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92374 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92374 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 7124258 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7124258 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 7124258 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7124258 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046270 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.046270 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043701 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.043701 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054910 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054910 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250893 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250893 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045119 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.045119 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045119 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.045119 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15080.033207 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15080.033207 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23996.521681 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23996.521681 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18174.171993 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18174.171993 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23305.391483 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23305.391483 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18752.179923 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18752.179923 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18947.796766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18947.796766 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2332,74 +2341,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119069 # number of writebacks -system.cpu1.dcache.writebacks::total 119069 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15047 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15047 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 52186 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52186 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 67233 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 67233 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 67233 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 67233 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 169666 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 169666 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 92953 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92953 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5273 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5273 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23325 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23325 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 262619 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 262619 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 262619 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 262619 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2247676267 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247676267 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2022089921 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2022089921 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 85260000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85260000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 495802239 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495802239 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 310500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 310500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4269766188 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4269766188 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4269766188 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4269766188 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 405245745 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 405245745 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 279561993 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279561993 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 684807738 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 684807738 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.041913 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041913 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027921 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027921 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054762 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054762 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.246802 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246802 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.035599 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035599 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13247.652841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13247.652841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 21753.896281 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21753.896281 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16169.163664 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16169.163664 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21256.258907 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21256.258907 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 115746 # number of writebacks +system.cpu1.dcache.writebacks::total 115746 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15462 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15462 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49475 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 49475 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64937 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 64937 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64937 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 64937 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166546 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166546 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89959 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 89959 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5163 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5163 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23176 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23176 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256505 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 256505 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256505 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256505 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202025254 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202025254 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2000006836 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2000006836 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83498750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83498750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492542247 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492542247 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 337500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 337500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4202032090 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4202032090 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4202032090 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4202032090 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329591498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329591498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202938498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202938498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532529996 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532529996 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042339 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042339 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028195 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028195 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054910 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054910 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250893 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250893 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.036004 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036004 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13221.724052 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13221.724052 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22232.426283 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22232.426283 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16172.525663 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16172.525663 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21252.254358 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21252.254358 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2407,58 +2416,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.485749 # Cycle average of tags in use +system.iocache.tags.replacements 36417 # number of replacements +system.iocache.tags.tagsinuse 0.992209 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 268964842000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.485749 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.905359 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.905359 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.992209 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062013 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062013 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328575 # Number of tag accesses -system.iocache.tags.data_accesses 328575 # Number of data accesses +system.iocache.tags.tag_accesses 328483 # Number of tag accesses +system.iocache.tags.data_accesses 328483 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31822377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31822377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31822377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31822377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31822377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31822377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 35 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 35 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31692627 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31692627 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31692627 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31692627 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31692627 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31692627 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36259 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36259 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000965 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000965 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124793.635294 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124793.635294 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124793.635294 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124793.635294 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 130422.333333 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130422.333333 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130422.333333 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130422.333333 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2467,34 +2476,34 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18561377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18561377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2257984064 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2257984064 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18561377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18561377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18561377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18561377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19056127 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19056127 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2259252335 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2259252335 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19056127 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19056127 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19056127 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19056127 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72789.713725 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72789.713725 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78420.275720 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78420.275720 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index 28bc9e108..9c1096f55 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout index c0a4743fb..89600f4c4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:01:02 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:27:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x4defb00 0x4defb00 + 0: system.cpu.isa: ISA system set to: 0x5580680 0x5580680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 @@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2852200332000 because m5_exit instruction encountered +Exiting @ tick 2852222670000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 06709bcae..69d9fc0b1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852200 # Number of seconds simulated -sim_ticks 2852200332000 # Number of ticks simulated -final_tick 2852200332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852223 # Number of seconds simulated +sim_ticks 2852222670000 # Number of ticks simulated +final_tick 2852222670000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169178 # Simulator instruction rate (inst/s) -host_op_rate 204545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4322499487 # Simulator tick rate (ticks/s) -host_mem_usage 558640 # Number of bytes of host memory used -host_seconds 659.85 # Real time elapsed on the host -sim_insts 111631963 # Number of instructions simulated -sim_ops 134968701 # Number of ops (including micro ops) simulated +host_inst_rate 166317 # Simulator instruction rate (inst/s) +host_op_rate 201081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4259610797 # Simulator tick rate (ticks/s) +host_mem_usage 558772 # Number of bytes of host memory used +host_seconds 669.60 # Real time elapsed on the host +sim_insts 111365458 # Number of instructions simulated +sim_ops 134642914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 6592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10875428 # Number of bytes read from this memory -system.physmem.bytes_read::total 10883108 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1665536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1665536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5669632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 6464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10896868 # Number of bytes read from this memory +system.physmem.bytes_read::total 10904484 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1667584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1667584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5681792 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8005492 # Number of bytes written to this memory +system.physmem.bytes_written::total 8017652 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 103 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 170448 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170568 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88588 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 101 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 170783 # Number of read requests responded to by this memory +system.physmem.num_reads::total 170902 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 88778 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129193 # Number of write requests responded to by this memory +system.physmem.num_writes::total 129383 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 2311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3812996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3815688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 583948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 583948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1987810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 812824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 2266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 67 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3820483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3823153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 584661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 584661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1992058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 812817 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2806778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1987810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 813160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3819140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6622466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170568 # Number of read requests accepted -system.physmem.writeReqs 129193 # Number of write requests accepted -system.physmem.readBursts 170568 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129193 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10907008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 8019264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10883108 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8005492 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4599 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10529 # Per bank write bursts -system.physmem.perBankRdBursts::1 10427 # Per bank write bursts -system.physmem.perBankRdBursts::2 10726 # Per bank write bursts -system.physmem.perBankRdBursts::3 10519 # Per bank write bursts -system.physmem.perBankRdBursts::4 13519 # Per bank write bursts -system.physmem.perBankRdBursts::5 10191 # Per bank write bursts -system.physmem.perBankRdBursts::6 11164 # Per bank write bursts -system.physmem.perBankRdBursts::7 10885 # Per bank write bursts -system.physmem.perBankRdBursts::8 10359 # Per bank write bursts -system.physmem.perBankRdBursts::9 10882 # Per bank write bursts -system.physmem.perBankRdBursts::10 10112 # Per bank write bursts -system.physmem.perBankRdBursts::11 9441 # Per bank write bursts -system.physmem.perBankRdBursts::12 10326 # Per bank write bursts -system.physmem.perBankRdBursts::13 11222 # Per bank write bursts -system.physmem.perBankRdBursts::14 10031 # Per bank write bursts -system.physmem.perBankRdBursts::15 10089 # Per bank write bursts -system.physmem.perBankWrBursts::0 7745 # Per bank write bursts -system.physmem.perBankWrBursts::1 7827 # Per bank write bursts -system.physmem.perBankWrBursts::2 8372 # Per bank write bursts -system.physmem.perBankWrBursts::3 8091 # Per bank write bursts -system.physmem.perBankWrBursts::4 7875 # Per bank write bursts -system.physmem.perBankWrBursts::5 7401 # Per bank write bursts -system.physmem.perBankWrBursts::6 8203 # Per bank write bursts -system.physmem.perBankWrBursts::7 8042 # Per bank write bursts -system.physmem.perBankWrBursts::8 7896 # Per bank write bursts -system.physmem.perBankWrBursts::9 8173 # Per bank write bursts -system.physmem.perBankWrBursts::10 7527 # Per bank write bursts -system.physmem.perBankWrBursts::11 7251 # Per bank write bursts -system.physmem.perBankWrBursts::12 7760 # Per bank write bursts -system.physmem.perBankWrBursts::13 8405 # Per bank write bursts -system.physmem.perBankWrBursts::14 7350 # Per bank write bursts -system.physmem.perBankWrBursts::15 7383 # Per bank write bursts +system.physmem.bw_write::total 2811019 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1992058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 813154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 67 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3826627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6634172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170902 # Number of read requests accepted +system.physmem.writeReqs 129383 # Number of write requests accepted +system.physmem.readBursts 170902 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129383 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10927488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue +system.physmem.bytesWritten 8031232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10904484 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8017652 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4593 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10513 # Per bank write bursts +system.physmem.perBankRdBursts::1 10240 # Per bank write bursts +system.physmem.perBankRdBursts::2 10772 # Per bank write bursts +system.physmem.perBankRdBursts::3 10550 # Per bank write bursts +system.physmem.perBankRdBursts::4 13501 # Per bank write bursts +system.physmem.perBankRdBursts::5 10124 # Per bank write bursts +system.physmem.perBankRdBursts::6 11177 # Per bank write bursts +system.physmem.perBankRdBursts::7 10891 # Per bank write bursts +system.physmem.perBankRdBursts::8 10227 # Per bank write bursts +system.physmem.perBankRdBursts::9 10892 # Per bank write bursts +system.physmem.perBankRdBursts::10 10093 # Per bank write bursts +system.physmem.perBankRdBursts::11 9609 # Per bank write bursts +system.physmem.perBankRdBursts::12 10331 # Per bank write bursts +system.physmem.perBankRdBursts::13 11217 # Per bank write bursts +system.physmem.perBankRdBursts::14 10288 # Per bank write bursts +system.physmem.perBankRdBursts::15 10317 # Per bank write bursts +system.physmem.perBankWrBursts::0 7730 # Per bank write bursts +system.physmem.perBankWrBursts::1 7662 # Per bank write bursts +system.physmem.perBankWrBursts::2 8408 # Per bank write bursts +system.physmem.perBankWrBursts::3 8127 # Per bank write bursts +system.physmem.perBankWrBursts::4 7860 # Per bank write bursts +system.physmem.perBankWrBursts::5 7340 # Per bank write bursts +system.physmem.perBankWrBursts::6 8206 # Per bank write bursts +system.physmem.perBankWrBursts::7 8039 # Per bank write bursts +system.physmem.perBankWrBursts::8 7784 # Per bank write bursts +system.physmem.perBankWrBursts::9 8077 # Per bank write bursts +system.physmem.perBankWrBursts::10 7518 # Per bank write bursts +system.physmem.perBankWrBursts::11 7421 # Per bank write bursts +system.physmem.perBankWrBursts::12 7767 # Per bank write bursts +system.physmem.perBankWrBursts::13 8402 # Per bank write bursts +system.physmem.perBankWrBursts::14 7544 # Per bank write bursts +system.physmem.perBankWrBursts::15 7603 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2852199845000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 2852222186000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 170013 # Read request sizes (log2) +system.physmem.readPktSize::6 170347 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124812 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125002 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -158,220 +158,219 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6597 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60576 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.437401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.644234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.251922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22086 36.46% 36.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14485 23.91% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6694 11.05% 71.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3534 5.83% 77.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2501 4.13% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1624 2.68% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1087 1.79% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7503 12.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60576 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6291 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.088221 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 577.877413 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6289 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.666217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.364711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.290387 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22259 36.59% 36.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14417 23.70% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6771 11.13% 71.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3560 5.85% 77.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2627 4.32% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1563 2.57% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1081 1.78% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1081 1.78% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7471 12.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60830 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6311 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.051339 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 576.967682 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6309 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6291 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6291 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.917501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.380102 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.942111 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5514 87.65% 87.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 46 0.73% 88.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.49% 88.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 207 3.29% 92.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 183 2.91% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 14 0.22% 95.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.27% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.27% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 30 0.48% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.11% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 154 2.45% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.33% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 6 0.10% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6311 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.884012 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.375867 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.802704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5533 87.67% 87.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 35 0.55% 88.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.48% 88.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 215 3.41% 92.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 199 3.15% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.24% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.27% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.30% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.30% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.10% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 155 2.46% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.10% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.19% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.11% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.08% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6291 # Writes before turning the bus around for reads -system.physmem.totQLat 1680738000 # Total ticks spent queuing -system.physmem.totMemAccLat 4876150500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 852110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9862.21 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6311 # Writes before turning the bus around for reads +system.physmem.totQLat 1715938250 # Total ticks spent queuing +system.physmem.totMemAccLat 4917350750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 853710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10049.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28612.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28799.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 140727 # Number of row buffer hits during reads -system.physmem.writeRowHits 94419 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.34 # Row buffer hit rate for writes -system.physmem.avgGap 9514913.03 # Average gap between requests -system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2713226080000 # Time in different power states -system.physmem.memoryStateTime::REF 95241120000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.21 # Average write queue length when enqueuing +system.physmem.readRowHits 140944 # Number of row buffer hits during reads +system.physmem.writeRowHits 94455 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes +system.physmem.avgGap 9498383.82 # Average gap between requests +system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2712510439500 # Time in different power states +system.physmem.memoryStateTime::REF 95241900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 43733042000 # Time in different power states +system.physmem.memoryStateTime::ACT 44470242000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234125640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127747125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 686088000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 643195800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 411842880 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 400107600 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 186291630720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 186291630720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82872817560 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 82165704345 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1638622788000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1639243062750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1909247039925 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1909089659010 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.395204 # Core power per rank (mW) -system.physmem.averagePower::1 669.340025 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 180 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 180 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 180 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 180 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 180 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 180 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 71824 # Transaction distribution -system.membus.trans_dist::ReadResp 71824 # Transaction distribution +system.physmem.actEnergy::0 234798480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 225076320 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 128114250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122809500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 684590400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 647189400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 410650560 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 402511680 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 186293156400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 186293156400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 83147145165 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 82654300080 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1638396165000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1638828485250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1909294620255 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1909173528630 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.406404 # Core power per rank (mW) +system.physmem.averagePower::1 669.363949 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 71842 # Transaction distribution +system.membus.trans_dist::ReadResp 71842 # Transaction distribution system.membus.trans_dist::WriteReq 27607 # Transaction distribution system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 88588 # Transaction distribution +system.membus.trans_dist::Writeback 88778 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4597 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution -system.membus.trans_dist::ReadExReq 129554 # Transaction distribution -system.membus.trans_dist::ReadExResp 129554 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution +system.membus.trans_dist::ReadExReq 129869 # Transaction distribution +system.membus.trans_dist::ReadExResp 129869 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556132 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 627985 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 628829 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16569304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16733149 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16602840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16766621 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19052445 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19085917 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 296652 # Request fanout histogram +system.membus.snoop_fanout::samples 297178 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 296652 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 297178 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 296652 # Request fanout histogram -system.membus.reqLayer0.occupancy 87220000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 297178 # Request fanout histogram +system.membus.reqLayer0.occupancy 87065000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1713500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1712000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1383760500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1386132250 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1715299901 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1718569157 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38332500 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38335749 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -504,24 +503,24 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326584849 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36805500 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36809251 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 30761849 # Number of BP lookups -system.cpu.branchPred.condPredicted 16759561 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2494541 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18376022 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13249221 # Number of BTB hits +system.cpu.branchPred.lookups 30769128 # Number of BP lookups +system.cpu.branchPred.condPredicted 16730733 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2480939 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18423796 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13205412 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.100594 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7712174 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1491943 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.675848 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7765211 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1476374 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -545,25 +544,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24631139 # DTB read hits -system.cpu.dtb.read_misses 58263 # DTB read misses -system.cpu.dtb.write_hits 19400231 # DTB write hits -system.cpu.dtb.write_misses 6058 # DTB write misses +system.cpu.dtb.read_hits 24572928 # DTB read hits +system.cpu.dtb.read_misses 58429 # DTB read misses +system.cpu.dtb.write_hits 19368405 # DTB write hits +system.cpu.dtb.write_misses 5913 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4344 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1249 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1245 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 740 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24689402 # DTB read accesses -system.cpu.dtb.write_accesses 19406289 # DTB write accesses +system.cpu.dtb.perms_faults 752 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24631357 # DTB read accesses +system.cpu.dtb.write_accesses 19374318 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44031370 # DTB hits -system.cpu.dtb.misses 64321 # DTB misses -system.cpu.dtb.accesses 44095691 # DTB accesses +system.cpu.dtb.hits 43941333 # DTB hits +system.cpu.dtb.misses 64342 # DTB misses +system.cpu.dtb.accesses 44005675 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -585,8 +584,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 57062578 # ITB inst hits -system.cpu.itb.inst_misses 5424 # ITB inst misses +system.cpu.itb.inst_hits 57038768 # ITB inst hits +system.cpu.itb.inst_misses 5411 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -595,83 +594,83 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2982 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2977 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8630 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8664 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57068002 # ITB inst accesses -system.cpu.itb.hits 57062578 # DTB hits -system.cpu.itb.misses 5424 # DTB misses -system.cpu.itb.accesses 57068002 # DTB accesses -system.cpu.numCycles 313219225 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57044179 # ITB inst accesses +system.cpu.itb.hits 57038768 # DTB hits +system.cpu.itb.misses 5411 # DTB misses +system.cpu.itb.accesses 57044179 # DTB accesses +system.cpu.numCycles 313347638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111631963 # Number of instructions committed -system.cpu.committedOps 134968701 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7932752 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111365458 # Number of instructions committed +system.cpu.committedOps 134642914 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7897593 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5391228164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.805820 # CPI: cycles per instruction -system.cpu.ipc 0.356402 # IPC: instructions per cycle +system.cpu.quiesceCycles 5391144295 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.813688 # CPI: cycles per instruction +system.cpu.ipc 0.355405 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 224159041 # Number of cycles that the object actually ticked -system.cpu.idleCycles 89060184 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 2896816 # number of replacements -system.cpu.icache.tags.tagsinuse 511.427908 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54156207 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897328 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.691776 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15213008250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.427908 # Average occupied blocks per requestor +system.cpu.tickCycles 224151816 # Number of cycles that the object actually ticked +system.cpu.idleCycles 89195822 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 2897350 # number of replacements +system.cpu.icache.tags.tagsinuse 511.427915 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54131849 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897862 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.679926 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15213015250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.427915 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59950884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59950884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54156207 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54156207 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54156207 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54156207 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54156207 # number of overall hits -system.cpu.icache.overall_hits::total 54156207 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897339 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897339 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897339 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2897339 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2897339 # number of overall misses -system.cpu.icache.overall_misses::total 2897339 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39126605503 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39126605503 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39126605503 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39126605503 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39126605503 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39126605503 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57053546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57053546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57053546 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57053546 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57053546 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57053546 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050783 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050783 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.324314 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13504.324314 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13504.324314 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13504.324314 # average overall miss latency +system.cpu.icache.tags.tag_accesses 59927594 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59927594 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54131849 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54131849 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54131849 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54131849 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54131849 # number of overall hits +system.cpu.icache.overall_hits::total 54131849 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2897873 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2897873 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2897873 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2897873 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2897873 # number of overall misses +system.cpu.icache.overall_misses::total 2897873 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39140139756 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39140139756 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39140139756 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39140139756 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39140139756 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39140139756 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57029722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57029722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57029722 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57029722 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57029722 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57029722 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050813 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050813 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050813 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050813 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050813 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050813 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.506240 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.506240 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.506240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.506240 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,225 +679,225 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33322439497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33322439497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33322439497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33322439497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33322439497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33322439497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222173750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222173750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222173750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 222173750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050783 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050783 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050783 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11501.049583 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11501.049583 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897873 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897873 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897873 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2897873 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2897873 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2897873 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33334905244 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33334905244 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33334905244 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33334905244 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33334905244 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33334905244 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222062750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222062750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222062750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 222062750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050813 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050813 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050813 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.231937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.231937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3575425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3575329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3575187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3575091 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697864 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2821 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295691 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5800652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2504517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8476707 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185619904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98723549 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276412 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284638757 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 60515 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4573888 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088927 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295755 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295755 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801712 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2503299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 155961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8476265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185653696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98670557 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284619693 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 60174 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4573282 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.007974 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088941 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4537427 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36461 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 4536814 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36468 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4573888 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3011299661 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4573282 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3010555155 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4355950753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4356749506 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1340010456 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1339516197 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10527250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10501000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 87188750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 86895250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 97184 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65075.712435 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4041226 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162444 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.877656 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 93442219500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47462.018914 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 55.401726 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009455 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 17558.282340 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.724213 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000845 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 97514 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65073.344541 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4041263 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162774 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.827448 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 93462601500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 47542.577135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 54.389093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 17476.368811 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.725442 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000830 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.267918 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992977 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65213 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55798 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995071 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36570721 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36570721 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69000 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4721 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 3405800 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3479521 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 697864 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 697864 # number of Writeback hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266668 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65216 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55801 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 36568997 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 36568997 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68967 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4789 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 3405854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3479610 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 697424 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 697424 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.inst 45 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 164314 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164314 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69000 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4721 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 3570114 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3643835 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69000 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 4721 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 3570114 # number of overall hits -system.cpu.l2cache.overall_hits::total 3643835 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 103 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 37510 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 37615 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2774 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2774 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.inst 164068 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164068 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 68967 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 4789 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 3569922 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3643678 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 68967 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 4789 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 3569922 # number of overall hits +system.cpu.l2cache.overall_hits::total 3643678 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 101 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 37534 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37638 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2773 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2773 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 131377 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131377 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 168887 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168992 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 103 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 168887 # number of overall misses -system.cpu.l2cache.overall_misses::total 168992 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7796000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 163250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2760094000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2768053250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 998957 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 998957 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9221968427 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9221968427 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7796000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 163250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11982062427 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11990021677 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7796000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 163250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11982062427 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11990021677 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4723 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443310 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 3517136 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 697864 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 697864 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2819 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2819 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.inst 131687 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131687 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 101 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 169221 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 169325 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 101 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 169221 # number of overall misses +system.cpu.l2cache.overall_misses::total 169325 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7803500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 223500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2773793750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2781820750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 1024956 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1024956 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46998 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9263576682 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9263576682 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7803500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 223500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12037370432 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12045397432 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7803500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 223500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12037370432 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12045397432 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4792 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443388 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3517248 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 697424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 697424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2818 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2818 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295691 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295691 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69103 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 4723 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 3739001 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 3812827 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69103 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 4723 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3739001 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 3812827 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001491 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000423 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010894 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.010695 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984037 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984037 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295755 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295755 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69068 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 4792 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3739143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3813003 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69068 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 4792 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3739143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3813003 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001462 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000626 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010900 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.010701 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984031 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984031 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.444305 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.444305 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001491 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000423 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045169 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.044322 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001491 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000423 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045169 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.044322 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 75689.320388 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73582.884564 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73589.080154 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 360.114275 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 360.114275 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23249 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70194.694863 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70194.694863 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70950.232419 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70950.232419 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.445257 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.445257 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045257 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.044407 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045257 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.044407 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77262.376238 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73900.829914 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73909.898241 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 369.619906 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 369.619906 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23499 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70345.415128 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70345.415128 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71137.737676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71137.737676 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -907,92 +906,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88588 # number of writebacks -system.cpu.l2cache.writebacks::total 88588 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 103 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37345 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37450 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2774 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2774 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 88778 # number of writebacks +system.cpu.l2cache.writebacks::total 88778 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 168 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 168 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 168 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 168 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37366 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37470 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2773 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2773 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131377 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131377 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 168722 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168827 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 168722 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168827 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6531000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 138750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2281377500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2288047250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27781774 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27781774 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131687 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131687 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 169053 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 101 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 169053 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6559500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 187500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2294945750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2301692750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27763773 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27763773 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 20002 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7543603073 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7543603073 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6531000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 138750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9824980573 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9831650323 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6531000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 138750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9824980573 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9831650323 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545609250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545609250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106796000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106796000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652405250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652405250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010846 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010648 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984037 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984037 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7581141318 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7581141318 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6559500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 187500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9876087068 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9882834068 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6559500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 187500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9876087068 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9882834068 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545310750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545310750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106655500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106655500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9651966250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9651966250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010653 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984031 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.444305 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444305 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044279 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044279 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 69375 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61089.235507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61096.054740 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.059120 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.059120 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445257 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445257 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044363 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044363 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61418.020393 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61427.615426 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.179228 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.179228 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57419.510820 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57419.510820 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57569.398027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57569.398027 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1000,94 +999,94 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 841153 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.953397 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42536757 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 841665 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.538821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 279806250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953397 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 840767 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.953448 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42450068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 841279 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.458965 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953448 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175509435 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175509435 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 23374617 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23374617 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 18241170 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18241170 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457775 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457775 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 460281 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 41615787 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41615787 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 41615787 # number of overall hits -system.cpu.dcache.overall_hits::total 41615787 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 583566 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 583566 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 541192 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541192 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8333 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8333 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 175160699 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175160699 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 23317429 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23317429 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 18211581 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18211581 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457826 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457826 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 460320 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460320 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 41529010 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41529010 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 41529010 # number of overall hits +system.cpu.dcache.overall_hits::total 41529010 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 583115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 583115 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 541259 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 541259 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8317 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8317 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 1124758 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1124758 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1124758 # number of overall misses -system.cpu.dcache.overall_misses::total 1124758 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8637456588 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8637456588 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21531074313 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21531074313 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117993250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 117993250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 30168530901 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30168530901 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 30168530901 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30168530901 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23958183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23958183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 18782362 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18782362 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466108 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466108 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460283 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42740545 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42740545 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42740545 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42740545 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024358 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024358 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028814 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028814 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017878 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017878 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.inst 1124374 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1124374 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1124374 # number of overall misses +system.cpu.dcache.overall_misses::total 1124374 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8642422585 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8642422585 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588022799 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21588022799 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117987000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117987000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 53002 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 30230445384 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30230445384 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 30230445384 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30230445384 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23900544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23900544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 18752840 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18752840 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466143 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466143 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460322 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460322 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 42653384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42653384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42653384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42653384 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024398 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024398 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028863 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028863 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017842 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017842 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.026316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.026316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14801.164886 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14801.164886 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39784.539152 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39784.539152 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.756390 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.756390 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26822.241674 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26822.241674 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.026361 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026361 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.026361 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026361 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14821.128911 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14821.128911 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39884.829257 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39884.829257 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14186.245040 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14186.245040 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26886.467834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26886.467834 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1096,70 +1095,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 697864 # number of writebacks -system.cpu.dcache.writebacks::total 697864 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45894 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45894 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242687 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 242687 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 288581 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 288581 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 288581 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 288581 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537672 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 537672 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298505 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298505 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8333 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8333 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 697424 # number of writebacks +system.cpu.dcache.writebacks::total 697424 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45879 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45879 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242691 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 242691 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 288570 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 288570 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 288570 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 288570 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537236 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 537236 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298568 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298568 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8317 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8317 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 836177 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 836177 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 836177 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 836177 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6873353393 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6873353393 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11227746403 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11227746403 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101298750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101298750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18101099796 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18101099796 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18101099796 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18101099796 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791247750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791247750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439329000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439329000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230576750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230576750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022442 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022442 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015893 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015893 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017878 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017878 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 835804 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 835804 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 835804 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 835804 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6874982646 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6874982646 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11266915159 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266915159 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101324000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101324000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18141897805 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18141897805 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18141897805 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18141897805 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791016000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791016000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439188000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439188000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015921 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017842 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017842 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019564 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019564 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.543486 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.543486 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37613.260759 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37613.260759 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.336253 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.336253 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019595 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019595 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12796.950774 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12796.950774 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37736.512818 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37736.512818 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12182.758206 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12182.758206 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1168,14 +1167,14 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031370 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031475 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 269945589000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031370 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031475 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064467 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064467 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1189,12 +1188,12 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 27970377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 27970377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 27970377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 27970377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 27970377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 27970377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 27954377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 27954377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 27954377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 27954377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 27954377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 27954377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1209,12 +1208,12 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119531.525641 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119531.525641 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119531.525641 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119531.525641 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 119463.149573 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119463.149573 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119463.149573 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119463.149573 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1229,28 +1228,28 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15801377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15801377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2215530472 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2215530472 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15801377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15801377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15801377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15801377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15785377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15785377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2212496723 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2212496723 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15785377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15785377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15785377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15785377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67527.252137 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67527.252137 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67458.876068 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67458.876068 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index c9ee24d0f..9621b86d6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index d913c3f34..44bde2ec3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -32,7 +32,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] -warn: 81667444500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000 +warn: 81667038500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000 warn: Returning zero for read from miscreg pmcr warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index c5b41115c..f4b480e9e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:12:13 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:29:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.checker.isa: ISA system set to: 0x59c2b00 0x59c2b00 - 0: system.cpu.isa: ISA system set to: 0x59c2b00 0x59c2b00 + 0: system.cpu.checker.isa: ISA system set to: 0x4985680 0x4985680 + 0: system.cpu.isa: ISA system set to: 0x4985680 0x4985680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 @@ -44,4 +44,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2826845674500 because m5_exit instruction encountered +Exiting @ tick 2826844351500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 2f04b9368..b1bf82ddf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826846 # Number of seconds simulated -sim_ticks 2826845674500 # Number of ticks simulated -final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826844 # Number of seconds simulated +sim_ticks 2826844351500 # Number of ticks simulated +final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73722 # Simulator instruction rate (inst/s) -host_op_rate 89421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1841455705 # Simulator tick rate (ticks/s) -host_mem_usage 559660 # Number of bytes of host memory used -host_seconds 1535.11 # Real time elapsed on the host -sim_insts 113172343 # Number of instructions simulated -sim_ops 137271263 # Number of ops (including micro ops) simulated +host_inst_rate 73855 # Simulator instruction rate (inst/s) +host_op_rate 89582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1844239732 # Simulator tick rate (ticks/s) +host_mem_usage 559768 # Number of bytes of host memory used +host_seconds 1532.80 # Real time elapsed on the host +sim_insts 113205077 # Number of instructions simulated +sim_ops 137311743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory -system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory +system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory +system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory -system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory +system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory +system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 172183 # Number of read requests accepted -system.physmem.writeReqs 131246 # Number of write requests accepted -system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 172165 # Number of read requests accepted +system.physmem.writeReqs 131231 # Number of write requests accepted +system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10992 # Per bank write bursts +system.physmem.perBankRdBursts::0 10989 # Per bank write bursts system.physmem.perBankRdBursts::1 10130 # Per bank write bursts -system.physmem.perBankRdBursts::2 11200 # Per bank write bursts -system.physmem.perBankRdBursts::3 11425 # Per bank write bursts +system.physmem.perBankRdBursts::2 11201 # Per bank write bursts +system.physmem.perBankRdBursts::3 11419 # Per bank write bursts system.physmem.perBankRdBursts::4 13122 # Per bank write bursts -system.physmem.perBankRdBursts::5 10553 # Per bank write bursts -system.physmem.perBankRdBursts::6 11175 # Per bank write bursts -system.physmem.perBankRdBursts::7 11538 # Per bank write bursts -system.physmem.perBankRdBursts::8 10354 # Per bank write bursts -system.physmem.perBankRdBursts::9 11059 # Per bank write bursts -system.physmem.perBankRdBursts::10 10499 # Per bank write bursts +system.physmem.perBankRdBursts::5 10546 # Per bank write bursts +system.physmem.perBankRdBursts::6 11171 # Per bank write bursts +system.physmem.perBankRdBursts::7 11539 # Per bank write bursts +system.physmem.perBankRdBursts::8 10356 # Per bank write bursts +system.physmem.perBankRdBursts::9 11055 # Per bank write bursts +system.physmem.perBankRdBursts::10 10496 # Per bank write bursts system.physmem.perBankRdBursts::11 9259 # Per bank write bursts system.physmem.perBankRdBursts::12 10183 # Per bank write bursts system.physmem.perBankRdBursts::13 10761 # Per bank write bursts system.physmem.perBankRdBursts::14 10049 # Per bank write bursts -system.physmem.perBankRdBursts::15 9748 # Per bank write bursts +system.physmem.perBankRdBursts::15 9745 # Per bank write bursts system.physmem.perBankWrBursts::0 8312 # Per bank write bursts system.physmem.perBankWrBursts::1 7765 # Per bank write bursts system.physmem.perBankWrBursts::2 8704 # Per bank write bursts -system.physmem.perBankWrBursts::3 8608 # Per bank write bursts +system.physmem.perBankWrBursts::3 8604 # Per bank write bursts system.physmem.perBankWrBursts::4 7611 # Per bank write bursts -system.physmem.perBankWrBursts::5 7956 # Per bank write bursts -system.physmem.perBankWrBursts::6 8259 # Per bank write bursts +system.physmem.perBankWrBursts::5 7949 # Per bank write bursts +system.physmem.perBankWrBursts::6 8258 # Per bank write bursts system.physmem.perBankWrBursts::7 8579 # Per bank write bursts -system.physmem.perBankWrBursts::8 7842 # Per bank write bursts -system.physmem.perBankWrBursts::9 8532 # Per bank write bursts -system.physmem.perBankWrBursts::10 7844 # Per bank write bursts +system.physmem.perBankWrBursts::8 7843 # Per bank write bursts +system.physmem.perBankWrBursts::9 8531 # Per bank write bursts +system.physmem.perBankWrBursts::10 7842 # Per bank write bursts system.physmem.perBankWrBursts::11 6872 # Per bank write bursts system.physmem.perBankWrBursts::12 7611 # Per bank write bursts system.physmem.perBankWrBursts::13 8198 # Per bank write bursts system.physmem.perBankWrBursts::14 7543 # Per bank write bursts -system.physmem.perBankWrBursts::15 7119 # Per bank write bursts +system.physmem.perBankWrBursts::15 7118 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2826845408500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 2826844140500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168635 # Read request sizes (log2) +system.physmem.readPktSize::6 168617 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126865 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126850 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -162,116 +162,118 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62171 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.209036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.794963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.700925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23473 37.76% 37.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14721 23.68% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6339 10.20% 71.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3681 5.92% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2625 4.22% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1528 2.46% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1121 1.80% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1145 1.84% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.317098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads -system.physmem.totQLat 2068507750 # Total ticks spent queuing -system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads +system.physmem.totQLat 2071957750 # Total ticks spent queuing +system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s @@ -280,36 +282,36 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing -system.physmem.readRowHits 142034 # Number of row buffer hits during reads -system.physmem.writeRowHits 95196 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes -system.physmem.avgGap 9316332.35 # Average gap between requests -system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states -system.physmem.memoryStateTime::REF 94394560000 # Time in different power states +system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing +system.physmem.readRowHits 141999 # Number of row buffer hits during reads +system.physmem.writeRowHits 95218 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes +system.physmem.avgGap 9317341.50 # Average gap between requests +system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states +system.physmem.memoryStateTime::REF 94394300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states +system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.338580 # Core power per rank (mW) -system.physmem.averagePower::1 669.240432 # Core power per rank (mW) +system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.335912 # Core power per rank (mW) +system.physmem.averagePower::1 669.239814 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory @@ -322,57 +324,57 @@ system.realview.nvmem.bw_inst_read::cpu.inst 45 system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 67851 # Transaction distribution -system.membus.trans_dist::ReadResp 67850 # Transaction distribution +system.membus.trans_dist::ReadReq 67834 # Transaction distribution +system.membus.trans_dist::ReadResp 67833 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 90641 # Transaction distribution +system.membus.trans_dist::Writeback 90626 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135128 # Transaction distribution -system.membus.trans_dist::ReadExResp 135128 # Transaction distribution +system.membus.trans_dist::ReadExReq 135127 # Transaction distribution +system.membus.trans_dist::ReadExResp 135127 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 205 # Total snoops (count) -system.membus.snoop_fanout::samples 300256 # Request fanout histogram +system.membus.snoop_fanout::samples 300222 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 300256 # Request fanout histogram -system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 300222 # Request fanout histogram +system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -413,9 +415,8 @@ system.cf0.dma_write_bytes 2318336 # Nu system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59035 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -506,24 +507,24 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46931803 # Number of BP lookups -system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits +system.cpu.branchPred.lookups 46964481 # Number of BP lookups +system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -547,9 +548,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24593793 # DTB read hits -system.cpu.checker.dtb.read_misses 8242 # DTB read misses -system.cpu.checker.dtb.write_hits 19641565 # DTB write hits +system.cpu.checker.dtb.read_hits 24601451 # DTB read hits +system.cpu.checker.dtb.read_misses 8241 # DTB read misses +system.cpu.checker.dtb.write_hits 19645361 # DTB write hits system.cpu.checker.dtb.write_misses 1441 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -560,12 +561,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24602035 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19643006 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24609692 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19646802 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44235358 # DTB hits -system.cpu.checker.dtb.misses 9683 # DTB misses -system.cpu.checker.dtb.accesses 44245041 # DTB accesses +system.cpu.checker.dtb.hits 44246812 # DTB hits +system.cpu.checker.dtb.misses 9682 # DTB misses +system.cpu.checker.dtb.accesses 44256494 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -587,7 +588,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 115874779 # ITB inst hits +system.cpu.checker.itb.inst_hits 115909457 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -604,11 +605,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115879605 # ITB inst accesses -system.cpu.checker.itb.hits 115874779 # DTB hits +system.cpu.checker.itb.inst_accesses 115914283 # ITB inst accesses +system.cpu.checker.itb.hits 115909457 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115879605 # DTB accesses -system.cpu.checker.numCycles 139125744 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115914283 # DTB accesses +system.cpu.checker.numCycles 139168167 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -634,10 +635,10 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25464394 # DTB read hits -system.cpu.dtb.read_misses 60419 # DTB read misses -system.cpu.dtb.write_hits 19915991 # DTB write hits -system.cpu.dtb.write_misses 9380 # DTB write misses +system.cpu.dtb.read_hits 25471928 # DTB read hits +system.cpu.dtb.read_misses 60410 # DTB read misses +system.cpu.dtb.write_hits 19919780 # DTB write hits +system.cpu.dtb.write_misses 9388 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID @@ -646,13 +647,13 @@ system.cpu.dtb.flush_entries 4324 # Nu system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25524813 # DTB read accesses -system.cpu.dtb.write_accesses 19925371 # DTB write accesses +system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25532338 # DTB read accesses +system.cpu.dtb.write_accesses 19929168 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45380385 # DTB hits -system.cpu.dtb.misses 69799 # DTB misses -system.cpu.dtb.accesses 45450184 # DTB accesses +system.cpu.dtb.hits 45391708 # DTB hits +system.cpu.dtb.misses 69798 # DTB misses +system.cpu.dtb.accesses 45461506 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -674,8 +675,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66292387 # ITB inst hits -system.cpu.itb.inst_misses 11931 # ITB inst misses +system.cpu.itb.inst_hits 66240861 # ITB inst hits +system.cpu.itb.inst_misses 11936 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -688,94 +689,94 @@ system.cpu.itb.flush_entries 3095 # Nu system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66304318 # ITB inst accesses -system.cpu.itb.hits 66292387 # DTB hits -system.cpu.itb.misses 11931 # DTB misses -system.cpu.itb.accesses 66304318 # DTB accesses -system.cpu.numCycles 260551438 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66252797 # ITB inst accesses +system.cpu.itb.hits 66240861 # DTB hits +system.cpu.itb.misses 11936 # DTB misses +system.cpu.itb.accesses 66252797 # DTB accesses +system.cpu.numCycles 260549216 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125305 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254586778 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563008 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882453 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -783,9 +784,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -814,13 +815,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -848,97 +849,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued -system.cpu.iq.rate 0.550119 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued +system.cpu.iq.rate 0.550285 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200946 # number of nop insts executed -system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed -system.cpu.iew.exec_branches 26532601 # Number of branches executed -system.cpu.iew.exec_stores 20878795 # Number of stores executed -system.cpu.iew.exec_rate 0.546502 # Inst execution rate -system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63282838 # num instructions producing a value -system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value +system.cpu.iew.exec_nop 200927 # number of nop insts executed +system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed +system.cpu.iew.exec_branches 26544157 # Number of branches executed +system.cpu.iew.exec_stores 20882594 # Number of stores executed +system.cpu.iew.exec_rate 0.546668 # Inst execution rate +system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63301722 # num instructions producing a value +system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back +system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113327248 # Number of instructions committed -system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113359982 # Number of instructions committed +system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45519928 # Number of memory references committed -system.cpu.commit.loads 24920655 # Number of loads committed -system.cpu.commit.membars 814679 # Number of memory barriers committed -system.cpu.commit.branches 26048896 # Number of branches committed +system.cpu.commit.refs 45531388 # Number of memory references committed +system.cpu.commit.loads 24928306 # Number of loads committed +system.cpu.commit.membars 814674 # Number of memory barriers committed +system.cpu.commit.branches 26060542 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120245785 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892513 # Number of function calls committed. +system.cpu.commit.int_insts 120282409 # Number of committed integer instructions. +system.cpu.commit.function_calls 4896404 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -966,55 +967,55 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction -system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction +system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373356629 # The number of ROB reads -system.cpu.rob.rob_writes 292965429 # The number of ROB writes -system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393139912 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113172343 # Number of Instructions Simulated -system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155828809 # number of integer regfile reads -system.cpu.int_regfile_writes 88634134 # number of integer regfile writes +system.cpu.rob.rob_reads 373371044 # The number of ROB reads +system.cpu.rob.rob_writes 293051212 # The number of ROB writes +system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113205077 # Number of Instructions Simulated +system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155870959 # number of integer regfile reads +system.cpu.int_regfile_writes 88663006 # number of integer regfile writes system.cpu.fp_regfile_reads 9591 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503010936 # number of cc regfile reads -system.cpu.cc_regfile_writes 53185281 # number of cc regfile writes -system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution +system.cpu.cc_regfile_reads 503160198 # number of cc regfile reads +system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes +system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795251 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31166 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128727 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121302864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98352737 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46636 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219917661 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65503 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3561986 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65488 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1027,31 +1028,31 @@ system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 3525536 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 36450 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 3525412 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 36449 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3561986 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503006527 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849563150 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334496858 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19512240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74894955 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1894110 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373809 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64308148 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894622 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.942469 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1894038 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373809 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1060,250 +1061,250 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 170 system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68184330 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68184330 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64308148 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64308148 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64308148 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64308148 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64308148 # number of overall hits -system.cpu.icache.overall_hits::total 64308148 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981542 # number of overall misses -system.cpu.icache.overall_misses::total 1981542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763338374 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26763338374 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26763338374 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26763338374 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26763338374 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26763338374 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66289690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66289690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66289690 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66289690 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66289690 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66289690 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029892 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029892 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029892 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029892 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029892 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029892 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.319005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.319005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.319005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.319005 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2089 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68132740 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68132740 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64256715 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64256715 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64256715 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64256715 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64256715 # number of overall hits +system.cpu.icache.overall_hits::total 64256715 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981457 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981457 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981457 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981457 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981457 # number of overall misses +system.cpu.icache.overall_misses::total 1981457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763157130 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26763157130 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26763157130 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26763157130 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26763157130 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26763157130 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66238172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66238172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66238172 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66238172 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66238172 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66238172 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.806925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.806925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.806925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.806925 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.086538 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86900 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86900 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86900 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86900 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86900 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86900 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894642 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894642 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894642 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894642 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894642 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894642 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22157720096 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22157720096 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22157720096 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22157720096 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22157720096 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22157720096 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202542500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202542500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202542500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 202542500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028581 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028581 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028581 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11694.937669 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11694.937669 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86887 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86887 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86887 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86887 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86887 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86887 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22160408840 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22160408840 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22160408840 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22160408840 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22160408840 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22160408840 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.801301 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.801301 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98637 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65077.786040 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3021048 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163850 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.437888 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 98619 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65077.788296 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3020959 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.439371 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49563.565409 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.530935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.672892 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.756280 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612651 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617936 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157326 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.079203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157327 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.079218 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7016 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28438268 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28438268 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53837 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11652 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874630 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528067 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2468186 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 695424 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 695424 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 28437367 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28437367 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53840 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1874571 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528036 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2468107 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 695414 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 695414 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 159691 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 159691 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53837 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 11652 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1874630 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 687758 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2627877 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53837 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 11652 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1874630 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 687758 # number of overall hits -system.cpu.l2cache.overall_hits::total 2627877 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 159688 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 159688 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53840 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11660 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1874571 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 687724 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2627795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53840 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11660 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1874571 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 687724 # number of overall hits +system.cpu.l2cache.overall_hits::total 2627795 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 19979 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 13624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33629 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2734 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2734 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 19966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 13620 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33612 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2733 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2733 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19979 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 150561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 170566 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19966 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 150557 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 170549 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19979 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 150561 # number of overall misses -system.cpu.l2cache.overall_misses::total 170566 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1661750 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 19966 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 150557 # number of overall misses +system.cpu.l2cache.overall_misses::total 170549 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1458500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1496766000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1081319750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2580283750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1500107250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078643000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2580745000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9921795191 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9921795191 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1661750 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9922806190 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9922806190 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1458500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1496766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11003114941 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12502078941 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1661750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1500107250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11001449190 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12503551190 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1458500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1496766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11003114941 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12502078941 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53856 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11659 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894609 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 541691 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2501815 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 695424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 695424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 1500107250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11001449190 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12503551190 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53859 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11667 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894537 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 541656 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2501719 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 695414 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 695414 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2767 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2767 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11659 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1894609 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 838319 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2798443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11659 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1894609 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 838319 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2798443 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53859 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 11667 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1894537 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 838281 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2798344 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53859 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11667 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1894537 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 838281 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2798344 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010545 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013442 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987717 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987717 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025145 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013436 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987712 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987712 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461646 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461646 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461650 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461650 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010545 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.179599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060950 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.179602 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060946 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010545 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.179599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060950 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87460.526316 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.179602 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060946 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76763.157895 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74916.962811 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79368.742660 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76727.935710 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.231529 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.231529 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75133.088751 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79195.521292 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76780.465310 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.309550 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.309550 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72455.181514 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72455.181514 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72462.564464 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72462.564464 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73297.602928 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73313.541504 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73297.602928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73313.541504 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1312,8 +1313,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 90641 # number of writebacks -system.cpu.l2cache.writebacks::total 90641 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 90626 # number of writebacks +system.cpu.l2cache.writebacks::total 90626 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits @@ -1325,96 +1326,96 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 112 system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19954 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13512 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33492 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2734 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19941 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13508 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33475 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2733 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2733 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 150449 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 170429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19941 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 150445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 170412 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19954 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 150449 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 170429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1426250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19941 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 150445 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 170412 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1223500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1244689750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 905485750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152053000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27405734 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27405734 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1248209500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902938000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152822250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27396733 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27396733 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8208319809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8208319809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1426250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8209305810 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8209305810 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1223500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1244689750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9113805559 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10360372809 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1426250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1248209500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112243810 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10362128060 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1223500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1244689750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9113805559 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10360372809 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157860000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387400000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545260000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107351500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107351500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157860000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494751500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652611500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1248209500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112243810 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10362128060 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387481250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545358250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107341000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107341000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494822250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652699250 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024944 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013387 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987717 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987717 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024938 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987712 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987712 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461646 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461646 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461650 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461650 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060901 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060897 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060901 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060897 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62377.956801 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67013.451007 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64255.732712 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.043160 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.043160 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62595.130635 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66844.684631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64311.344287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59942.307842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59942.307842 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59949.508241 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59949.508241 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1424,13 +1425,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 837784 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958472 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40159350 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838296 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.905931 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244993250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958472 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 837746 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1438,170 +1439,170 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179375223 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179375223 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23322313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23322313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15585229 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15585229 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346650 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346650 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441994 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441994 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460302 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460302 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38907542 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38907542 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39254192 # number of overall hits -system.cpu.dcache.overall_hits::total 39254192 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700487 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700487 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3573434 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3573434 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177076 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177076 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26736 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26736 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits +system.cpu.dcache.overall_hits::total 39265074 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4273921 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4273921 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4450997 # number of overall misses -system.cpu.dcache.overall_misses::total 4450997 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9902093641 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9902093641 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135168862785 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135168862785 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356751499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 356751499 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses +system.cpu.dcache.overall_misses::total 4451402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145070956426 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145070956426 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145070956426 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145070956426 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24022800 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24022800 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19158663 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19158663 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523726 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523726 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468730 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468730 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460307 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460307 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43181463 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43181463 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43705189 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43705189 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029159 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029159 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186518 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186518 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057039 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098976 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33943.293857 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33943.293857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.912650 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks -system.cpu.dcache.writebacks::total 695424 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks +system.cpu.dcache.writebacks::total 695414 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3560465 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414191 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299265 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713456 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832762 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5344701667 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713418 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17226829872 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1610,57 +1611,53 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328020 # Number of tag accesses -system.iocache.tags.data_accesses 328020 # Number of data accesses +system.iocache.tags.tag_accesses 327996 # Number of tag accesses +system.iocache.tags.data_accesses 327996 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses system.iocache.demand_misses::total 220 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 220 # number of overall misses system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1675,28 +1672,28 @@ system.iocache.demand_mshr_misses::realview.ide 220 system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 205f12926..23b34b238 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index a9432ee5f..deb0b678e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:14:43 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:38:41 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x5555b00 0x5555b00 - 0: system.cpu1.isa: ISA system set to: 0x5555b00 0x5555b00 + 0: system.cpu0.isa: ISA system set to: 0x479a680 0x479a680 + 0: system.cpu1.isa: ISA system set to: 0x479a680 0x479a680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2824356167500 because m5_exit instruction encountered +Exiting @ tick 2824340874000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index dc7744710..3996d6a6b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,186 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824356 # Number of seconds simulated -sim_ticks 2824356167500 # Number of ticks simulated -final_tick 2824356167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824341 # Number of seconds simulated +sim_ticks 2824340874000 # Number of ticks simulated +final_tick 2824340874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95847 # Simulator instruction rate (inst/s) -host_op_rate 116283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2253286315 # Simulator tick rate (ticks/s) -host_mem_usage 605880 # Number of bytes of host memory used -host_seconds 1253.44 # Real time elapsed on the host -sim_insts 120137953 # Number of instructions simulated -sim_ops 145753814 # Number of ops (including micro ops) simulated +host_inst_rate 96866 # Simulator instruction rate (inst/s) +host_op_rate 117519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2277239721 # Simulator tick rate (ticks/s) +host_mem_usage 609056 # Number of bytes of host memory used +host_seconds 1240.25 # Real time elapsed on the host +sim_insts 120137719 # Number of instructions simulated +sim_ops 145752951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 208 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 336 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 208 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 336 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 74 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 119 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 74 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 119 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 74 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 286048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1048060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10518784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 32848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 551328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1337024 # Number of bytes read from this memory -system.physmem.bytes_read::total 13777996 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 286048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 32848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 318896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7262976 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 286816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1046908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10513536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 549344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1344384 # Number of bytes read from this memory +system.physmem.bytes_read::total 13777356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 286816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 318768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7262336 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9599056 # Number of bytes written to this memory +system.physmem.bytes_written::total 9598416 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6715 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 16901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 164356 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 580 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8638 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 20891 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218142 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 113484 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 16883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 164274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 21006 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218132 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113474 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 154144 # Number of write requests responded to by this memory +system.physmem.num_writes::total 154134 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 101279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 371079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3724312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 195205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 473391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4878279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 101279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11630 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112909 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2571551 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 820837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 101551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 370673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3722474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 194503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 475999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4878078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 101551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2571338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820841 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3398671 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2571551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 821177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 101279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 377348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3724312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 195219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 473391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8276949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 218142 # Number of read requests accepted -system.physmem.writeReqs 154144 # Number of write requests accepted -system.physmem.readBursts 218142 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 154144 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13946624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14464 # Total number of bytes read from write queue -system.physmem.bytesWritten 9613440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13777996 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9599056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 226 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 3398462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2571338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 821181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 101551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 376942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3722474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 194518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 475999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8276541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 218132 # Number of read requests accepted +system.physmem.writeReqs 154134 # Number of write requests accepted +system.physmem.readBursts 218132 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 154134 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13944832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9612032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13777356 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9598416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13812 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13742 # Per bank write bursts -system.physmem.perBankRdBursts::1 13629 # Per bank write bursts -system.physmem.perBankRdBursts::2 14383 # Per bank write bursts -system.physmem.perBankRdBursts::3 14277 # Per bank write bursts -system.physmem.perBankRdBursts::4 15951 # Per bank write bursts -system.physmem.perBankRdBursts::5 13005 # Per bank write bursts -system.physmem.perBankRdBursts::6 13913 # Per bank write bursts -system.physmem.perBankRdBursts::7 13901 # Per bank write bursts -system.physmem.perBankRdBursts::8 13634 # Per bank write bursts -system.physmem.perBankRdBursts::9 13374 # Per bank write bursts -system.physmem.perBankRdBursts::10 12813 # Per bank write bursts -system.physmem.perBankRdBursts::11 11699 # Per bank write bursts -system.physmem.perBankRdBursts::12 13387 # Per bank write bursts -system.physmem.perBankRdBursts::13 14173 # Per bank write bursts -system.physmem.perBankRdBursts::14 13330 # Per bank write bursts -system.physmem.perBankRdBursts::15 12705 # Per bank write bursts -system.physmem.perBankWrBursts::0 9697 # Per bank write bursts -system.physmem.perBankWrBursts::1 9775 # Per bank write bursts -system.physmem.perBankWrBursts::2 10292 # Per bank write bursts -system.physmem.perBankWrBursts::3 9920 # Per bank write bursts -system.physmem.perBankWrBursts::4 9082 # Per bank write bursts -system.physmem.perBankWrBursts::5 9049 # Per bank write bursts -system.physmem.perBankWrBursts::6 9470 # Per bank write bursts -system.physmem.perBankWrBursts::7 9454 # Per bank write bursts -system.physmem.perBankWrBursts::8 9424 # Per bank write bursts -system.physmem.perBankWrBursts::9 9315 # Per bank write bursts -system.physmem.perBankWrBursts::10 9173 # Per bank write bursts -system.physmem.perBankWrBursts::11 8636 # Per bank write bursts -system.physmem.perBankWrBursts::12 9486 # Per bank write bursts -system.physmem.perBankWrBursts::13 9567 # Per bank write bursts -system.physmem.perBankWrBursts::14 9156 # Per bank write bursts -system.physmem.perBankWrBursts::15 8714 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 13729 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13731 # Per bank write bursts +system.physmem.perBankRdBursts::1 13637 # Per bank write bursts +system.physmem.perBankRdBursts::2 14382 # Per bank write bursts +system.physmem.perBankRdBursts::3 14282 # Per bank write bursts +system.physmem.perBankRdBursts::4 15946 # Per bank write bursts +system.physmem.perBankRdBursts::5 13017 # Per bank write bursts +system.physmem.perBankRdBursts::6 13909 # Per bank write bursts +system.physmem.perBankRdBursts::7 13917 # Per bank write bursts +system.physmem.perBankRdBursts::8 13612 # Per bank write bursts +system.physmem.perBankRdBursts::9 13371 # Per bank write bursts +system.physmem.perBankRdBursts::10 12787 # Per bank write bursts +system.physmem.perBankRdBursts::11 11726 # Per bank write bursts +system.physmem.perBankRdBursts::12 13349 # Per bank write bursts +system.physmem.perBankRdBursts::13 14174 # Per bank write bursts +system.physmem.perBankRdBursts::14 13344 # Per bank write bursts +system.physmem.perBankRdBursts::15 12704 # Per bank write bursts +system.physmem.perBankWrBursts::0 9692 # Per bank write bursts +system.physmem.perBankWrBursts::1 9790 # Per bank write bursts +system.physmem.perBankWrBursts::2 10299 # Per bank write bursts +system.physmem.perBankWrBursts::3 9942 # Per bank write bursts +system.physmem.perBankWrBursts::4 9060 # Per bank write bursts +system.physmem.perBankWrBursts::5 9040 # Per bank write bursts +system.physmem.perBankWrBursts::6 9465 # Per bank write bursts +system.physmem.perBankWrBursts::7 9428 # Per bank write bursts +system.physmem.perBankWrBursts::8 9418 # Per bank write bursts +system.physmem.perBankWrBursts::9 9301 # Per bank write bursts +system.physmem.perBankWrBursts::10 9150 # Per bank write bursts +system.physmem.perBankWrBursts::11 8663 # Per bank write bursts +system.physmem.perBankWrBursts::12 9463 # Per bank write bursts +system.physmem.perBankWrBursts::13 9594 # Per bank write bursts +system.physmem.perBankWrBursts::14 9165 # Per bank write bursts +system.physmem.perBankWrBursts::15 8718 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2824354558500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2824339295000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3083 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 214472 # Read request sizes (log2) +system.physmem.readPktSize::6 214462 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149708 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 53602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149698 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 53523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -209,115 +191,117 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4134 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 253.699567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.705803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.390709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46941 50.55% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18915 20.37% 70.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6813 7.34% 78.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3565 3.84% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3222 3.47% 85.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2153 2.32% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1230 1.32% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1078 1.16% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8949 9.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7533 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.928183 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 527.934330 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7532 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 253.842782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.815283 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.388546 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46919 50.56% 50.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18870 20.33% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6768 7.29% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3705 3.99% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3168 3.41% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2103 2.27% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1242 1.34% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1089 1.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92801 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.931483 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 528.461754 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7530 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7533 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.940263 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.639504 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.756386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6124 81.30% 81.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 560 7.43% 88.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 110 1.46% 90.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 221 2.93% 93.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 195 2.59% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.28% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.23% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 21 0.28% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 30 0.40% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 97.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.04% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 162 2.15% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.17% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.09% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7533 # Writes before turning the bus around for reads -system.physmem.totQLat 8921648500 # Total ticks spent queuing -system.physmem.totMemAccLat 13007573500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1089580000 # Total ticks spent in databus transfers -system.physmem.avgQLat 40940.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7531 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7531 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.942637 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.618581 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.035986 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6139 81.52% 81.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 568 7.54% 89.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 91 1.21% 90.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 228 3.03% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 184 2.44% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 18 0.24% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 26 0.35% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.15% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 33 0.44% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.07% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.13% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 156 2.07% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.12% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.17% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.05% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.08% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7531 # Writes before turning the bus around for reads +system.physmem.totQLat 8907181250 # Total ticks spent queuing +system.physmem.totMemAccLat 12992581250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1089440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 40879.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 59690.77 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 59629.63 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s @@ -326,599 +310,617 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.17 # Average write queue length when enqueuing -system.physmem.readRowHits 185257 # Number of row buffer hits during reads -system.physmem.writeRowHits 90003 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.91 # Row buffer hit rate for writes -system.physmem.avgGap 7586518.32 # Average gap between requests -system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2697281054000 # Time in different power states -system.physmem.memoryStateTime::REF 94311360000 # Time in different power states +system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.20 # Average write queue length when enqueuing +system.physmem.readRowHits 185267 # Number of row buffer hits during reads +system.physmem.writeRowHits 90008 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.92 # Row buffer hit rate for writes +system.physmem.avgGap 7586884.90 # Average gap between requests +system.physmem.pageHitRate 74.78 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2697410352000 # Time in different power states +system.physmem.memoryStateTime::REF 94310840000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32761026000 # Time in different power states +system.physmem.memoryStateTime::ACT 32616675500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 364739760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 337327200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 199014750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 184057500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 879847800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 819897000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 497268720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 476092080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184473020160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184473020160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 78882264090 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 78474830085 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625417087250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1625774485500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1890713242530 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1890539709525 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.432241 # Core power per rank (mW) -system.physmem.averagePower::1 669.370799 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 237803 # Transaction distribution -system.membus.trans_dist::ReadResp 237803 # Transaction distribution -system.membus.trans_dist::WriteReq 30981 # Transaction distribution -system.membus.trans_dist::WriteResp 30981 # Transaction distribution -system.membus.trans_dist::Writeback 113484 # Transaction distribution +system.physmem.actEnergy::0 364754880 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 336820680 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 199023000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 183781125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 880003800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 819522600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 497119680 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 476098560 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184472003040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184472003040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 78880301865 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 78435436815 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625409465000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1625799697500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1890702671265 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1890523360320 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.432189 # Core power per rank (mW) +system.physmem.averagePower::1 669.368701 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 237823 # Transaction distribution +system.membus.trans_dist::ReadResp 237823 # Transaction distribution +system.membus.trans_dist::WriteReq 30977 # Transaction distribution +system.membus.trans_dist::WriteResp 30977 # Transaction distribution +system.membus.trans_dist::Writeback 113474 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79622 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40753 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13812 # Transaction distribution -system.membus.trans_dist::ReadExReq 31225 # Transaction distribution -system.membus.trans_dist::ReadExResp 14907 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79489 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40661 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13729 # Transaction distribution +system.membus.trans_dist::ReadExReq 31194 # Transaction distribution +system.membus.trans_dist::ReadExResp 14874 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 709115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 830877 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 830527 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 903587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 903237 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21057756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21248442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21056476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21247122 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23567738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123113 # Total snoops (count) -system.membus.snoop_fanout::samples 501114 # Request fanout histogram +system.membus.pkt_size::total 23566418 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122973 # Total snoops (count) +system.membus.snoop_fanout::samples 500866 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 501114 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 500866 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 501114 # Request fanout histogram -system.membus.reqLayer0.occupancy 81319989 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 500866 # Request fanout histogram +system.membus.reqLayer0.occupancy 81235490 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11512493 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11626497 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1643090249 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1642596998 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2114237552 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2113984385 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38543657 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38546403 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 153338 # number of replacements -system.l2c.tags.tagsinuse 64407.351795 # Cycle average of tags in use -system.l2c.tags.total_refs 520948 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 218016 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.389494 # Average number of references to valid blocks. +system.l2c.tags.replacements 153419 # number of replacements +system.l2c.tags.tagsinuse 64440.075057 # Cycle average of tags in use +system.l2c.tags.total_refs 521049 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 218085 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.389201 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 14039.109160 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 10.926266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1406.687456 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2124.369402 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39350.084930 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.463090 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906491 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 305.066680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 911.182744 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6250.491894 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.214220 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000167 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.021464 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.032415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.600435 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000114 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004655 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013904 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.095375 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.982778 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44311 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 20347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 406 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 7760 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 36145 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 14106.989110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.481706 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.879098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1413.448081 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2144.570039 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39278.457251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.502209 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002709 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 292.869735 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 885.757521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6295.117598 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.215256 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.021568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.032724 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004469 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013516 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983278 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 44367 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 20280 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 7792 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 36164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4612 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15362 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.676132 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.310471 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6600636 # Number of tag accesses -system.l2c.tags.data_accesses 6600636 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 292 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 154 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 12492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 39083 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182457 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 82 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4094 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11500 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44186 # number of ReadReq hits -system.l2c.ReadReq_hits::total 294388 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 252842 # number of Writeback hits -system.l2c.Writeback_hits::total 252842 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11706 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4621 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15296 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.676987 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.309448 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6602520 # Number of tag accesses +system.l2c.tags.data_accesses 6602520 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 282 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 12559 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 39006 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182592 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 97 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 55 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 4109 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11553 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44326 # number of ReadReq hits +system.l2c.ReadReq_hits::total 294701 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 252802 # number of Writeback hits +system.l2c.Writeback_hits::total 252802 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12433 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 197 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 154 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 351 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3674 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1157 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4831 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 292 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 154 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 12492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 42757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 182457 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 82 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4094 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 44186 # number of demand (read+write) hits -system.l2c.demand_hits::total 299219 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 292 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 154 # number of overall hits -system.l2c.overall_hits::cpu0.inst 12492 # number of overall hits -system.l2c.overall_hits::cpu0.data 42757 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 182457 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 82 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4094 # number of overall hits -system.l2c.overall_hits::cpu1.data 12657 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 44186 # number of overall hits -system.l2c.overall_hits::total 299219 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3722 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8649 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164359 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 492 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1396 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 20906 # number of ReadReq misses -system.l2c.ReadReq_misses::total 199570 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8911 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2815 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11726 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 768 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1215 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1983 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 7775 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7235 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 15010 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3722 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 164359 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 492 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8631 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 20906 # number of demand (read+write) misses -system.l2c.demand_misses::total 214580 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3722 # number of overall misses -system.l2c.overall_misses::cpu0.data 16424 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 164359 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 492 # number of overall misses -system.l2c.overall_misses::cpu1.data 8631 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 20906 # number of overall misses -system.l2c.overall_misses::total 214580 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2653000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 225500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 348764246 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 769947990 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 875000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 50097250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 119367500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 22807506228 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 7178208 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2570892 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9749100 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1432440 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 791466 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2223906 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 708658416 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 564088479 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1272746895 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2653000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 225500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 348764246 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1478606406 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 875000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 50097250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 683455979 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 24080253123 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2653000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 225500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 348764246 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1478606406 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 875000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 50097250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 683455979 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of overall miss cycles -system.l2c.overall_miss_latency::total 24080253123 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 323 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 157 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 16214 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 47732 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346816 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 93 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 49 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 4586 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12896 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65092 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 493958 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 252842 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 252842 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 20617 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3542 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 24159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 965 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1369 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2334 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 11449 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 8392 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 19841 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 323 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 157 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 16214 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 59181 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346816 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 93 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 49 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 4586 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 21288 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65092 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 513799 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 323 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 157 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 16214 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 59181 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346816 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 93 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 4586 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 21288 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65092 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 513799 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019108 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.229555 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.181199 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.107283 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.108251 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.404022 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.432216 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.794749 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.485368 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795855 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.887509 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.849614 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.679099 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.862131 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.756514 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019108 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.229555 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.277522 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.020408 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.107283 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.405440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.417634 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019108 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.229555 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.277522 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.020408 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.107283 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.405440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.417634 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93703.451370 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 89021.619840 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average ReadReq miss latency +system.l2c.UpgradeReq_hits::total 12432 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 184 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 173 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 357 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3642 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1229 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4871 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 12559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 42648 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 182592 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 97 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 55 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 4109 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 44326 # number of demand (read+write) hits +system.l2c.demand_hits::total 299572 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits +system.l2c.overall_hits::cpu0.inst 12559 # number of overall hits +system.l2c.overall_hits::cpu0.data 42648 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 182592 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 97 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 55 # number of overall hits +system.l2c.overall_hits::cpu1.inst 4109 # number of overall hits +system.l2c.overall_hits::cpu1.data 12782 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 44326 # number of overall hits +system.l2c.overall_hits::total 299572 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8647 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164277 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 479 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1383 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21024 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199597 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8851 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2828 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11679 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1952 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 7757 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7215 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 14972 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3733 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 16404 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 164277 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 479 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8598 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 21024 # number of demand (read+write) misses +system.l2c.demand_misses::total 214569 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses +system.l2c.overall_misses::cpu0.data 16404 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 164277 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 479 # number of overall misses +system.l2c.overall_misses::cpu1.data 8598 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 21024 # number of overall misses +system.l2c.overall_misses::total 214569 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2727250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 613750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 350075996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 761569744 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 768250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 150000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 47537750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 122331750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 22797831231 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 6376742 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2877882 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9254624 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147452 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1135953 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2283405 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 711214419 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 562948982 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1274163401 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2727250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 613750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 350075996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1472784163 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 768250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 150000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 47537750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 685280732 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 24071994632 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2727250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 613750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 350075996 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1472784163 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 768250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 150000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 47537750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 685280732 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of overall miss cycles +system.l2c.overall_miss_latency::total 24071994632 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 316 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 130 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 16292 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 47653 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346869 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 107 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 57 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 4588 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12936 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65350 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 494298 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 252802 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 252802 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 20556 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3555 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24111 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 933 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1376 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 11399 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8444 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 19843 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 316 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 130 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 16292 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 59052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346869 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 57 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 4588 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 21380 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65350 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 514141 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 316 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 130 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 16292 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 59052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346869 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 57 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 4588 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 21380 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65350 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 514141 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.061538 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.229131 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.181458 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.035088 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.104403 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.106911 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.403799 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.430580 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795499 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.484385 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.802787 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.874273 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.845388 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.680498 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.854453 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.754523 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.061538 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.229131 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.277789 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.035088 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.104403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.402152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.417335 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.061538 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.229131 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.277789 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.035088 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.104403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.402152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.417335 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 76718.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93778.729172 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 88073.290621 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76825 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 101823.678862 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 85506.805158 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 114283.240106 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 805.544608 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 913.283126 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 831.408835 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1865.156250 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 651.412346 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1121.485628 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91145.776977 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77966.617692 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84793.264157 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 99243.736952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 88453.904555 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 114219.308061 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 720.454412 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1017.638614 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 792.415789 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1531.978638 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 944.266833 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1169.777152 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91686.788578 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78024.806930 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85103.085827 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 76718.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 93778.729172 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 89782.014326 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76825 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 112220.398560 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 99243.736952 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 79702.341475 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 112187.662859 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 76718.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 93778.729172 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 89782.014326 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76825 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 112220.398560 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 435 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu1.inst 99243.736952 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 79702.341475 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 112187.662859 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 168 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 11 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 16.730769 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 15.272727 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 113484 # number of writebacks -system.l2c.writebacks::total 113484 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 113474 # number of writebacks +system.l2c.writebacks::total 113474 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 18 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 31 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 3721 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8649 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 491 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1396 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 199550 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8911 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2815 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11726 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 768 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1215 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1983 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 7775 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7235 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 15010 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 31 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 3721 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 16424 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 491 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8631 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 214560 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 31 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 3721 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 16424 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 491 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8631 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 214560 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 187500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 302749246 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 662570490 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 738500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 43998750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101980500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 20353955728 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90147824 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28509296 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 118657120 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7897727 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12233707 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 20131434 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 612435582 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 472780517 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1085216099 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 187500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 302749246 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1275006072 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 738500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 43998750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 574761017 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21439171827 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 187500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 302749246 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1275006072 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 738500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 43998750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 574761017 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21439171827 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 158715000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685804000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5055250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919801500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5769375750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713908502 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535177501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4249086003 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158715000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6399712502 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5055250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3454979001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10018461753 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181199 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108251 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.403982 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.432216 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.794749 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.485368 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795855 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.887509 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.849614 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.679099 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.862131 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.756514 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.417595 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.417595 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76606.600763 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average ReadReq mshr miss latency +system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 24 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 34 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3733 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8646 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 477 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1383 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 199573 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8851 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2828 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11679 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 749 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1203 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1952 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 7757 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7215 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 14972 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 34 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 8 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3733 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 16403 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 477 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8598 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 214545 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 34 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 8 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 3733 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 16403 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 477 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8598 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 214545 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 513750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 303960496 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 654157744 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 643750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 41455250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105134250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 20343291231 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 89616766 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28576308 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 118193074 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7674203 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12103692 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 19777895 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 615195579 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 471924516 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1087120095 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 513750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 303960496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1269353323 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 643750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 41455250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 577058766 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21430411326 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 513750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 303960496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1269353323 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 643750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 41455250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 577058766 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21430411326 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686341747 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919844500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5770618747 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713885499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535420500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4249305999 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400227246 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455265000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10019924746 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181437 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.106911 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.403750 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430580 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795499 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.484385 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.802787 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.874273 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845388 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.680498 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854453 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.754523 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.417288 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.417288 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75660.160074 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73051.934097 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 101999.277013 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10116.465492 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10127.636234 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.147194 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10283.498698 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10068.894650 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10152.009077 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78769.849775 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65346.305045 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72299.540240 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76018.980477 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 101934.085427 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10125.044176 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.776521 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.136484 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10245.931909 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10061.256858 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10132.118340 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79308.441279 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65408.803326 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72610.212063 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -970,50 +972,50 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 660507 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 660492 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30981 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30981 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 252842 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 91952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41104 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 133056 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 40101 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 40101 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1300560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426210 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1726770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40798474 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8541616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49340090 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 291850 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1084776 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033629 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.180273 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 660487 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 660472 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30977 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 252802 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 91823 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41018 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 132841 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 40090 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 40090 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1299997 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426747 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1726744 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40789878 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8569500 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49359378 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 291335 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1084475 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033634 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.180285 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1048296 96.64% 96.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36480 3.36% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1048000 96.64% 96.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36475 3.36% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1084776 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1587917075 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1084475 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1587731325 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2276216676 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2275347621 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 846189675 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 846816900 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31016 # Transaction distribution system.iobus.trans_dist::ReadResp 31016 # Transaction distribution -system.iobus.trans_dist::WriteReq 59419 # Transaction distribution +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 21 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 15 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1104,23 +1106,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326647327 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326640327 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36834343 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36831597 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 24027935 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15717476 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 977431 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14651046 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10773468 # Number of BTB hits +system.cpu0.branchPred.lookups 24028098 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15717962 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 977131 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14655901 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10773369 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.533780 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3878036 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32430 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.508746 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3877913 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32441 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1144,25 +1146,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17722520 # DTB read hits -system.cpu0.dtb.read_misses 56371 # DTB read misses -system.cpu0.dtb.write_hits 14647463 # DTB write hits -system.cpu0.dtb.write_misses 8727 # DTB write misses +system.cpu0.dtb.read_hits 17721911 # DTB read hits +system.cpu0.dtb.read_misses 56434 # DTB read misses +system.cpu0.dtb.write_hits 14647364 # DTB write hits +system.cpu0.dtb.write_misses 8710 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 304 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2358 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 853 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17778891 # DTB read accesses -system.cpu0.dtb.write_accesses 14656190 # DTB write accesses +system.cpu0.dtb.perms_faults 855 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17778345 # DTB read accesses +system.cpu0.dtb.write_accesses 14656074 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32369983 # DTB hits -system.cpu0.dtb.misses 65098 # DTB misses -system.cpu0.dtb.accesses 32435081 # DTB accesses +system.cpu0.dtb.hits 32369275 # DTB hits +system.cpu0.dtb.misses 65144 # DTB misses +system.cpu0.dtb.accesses 32434419 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1184,8 +1186,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 37749886 # ITB inst hits -system.cpu0.itb.inst_misses 10298 # ITB inst misses +system.cpu0.itb.inst_hits 37749203 # ITB inst hits +system.cpu0.itb.inst_misses 10291 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1194,98 +1196,98 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2364 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1942 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1952 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37760184 # ITB inst accesses -system.cpu0.itb.hits 37749886 # DTB hits -system.cpu0.itb.misses 10298 # DTB misses -system.cpu0.itb.accesses 37760184 # DTB accesses -system.cpu0.numCycles 126958641 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37759494 # ITB inst accesses +system.cpu0.itb.hits 37749203 # DTB hits +system.cpu0.itb.misses 10291 # DTB misses +system.cpu0.itb.accesses 37759494 # DTB accesses +system.cpu0.numCycles 126930318 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18143411 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 112712815 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 24027935 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14651504 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 104787507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2823240 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 133419 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 39139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 365906 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 432078 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 38034 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37750510 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 265510 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3919 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 125351114 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.084784 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.263056 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18136746 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 112711782 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 24028098 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14651282 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 104771989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2822564 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133376 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 38789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 365072 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 429907 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 37570 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37749815 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 265004 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3918 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 125324731 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.084977 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.263079 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62795131 50.10% 50.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21461544 17.12% 67.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8765998 6.99% 74.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 32328441 25.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 62770441 50.09% 50.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21460959 17.12% 67.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8766539 7.00% 74.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32326792 25.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 125351114 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.189258 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.887792 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19217150 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58693987 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 41414238 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4958351 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1067388 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3055751 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 348432 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 110728193 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3997819 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1067388 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24968075 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11998776 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 36565512 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40482982 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10268381 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 105647193 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1060681 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1440352 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 161094 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 60996 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6068574 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 109731042 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 482381977 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 120921551 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9385 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 98136808 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11594231 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1228692 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1087401 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12320869 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18735521 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16202725 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1699910 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2282844 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 102687285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1694390 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100670059 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 484670 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9020348 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22495673 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 122680 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 125351114 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.803105 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.034773 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 125324731 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.189301 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.887982 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19209269 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58676701 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41413260 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4958284 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1067217 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3055385 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 348256 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 110724808 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3997323 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1067217 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24959463 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12008700 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 36549302 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40482992 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10257057 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 105644030 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1060860 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1434602 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 161076 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 61450 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6058216 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109726611 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 482367040 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120917485 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 98135067 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11591541 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1228775 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1087468 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12318365 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18735262 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16202067 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1700806 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2287265 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102683814 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1694438 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100667981 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 483835 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9019913 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22488132 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 122848 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 125324731 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.803257 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.034844 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 69205207 55.21% 55.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23183333 18.49% 73.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22514733 17.96% 91.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9334141 7.45% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1113663 0.89% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 69182553 55.20% 55.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23178514 18.49% 73.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22516011 17.97% 91.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9333204 7.45% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1114412 0.89% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -1293,44 +1295,44 @@ system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 125351114 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 125324731 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9379501 40.75% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 82 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5582636 24.26% 65.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8053143 34.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9379454 40.76% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 82 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5581640 24.26% 65.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8050330 34.98% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66409608 65.97% 65.97% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 93111 0.09% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66408183 65.97% 65.97% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 93140 0.09% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued @@ -1353,102 +1355,102 @@ system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Ty system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18430675 18.31% 84.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15726281 15.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18430252 18.31% 84.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15726021 15.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100670059 # Type of FU issued -system.cpu0.iq.rate 0.792936 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 23015362 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228622 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 350159403 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 113409879 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98581657 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 31861 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9722 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 123662544 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 20604 # Number of floating point alu accesses +system.cpu0.iq.FU_type_0::total 100667981 # Type of FU issued +system.cpu0.iq.rate 0.793096 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23011506 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228588 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 350124170 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 113406012 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98579580 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 31864 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123656622 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 20592 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2006423 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2595 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19219 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1022338 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2006492 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2605 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19209 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1022192 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 106441 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 337136 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 106472 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 336634 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1615648 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 188928 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 104556414 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1067217 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1619268 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 191305 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 104552982 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18735521 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16202725 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876047 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27263 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 138025 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19219 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291871 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 400586 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 692457 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99572602 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17974009 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1032494 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18735262 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16202067 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876141 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27204 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 140421 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19209 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 291739 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 400527 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 692266 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99570429 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17973451 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1032544 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 174739 # number of nop insts executed -system.cpu0.iew.exec_refs 33508875 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16843329 # Number of branches executed -system.cpu0.iew.exec_stores 15534866 # Number of stores executed -system.cpu0.iew.exec_rate 0.784292 # Inst execution rate -system.cpu0.iew.wb_sent 99041613 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98591379 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51320038 # num instructions producing a value -system.cpu0.iew.wb_consumers 84796920 # num instructions consuming a value +system.cpu0.iew.exec_nop 174730 # number of nop insts executed +system.cpu0.iew.exec_refs 33508210 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16843179 # Number of branches executed +system.cpu0.iew.exec_stores 15534759 # Number of stores executed +system.cpu0.iew.exec_rate 0.784450 # Inst execution rate +system.cpu0.iew.wb_sent 99039643 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98589303 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51320532 # num instructions producing a value +system.cpu0.iew.wb_consumers 84799978 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.776563 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605211 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.776720 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605195 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8526320 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1571710 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 633199 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 123596989 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.768069 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.480980 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 8525678 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1571590 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 633066 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 123570875 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.768216 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.481246 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 79268840 64.13% 64.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24713999 20.00% 84.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8247824 6.67% 90.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3215855 2.60% 93.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3439875 2.78% 96.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1518279 1.23% 97.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1140929 0.92% 98.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 533748 0.43% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1517640 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 79246760 64.13% 64.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24711613 20.00% 84.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8248135 6.67% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3213746 2.60% 93.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3439781 2.78% 96.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1516341 1.23% 97.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1141391 0.92% 98.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 534018 0.43% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1519090 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 123596989 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78900966 # Number of instructions committed -system.cpu0.commit.committedOps 94931037 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 123570875 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78899754 # Number of instructions committed +system.cpu0.commit.committedOps 94929142 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31909485 # Number of memory references committed -system.cpu0.commit.loads 16729098 # Number of loads committed -system.cpu0.commit.membars 647159 # Number of memory barriers committed -system.cpu0.commit.branches 16205509 # Number of branches committed +system.cpu0.commit.refs 31908645 # Number of memory references committed +system.cpu0.commit.loads 16728770 # Number of loads committed +system.cpu0.commit.membars 647107 # Number of memory barriers committed +system.cpu0.commit.branches 16205360 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81880566 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1929583 # Number of function calls committed. +system.cpu0.commit.int_insts 81878721 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1929507 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62922752 66.28% 66.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 90691 0.10% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62921673 66.28% 66.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 90715 0.10% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction @@ -1476,501 +1478,504 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16729098 17.62% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15180387 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16728770 17.62% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15179875 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 94931037 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1517640 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 94929142 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1519090 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 221353668 # The number of ROB reads -system.cpu0.rob.rob_writes 208668086 # The number of ROB writes -system.cpu0.timesIdled 109562 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1607527 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5521753720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78778915 # Number of Instructions Simulated -system.cpu0.committedOps 94808986 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.611581 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.611581 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.620508 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.620508 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110614815 # number of integer regfile reads -system.cpu0.int_regfile_writes 59737885 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8165 # number of floating regfile reads +system.cpu0.rob.rob_reads 221323955 # The number of ROB reads +system.cpu0.rob.rob_writes 208662740 # The number of ROB writes +system.cpu0.timesIdled 109422 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1605587 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5521751456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78777703 # Number of Instructions Simulated +system.cpu0.committedOps 94807091 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.611247 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.611247 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.620637 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.620637 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110612001 # number of integer regfile reads +system.cpu0.int_regfile_writes 59736021 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes -system.cpu0.cc_regfile_reads 350771001 # number of cc regfile reads -system.cpu0.cc_regfile_writes 41073809 # number of cc regfile writes -system.cpu0.misc_regfile_reads 245697526 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224542 # number of misc regfile writes -system.cpu0.toL2Bus.trans_dist::ReadReq 2022292 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1921231 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19109 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19109 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 512497 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 635775 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 81120 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43298 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 105236 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 291864 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 281152 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2535030 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2361050 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28910 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120430 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5045420 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80976096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86183658 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50232 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218780 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 167428766 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1029243 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3600041 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.252406 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.434393 # Request fanout histogram +system.cpu0.cc_regfile_reads 350763374 # number of cc regfile reads +system.cpu0.cc_regfile_writes 41072426 # number of cc regfile writes +system.cpu0.misc_regfile_reads 246706358 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1224463 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 2021709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1920443 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 512971 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 647722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 80908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43157 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 104918 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 291878 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 281134 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2533809 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360432 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28914 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120703 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5043858 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80936864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86195670 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50328 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 219428 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 167402290 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1041040 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3611543 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.254928 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.435821 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2691370 74.76% 74.76% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 908671 25.24% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2690859 74.51% 74.51% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 920684 25.49% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3600041 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1889888022 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3611543 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1890112247 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117489749 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117326747 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1901826585 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1900909092 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1220473591 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1220029643 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16363478 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 16342731 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 65772430 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 65878690 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 1263981 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.774384 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36445999 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1264493 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.822618 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6310719000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774384 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 1263367 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774258 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36446077 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1263879 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.836682 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774258 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 76759130 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 76759130 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36445999 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36445999 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36445999 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36445999 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36445999 # number of overall hits -system.cpu0.icache.overall_hits::total 36445999 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1301304 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1301304 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1301304 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1301304 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1301304 # number of overall misses -system.cpu0.icache.overall_misses::total 1301304 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11020664802 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11020664802 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11020664802 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11020664802 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11020664802 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11020664802 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37747303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37747303 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37747303 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37747303 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37747303 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034474 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034474 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034474 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034474 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034474 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034474 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.939465 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.939465 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8468.939465 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8468.939465 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 725662 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 76757150 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76757150 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36446077 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36446077 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36446077 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36446077 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36446077 # number of overall hits +system.cpu0.icache.overall_hits::total 36446077 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1300540 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1300540 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1300540 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1300540 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1300540 # number of overall misses +system.cpu0.icache.overall_misses::total 1300540 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11011983856 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11011983856 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11011983856 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11011983856 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11011983856 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11011983856 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37746617 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37746617 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37746617 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37746617 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37746617 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37746617 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034454 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034454 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034454 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034454 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034454 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034454 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8467.239651 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8467.239651 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8467.239651 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8467.239651 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 724812 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 96193 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 96016 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.543813 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.548867 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36779 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 36779 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 36779 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 36779 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 36779 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 36779 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264525 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1264525 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264525 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1264525 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264525 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1264525 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8921757516 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8921757516 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8921757516 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8921757516 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8921757516 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8921757516 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243776998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243776998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243776998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 243776998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033500 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033500 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033500 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7055.422009 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36623 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 36623 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 36623 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 36623 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 36623 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 36623 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1263917 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1263917 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1263917 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1263917 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1263917 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1263917 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8916921322 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8916921322 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8916921322 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8916921322 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8916921322 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8916921322 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033484 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033484 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033484 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.989625 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11570902 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525454 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10431616 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 117790 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11566475 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 526266 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10413579 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118534 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25307 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 470730 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881250 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25521 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 482570 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881997 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 397283 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16205.229139 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2244912 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 413530 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.428656 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2809069613500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4639.805304 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.151524 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.649414 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 948.692737 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.057987 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9191.872173 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.283191 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000803 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057904 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086063 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.561027 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989089 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8152 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8085 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 237 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3322 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4084 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 501 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3682 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3594 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 245 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.497559 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.493469 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 43590224 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 43590224 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54156 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12330 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242747 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 407291 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1716524 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 512497 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 512497 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15462 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 15462 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2188 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2188 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216542 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 216542 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54156 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12330 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1242747 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 623833 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1933066 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54156 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12330 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1242747 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 623833 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1933066 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 539 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 228 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21755 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 91027 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 113549 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27999 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27999 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18512 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18512 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52925 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 52925 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 539 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 228 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 21755 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 143952 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 166474 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 539 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 228 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 21755 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 143952 # number of overall misses -system.cpu0.l2cache.overall_misses::total 166474 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14141500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5255000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 812129434 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2705700107 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 3537226041 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502587457 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 502587457 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362338282 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362338282 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 217500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 217500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2594310029 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2594310029 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14141500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5255000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 812129434 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5300010136 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 6131536070 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14141500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5255000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 812129434 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5300010136 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 6131536070 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54695 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12558 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264502 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498318 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1830073 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 512497 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 512497 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43461 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 43461 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20700 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20700 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269467 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269467 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54695 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12558 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1264502 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 767785 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2099540 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54695 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12558 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1264502 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 767785 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2099540 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.018156 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017204 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182668 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.062046 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.644233 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.644233 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.894300 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.894300 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.196406 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.196406 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.018156 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017204 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.187490 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.079291 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.018156 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017204 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.187490 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.079291 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23048.245614 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37330.702551 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29724.148956 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31151.538464 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17950.193114 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17950.193114 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19573.156979 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19573.156979 # average SCUpgradeReq miss latency +system.cpu0.l2cache.tags.replacements 397205 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16210.584505 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2245016 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 413453 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.429918 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2809067534500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4582.280464 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 7.704235 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.810288 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 954.063900 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1415.763715 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9248.961904 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.279680 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000470 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.058231 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086411 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.564512 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989416 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8114 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8126 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 255 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3376 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3995 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 500 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3570 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 262 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.495239 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.495972 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 43582923 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 43582923 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54301 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12378 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242064 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 407333 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1716076 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 512970 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 512970 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15323 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 15323 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2128 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2128 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216744 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 216744 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54301 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12378 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1242064 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 624077 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1932820 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54301 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12378 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1242064 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 624077 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1932820 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 556 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 204 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21825 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 90809 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 113394 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27941 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52711 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 52711 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 556 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 204 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 21825 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 143520 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 166105 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 556 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 204 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 21825 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 143520 # number of overall misses +system.cpu0.l2cache.overall_misses::total 166105 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14566249 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5056249 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 811526688 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694555362 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 3525704548 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501364439 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 501364439 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362083288 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362083288 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 361000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 361000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2596231534 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2596231534 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14566249 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5056249 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 811526688 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5290786896 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 6121936082 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14566249 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5056249 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 811526688 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5290786896 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 6121936082 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54857 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12582 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1263889 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498142 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1829470 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 512971 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 512971 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43264 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 43264 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20607 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20607 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269455 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269455 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54857 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12582 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1263889 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 767597 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2098925 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54857 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12582 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1263889 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 767597 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2098925 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016214 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017268 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182295 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.061982 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645826 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645826 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.896734 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.896734 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195621 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195621 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016214 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017268 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186973 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.079138 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016214 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017268 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186973 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.079138 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24785.534314 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.353402 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29672.778711 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31092.514137 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17943.682724 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17943.682724 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19594.311813 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19594.311813 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49018.611790 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49018.611790 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 36831.793974 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 36831.793974 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 59871 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49254.074747 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49254.074747 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 36855.820607 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 36855.820607 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 65022 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 1464 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 1467 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 40.895492 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.323108 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 212118 # number of writebacks -system.cpu0.l2cache.writebacks::total 212118 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.writebacks::writebacks 212015 # number of writebacks +system.cpu0.l2cache.writebacks::total 212015 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5582 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3121 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 8705 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8957 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 8957 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5576 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3180 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 8757 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8826 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 8826 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5582 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12078 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 17662 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5576 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12006 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5582 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12078 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 17662 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 538 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 227 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16173 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87906 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 104844 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 470726 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27999 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27999 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18512 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18512 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43968 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43968 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 538 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 227 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16173 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131874 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 148812 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 538 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 227 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16173 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131874 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 619538 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3653000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 584863774 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2018675176 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2617551450 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21918972757 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 483477329 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 483477329 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 250147229 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 250147229 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 175500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 175500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315007380 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315007380 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3653000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 584863774 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3333682556 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 3932558830 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3653000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 584863774 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3333682556 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 25851531587 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218357500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053329974 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4271687474 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040369451 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040369451 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218357500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7093699425 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312056925 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176405 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057290 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5576 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12006 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 17583 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 556 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 203 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16249 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87629 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 104637 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 482567 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27941 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18479 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18479 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43885 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43885 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 556 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 203 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16249 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131514 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 148522 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 556 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 203 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16249 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131514 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 631089 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3620751 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 587001511 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2007365947 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2608656960 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21948496416 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 481784375 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481784375 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249254743 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249254743 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 284000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 284000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315803854 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315803854 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3620751 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 587001511 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3323169801 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3924460814 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3620751 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 587001511 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3323169801 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 25872957230 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053946738 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272660488 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040262957 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040262957 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7094209695 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312923445 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175912 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057195 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.644233 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.644233 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.894300 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.894300 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163167 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163167 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070878 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645826 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645826 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896734 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896734 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162866 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162866 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070761 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.295083 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22964.020385 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24966.154000 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46564.185443 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17267.664167 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17267.664167 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13512.706839 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13512.706839 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300672 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22907.552831 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24930.540440 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45482.795997 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17242.918113 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17242.918113 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13488.540668 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13488.540668 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29908.282842 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29908.282842 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26426.355603 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41727.112117 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29982.997699 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29982.997699 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26423.430966 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40997.319285 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1980,192 +1985,192 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 712949 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.466444 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28841621 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 713461 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.424944 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 256469000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.466444 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965755 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965755 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 712829 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.082766 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28841671 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 713341 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.431815 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082766 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63482821 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63482821 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15588564 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15588564 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12071351 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12071351 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311001 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 311001 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363214 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363214 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360561 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 360561 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27659915 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27659915 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27970916 # number of overall hits -system.cpu0.dcache.overall_hits::total 27970916 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 638335 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 638335 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1832649 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1832649 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146162 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 146162 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24977 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24977 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20700 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20700 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2470984 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2470984 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2617146 # number of overall misses -system.cpu0.dcache.overall_misses::total 2617146 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8102181310 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8102181310 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25003432618 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 25003432618 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 396859499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 396859499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 455692776 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 455692776 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 235500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 235500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 33105613928 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 33105613928 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 33105613928 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 33105613928 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226899 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16226899 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904000 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13904000 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457163 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 457163 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388191 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388191 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381261 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381261 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30130899 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30130899 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30588062 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30588062 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039338 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039338 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131807 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131807 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319715 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319715 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054294 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054294 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082008 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.082008 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085561 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.085561 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12692.679095 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12692.679095 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13643.328656 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 13643.328656 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15888.997838 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15888.997838 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22014.143768 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22014.143768 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63481444 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63481444 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15588806 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15588806 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12071580 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12071580 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311031 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 311031 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363190 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363190 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360636 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 360636 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27660386 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27660386 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27971417 # number of overall hits +system.cpu0.dcache.overall_hits::total 27971417 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 638107 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 638107 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1831928 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1831928 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146057 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 146057 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20607 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20607 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2470035 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2470035 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2616092 # number of overall misses +system.cpu0.dcache.overall_misses::total 2616092 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8089240805 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8089240805 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24966494558 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24966494558 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395038253 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 395038253 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453870788 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 453870788 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 394000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 394000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 33055735363 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 33055735363 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 33055735363 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 33055735363 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16226913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13903508 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13903508 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457088 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 457088 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388166 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388166 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381243 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381243 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30130421 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30130421 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30587509 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30587509 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039324 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039324 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131760 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131760 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319538 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319538 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054052 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054052 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081978 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.081978 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085528 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.085528 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12676.934754 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12676.934754 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13628.534832 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 13628.534832 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.714166 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.714166 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22025.078274 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22025.078274 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13397.745161 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13397.745161 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12649.509782 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12649.509782 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1233 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3385599 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 191316 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.614286 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17.696371 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13382.699178 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13382.699178 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12635.540097 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12635.540097 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3370028 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 68 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 191306 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.602941 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17.615903 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 512498 # number of writebacks -system.cpu0.dcache.writebacks::total 512498 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248017 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 248017 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519903 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1519903 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18417 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767920 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1767920 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767920 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1767920 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390318 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 390318 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312746 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312746 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101547 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101547 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6560 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6560 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20700 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20700 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 703064 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 703064 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 804611 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 804611 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4171307993 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4171307993 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4996022111 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4996022111 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1423316745 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1423316745 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98363500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98363500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 413570224 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 413570224 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9167330104 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9167330104 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10590646849 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10590646849 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216535499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216535499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187175989 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187175989 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403711488 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403711488 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024054 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024054 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222124 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222124 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016899 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016899 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023334 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023334 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026305 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026305 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10686.947548 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10686.947548 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15974.695475 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15974.695475 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14016.334751 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14016.334751 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14994.435976 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14994.435976 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19979.237874 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19979.237874 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 512971 # number of writebacks +system.cpu0.dcache.writebacks::total 512971 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 247929 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 247929 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519381 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1519381 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18420 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18420 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767310 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1767310 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767310 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1767310 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390178 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 390178 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312547 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312547 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101517 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101517 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20607 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20607 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 702725 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 702725 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 804242 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 804242 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170870238 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170870238 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4998082086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4998082086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1413907491 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1413907491 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97710498 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97710498 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411958212 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411958212 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 372000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 372000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9168952324 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9168952324 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10582859815 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10582859815 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217153741 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217153741 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187052487 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187052487 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404206228 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404206228 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022480 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022480 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222095 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222095 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016890 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016890 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054052 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054052 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023323 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023323 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026293 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026293 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10689.660201 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10689.660201 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15991.457560 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15991.457560 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13927.790331 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13927.790331 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14903.980781 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14903.980781 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19991.178337 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19991.178337 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13039.111808 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13039.111808 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13162.443527 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13162.443527 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13047.710447 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13047.710447 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13158.800231 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13158.800231 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -2173,15 +2178,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 33913093 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11564399 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 305039 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18757536 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 14959019 # Number of BTB hits +system.cpu1.branchPred.lookups 33910931 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11562938 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 305104 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18756149 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 14959197 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.749382 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12491385 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7180 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.756228 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12490116 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7241 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2205,25 +2210,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10162981 # DTB read hits -system.cpu1.dtb.read_misses 18754 # DTB read misses -system.cpu1.dtb.write_hits 6542585 # DTB write hits -system.cpu1.dtb.write_misses 2848 # DTB write misses +system.cpu1.dtb.read_hits 10163466 # DTB read hits +system.cpu1.dtb.read_misses 18799 # DTB read misses +system.cpu1.dtb.write_hits 6542146 # DTB write hits +system.cpu1.dtb.write_misses 2834 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch +system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 394 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10181735 # DTB read accesses -system.cpu1.dtb.write_accesses 6545433 # DTB write accesses +system.cpu1.dtb.perms_faults 406 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10182265 # DTB read accesses +system.cpu1.dtb.write_accesses 6544980 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16705566 # DTB hits -system.cpu1.dtb.misses 21602 # DTB misses -system.cpu1.dtb.accesses 16727168 # DTB accesses +system.cpu1.dtb.hits 16705612 # DTB hits +system.cpu1.dtb.misses 21633 # DTB misses +system.cpu1.dtb.accesses 16727245 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2245,8 +2250,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 43643100 # ITB inst hits -system.cpu1.itb.inst_misses 6996 # ITB inst misses +system.cpu1.itb.inst_hits 43642051 # ITB inst hits +system.cpu1.itb.inst_misses 6989 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2255,261 +2260,261 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1201 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1203 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 541 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43650096 # ITB inst accesses -system.cpu1.itb.hits 43643100 # DTB hits -system.cpu1.itb.misses 6996 # DTB misses -system.cpu1.itb.accesses 43650096 # DTB accesses -system.cpu1.numCycles 104633766 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43649040 # ITB inst accesses +system.cpu1.itb.hits 43642051 # DTB hits +system.cpu1.itb.misses 6989 # DTB misses +system.cpu1.itb.accesses 43649040 # DTB accesses +system.cpu1.numCycles 104614253 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9986103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 109171918 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 33913093 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27450404 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 91805384 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3775592 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78970 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 32292 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 198987 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 295254 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 7461 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43642483 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 116201 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2279 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104292247 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.296794 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339797 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9984991 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 109167147 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33910931 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27449313 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 91788694 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3775566 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78493 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 31389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 199715 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 294230 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 7403 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43641443 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 116254 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2254 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104272698 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.296959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339784 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 47342099 45.39% 45.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14034599 13.46% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7535653 7.23% 66.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35379896 33.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 47324573 45.39% 45.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 14035291 13.46% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7536357 7.23% 66.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35376477 33.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104292247 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.324112 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.043372 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13023476 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 61678123 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26726804 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1110708 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1753136 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 754254 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 137537 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 68065454 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1169726 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1753136 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17456234 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2244493 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 56986986 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23381097 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2470301 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 55158602 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 230731 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 262273 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 35381 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18008 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1443637 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 54999686 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 260535269 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58684549 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1692 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52221656 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2778030 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1878103 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1805469 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13100518 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10455886 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6917101 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 629442 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 825387 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 54265513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 589015 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 53909819 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 113491 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2298739 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5813202 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 48820 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104292247 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.516911 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.852558 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104272698 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.324152 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.043521 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13017206 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 61665780 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26725185 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1111466 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1753061 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 754244 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 137628 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 68061507 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1169291 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1753061 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17449719 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2249370 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 56981821 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23380432 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2458295 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 55156803 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 230618 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 263094 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 35438 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18102 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1431236 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 55002903 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 260522537 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58680311 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 52222762 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2780141 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1878015 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13100914 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10457203 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6914095 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 629486 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 832023 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 54264845 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 589076 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53908335 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 111707 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2293120 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5811368 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 48776 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104272698 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.516994 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.852584 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71040936 68.12% 68.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16527616 15.85% 83.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13076642 12.54% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3359306 3.22% 99.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 287734 0.28% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 13 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 71021448 68.11% 68.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16528398 15.85% 83.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13076148 12.54% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3359187 3.22% 99.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 287505 0.28% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104292247 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104272698 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2924694 45.09% 45.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 678 0.01% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1673523 25.80% 70.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1887909 29.10% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2925111 45.11% 45.11% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 678 0.01% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1673253 25.80% 70.93% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1885198 29.07% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36727877 68.13% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46567 0.09% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36727070 68.13% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46542 0.09% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10379543 19.25% 87.47% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6752424 12.53% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10379930 19.25% 87.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6751385 12.52% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 53909819 # Type of FU issued -system.cpu1.iq.rate 0.515224 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6486804 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.120327 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 218706402 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57161340 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 51920676 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5778 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes +system.cpu1.iq.FU_type_0::total 53908335 # Type of FU issued +system.cpu1.iq.rate 0.515306 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6484240 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.120283 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 218679535 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57155155 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51920155 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60392866 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3691 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 91423 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 60388817 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 91403 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 489842 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 678 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10158 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 359303 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 490692 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10198 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 355978 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 51794 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 70407 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 51963 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 70332 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1753136 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 542605 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 110606 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 54906673 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1753061 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 546569 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 114085 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54906076 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10455886 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6917101 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301543 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9870 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 93230 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10158 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 54900 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 127108 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 182008 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53638957 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10277477 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 249277 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10457203 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6914095 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 301562 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9838 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 96727 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10198 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54956 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 127310 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 182266 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53638370 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10277968 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 248350 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 52145 # number of nop insts executed -system.cpu1.iew.exec_refs 16965020 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11808497 # Number of branches executed -system.cpu1.iew.exec_stores 6687543 # Number of stores executed -system.cpu1.iew.exec_rate 0.512635 # Inst execution rate -system.cpu1.iew.wb_sent 53498311 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 51922462 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25227303 # num instructions producing a value -system.cpu1.iew.wb_consumers 38487680 # num instructions consuming a value +system.cpu1.iew.exec_nop 52155 # number of nop insts executed +system.cpu1.iew.exec_refs 16965083 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11807834 # Number of branches executed +system.cpu1.iew.exec_stores 6687115 # Number of stores executed +system.cpu1.iew.exec_rate 0.512725 # Inst execution rate +system.cpu1.iew.wb_sent 53497576 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51921941 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25229731 # num instructions producing a value +system.cpu1.iew.wb_consumers 38490253 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.496230 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.655464 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.496318 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655484 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3659313 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 540195 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 170379 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102361190 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.498018 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.158864 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3658728 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 540300 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170382 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102340769 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.498127 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.159192 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 76777637 75.01% 75.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14293980 13.96% 88.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6079057 5.94% 94.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 703860 0.69% 95.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1980599 1.93% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1570719 1.53% 99.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 440748 0.43% 99.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 123191 0.12% 99.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 391399 0.38% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 76762339 75.01% 75.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14287767 13.96% 88.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6080575 5.94% 94.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 703802 0.69% 95.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980023 1.93% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1565125 1.53% 99.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 446359 0.44% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 123712 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 391067 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102361190 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41391892 # Number of instructions committed -system.cpu1.commit.committedOps 50977682 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102340769 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41392870 # Number of instructions committed +system.cpu1.commit.committedOps 50978714 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16523842 # Number of memory references committed -system.cpu1.commit.loads 9966044 # Number of loads committed -system.cpu1.commit.membars 209647 # Number of memory barriers committed -system.cpu1.commit.branches 11639863 # Number of branches committed +system.cpu1.commit.refs 16524628 # Number of memory references committed +system.cpu1.commit.loads 9966511 # Number of loads committed +system.cpu1.commit.membars 209715 # Number of memory barriers committed +system.cpu1.commit.branches 11639820 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 45828051 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3366801 # Number of function calls committed. +system.cpu1.commit.int_insts 45828641 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3366594 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34404842 67.49% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 45659 0.09% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34405110 67.49% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction @@ -2537,511 +2542,503 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9966044 19.55% 87.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6557798 12.86% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9966511 19.55% 87.14% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6558117 12.86% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 50977682 # Class of committed instruction -system.cpu1.commit.bw_lim_events 391399 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 50978714 # Class of committed instruction +system.cpu1.commit.bw_lim_events 391067 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 136568898 # The number of ROB reads -system.cpu1.rob.rob_writes 111201426 # The number of ROB writes -system.cpu1.timesIdled 53211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 341519 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5543537240 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41359038 # Number of Instructions Simulated -system.cpu1.committedOps 50944828 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.529889 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.529889 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.395274 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.395274 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 56284416 # number of integer regfile reads -system.cpu1.int_regfile_writes 35740317 # number of integer regfile writes +system.cpu1.rob.rob_reads 136550879 # The number of ROB reads +system.cpu1.rob.rob_writes 111203214 # The number of ROB writes +system.cpu1.timesIdled 53373 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 341555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5543525682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41360016 # Number of Instructions Simulated +system.cpu1.committedOps 50945860 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.529357 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.529357 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.395357 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.395357 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56284604 # number of integer regfile reads +system.cpu1.int_regfile_writes 35740768 # number of integer regfile writes system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads system.cpu1.fp_regfile_writes 520 # number of floating regfile writes -system.cpu1.cc_regfile_reads 191161573 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15561298 # number of cc regfile writes -system.cpu1.misc_regfile_reads 205957562 # number of misc regfile reads -system.cpu1.misc_regfile_writes 388863 # number of misc regfile writes -system.cpu1.toL2Bus.trans_dist::ReadReq 1295443 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 865390 # Transaction distribution +system.cpu1.cc_regfile_reads 191160889 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15560745 # number of cc regfile writes +system.cpu1.misc_regfile_reads 205861724 # number of misc regfile reads +system.cpu1.misc_regfile_writes 388836 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 1295167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 865146 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 116918 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 158167 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84977 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41950 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 87258 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 79543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66388 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215693 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825104 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17440 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38012 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2096249 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897120 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25415568 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 64411288 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 836156 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1798706 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.418986 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.493393 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::Writeback 117435 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 157667 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84819 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41863 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 87089 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 79490 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66369 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215695 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 824924 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17344 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37959 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2095922 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897296 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25431436 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30740 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67228 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 64426700 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 835314 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1798151 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.418656 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.493339 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1045073 58.10% 58.10% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 753633 41.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1045344 58.13% 58.13% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 752807 41.87% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1798706 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 658940429 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1798151 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 659597923 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81408998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81215248 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 913008604 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 913005612 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 404124267 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 403790804 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9811221 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9801715 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 21199862 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 21218619 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.icache.tags.replacements 607230 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.524831 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43017967 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 607742 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 70.783272 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78622263500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524831 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 607233 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.524677 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 43016935 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 607745 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 70.781224 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524677 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 87892389 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 87892389 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43017967 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43017967 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43017967 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43017967 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43017967 # number of overall hits -system.cpu1.icache.overall_hits::total 43017967 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 624354 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 624354 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 624354 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 624354 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 624354 # number of overall misses -system.cpu1.icache.overall_misses::total 624354 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095463294 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5095463294 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5095463294 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5095463294 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5095463294 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5095463294 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43642321 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43642321 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43642321 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43642321 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43642321 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43642321 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8161.176663 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8161.176663 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8161.176663 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8161.176663 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 277985 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 87890334 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87890334 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 43016935 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 43016935 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 43016935 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 43016935 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 43016935 # number of overall hits +system.cpu1.icache.overall_hits::total 43016935 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 624358 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 624358 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 624358 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 624358 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 624358 # number of overall misses +system.cpu1.icache.overall_misses::total 624358 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5094140300 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5094140300 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5094140300 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5094140300 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5094140300 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5094140300 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641293 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43641293 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43641293 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43641293 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43641293 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43641293 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014307 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014307 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014307 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014307 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014307 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014307 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8159.005410 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8159.005410 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8159.005410 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8159.005410 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 274240 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 36153 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 36121 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.689127 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.592259 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16607 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 16607 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 16607 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 16607 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 16607 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 16607 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607747 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 607747 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 607747 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 607747 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 607747 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 607747 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4104727229 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104727229 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104727229 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4104727229 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104727229 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4104727229 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7919750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7919750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7919750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7919750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16610 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 16610 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 16610 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 16610 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 16610 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 16610 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607748 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 607748 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 607748 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 607748 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 607748 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 607748 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4102836710 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4102836710 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4102836710 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4102836710 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4102836710 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4102836710 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.006567 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6750.884758 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841798 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 42982 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639721 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 43013 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841881 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43251 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4640074 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42977 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6040 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 110042 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564522 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6024 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109555 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564023 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85604 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15613.661542 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 844840 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100686 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.390839 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 85866 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15600.635673 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 846675 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 100980 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.384581 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5991.162043 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.384982 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.931077 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 706.431382 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1962.742096 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6937.009962 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.365672 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000878 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.043117 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.119796 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.423401 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952982 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9479 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5582 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8003 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1153 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6012.739780 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.101116 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.182282 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 726.495477 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1966.711133 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.405886 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.366989 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000555 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000072 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.044342 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.120039 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.420191 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.952187 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9526 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5563 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8131 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1089 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4223 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 941 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.578552 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001282 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.340698 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 16875679 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 16875679 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16408 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7497 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601881 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 101311 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 727097 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 116917 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 116917 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 836 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 836 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28901 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28901 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16408 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7497 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 601881 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 130212 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 755998 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16408 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7497 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 601881 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 130212 # number of overall hits -system.cpu1.l2cache.overall_hits::total 755998 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 474 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5861 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 72219 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 78825 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28423 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28423 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22608 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22608 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32938 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32938 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 474 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 5861 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 105157 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 111763 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 474 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 5861 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 105157 # number of overall misses -system.cpu1.l2cache.overall_misses::total 111763 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10500499 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5483500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 182847956 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610079123 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1808911078 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536990378 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 536990378 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 443102047 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443102047 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 554000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 554000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1287438029 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1287438029 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10500499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5483500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 182847956 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2897517152 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3096349107 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10500499 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5483500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 182847956 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2897517152 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3096349107 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16882 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7768 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607742 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173530 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 805922 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 116918 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 116918 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30684 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30684 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23444 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23444 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61839 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 61839 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16882 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7768 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 607742 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 235369 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 867761 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16882 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7768 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 607742 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 235369 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 867761 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.034887 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009644 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.416176 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.097807 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926313 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926313 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964341 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964341 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 415 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4194 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 954 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.581421 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.339539 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 16877479 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 16877479 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16335 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7409 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601802 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 101305 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 726851 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 117435 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 117435 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2252 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2252 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 837 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 837 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28910 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 28910 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16335 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7409 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 601802 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 130215 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 755761 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16335 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7409 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 601802 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130215 # number of overall hits +system.cpu1.l2cache.overall_hits::total 755761 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5943 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 72078 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 78769 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28388 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28388 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22558 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22558 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32913 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32913 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 5943 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 104991 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 111682 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 5943 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 104991 # number of overall misses +system.cpu1.l2cache.overall_misses::total 111682 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10433249 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5666498 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 181785702 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1611031625 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1808917074 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536972883 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 536972883 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442531028 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442531028 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 437999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 437999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1278690285 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1278690285 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10433249 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5666498 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 181785702 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2889721910 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3087607359 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10433249 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5666498 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 181785702 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2889721910 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3087607359 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16807 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7685 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607745 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173383 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 805620 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 117435 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 117435 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30640 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30640 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23395 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23395 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61823 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61823 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16807 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7685 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 607745 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 235206 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 867443 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16807 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7685 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 607745 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 235206 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 867443 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035914 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009779 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415715 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926501 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926501 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964223 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964223 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532641 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532641 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.034887 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009644 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446775 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.128795 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.034887 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009644 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446775 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.128795 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20234.317343 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31197.399079 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22294.397915 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22948.443742 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18892.811385 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18892.811385 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19599.347443 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19599.347443 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 184666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 184666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39086.709242 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39086.709242 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 27704.599080 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 27704.599080 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 23432 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532375 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532375 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035914 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009779 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446379 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.128749 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035914 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009779 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446379 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.128749 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20530.789855 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30588.204947 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22351.225409 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22964.834821 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18915.488340 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18915.488340 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19617.476195 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.476195 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 218999.500000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 218999.500000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38850.614803 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38850.614803 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 27646.418931 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 27646.418931 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 22060 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 464 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 480 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.958333 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 40723 # number of writebacks -system.cpu1.l2cache.writebacks::total 40723 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 40786 # number of writebacks +system.cpu1.l2cache.writebacks::total 40786 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1292 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 76 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1310 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 1310 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1367 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 84 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1465 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1237 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 1237 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1292 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1386 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 2692 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1367 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1321 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1292 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1386 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 2692 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 474 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 257 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4569 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72143 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 77443 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 110035 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28423 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28423 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22608 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22608 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31628 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 31628 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 474 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 257 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4569 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103771 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 109071 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 474 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 257 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4569 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103771 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 219106 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3513000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 126144777 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1103468683 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1240306961 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3485961286 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417373575 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417373575 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308955268 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308955268 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 463000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 463000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944601401 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944601401 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3513000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 126144777 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2048070084 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2184908362 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3513000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 126144777 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2048070084 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 5670869648 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7061250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2181994006 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189055256 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737322501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737322501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7061250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919316507 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926377757 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415738 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096092 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1367 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1321 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 2702 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 472 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4576 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71994 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 77304 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 109552 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28388 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28388 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22558 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22558 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31676 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 31676 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 472 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4576 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103670 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 108980 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 472 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4576 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103670 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 218532 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3660000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 123437534 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105460943 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1239685228 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3461172800 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 416881074 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 416881074 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308366284 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308366284 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 367999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 367999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944446910 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944446910 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3660000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 123437534 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2049907853 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2184132138 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3660000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 123437534 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2049907853 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5645304938 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182190507 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189531257 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737661499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737661499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919852006 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927192756 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415231 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.095956 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926313 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926313 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964341 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964341 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926501 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926501 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964223 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964223 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.511457 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.511457 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125692 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512366 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512366 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125634 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.252496 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15295.575219 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16015.740106 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31680.476994 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14684.360377 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14684.360377 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.749646 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.749646 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 154333.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 154333.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29865.985867 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29865.985867 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20031.982488 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25881.854664 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251927 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15354.903784 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.495240 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31593.880532 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14685.116035 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14685.116035 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.930136 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.930136 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29815.851433 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29815.851433 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20041.586878 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25832.852571 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -3051,191 +3048,191 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 191151 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.645791 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15740842 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191475 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 82.208341 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 102871069000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.645791 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 191071 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.558673 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15741841 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 82.247922 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558673 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32982505 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32982505 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9573878 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9573878 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5910219 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5910219 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49544 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49544 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79107 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79107 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70933 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70933 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15484097 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15484097 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15533641 # number of overall hits -system.cpu1.dcache.overall_hits::total 15533641 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 219762 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 219762 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 398432 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 398432 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30092 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30092 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18147 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18147 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23447 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23447 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 618194 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 618194 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 648286 # number of overall misses -system.cpu1.dcache.overall_misses::total 648286 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3451433990 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3451433990 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8738929077 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8738929077 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362617750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 362617750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 543339293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 543339293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 593000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 593000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12190363067 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12190363067 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12190363067 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12190363067 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793640 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9793640 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308651 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6308651 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79636 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79636 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97254 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97254 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94380 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94380 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16102291 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16102291 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16181927 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16181927 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022439 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022439 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063156 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.063156 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377869 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377869 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186594 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186594 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248432 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248432 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038392 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038392 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040062 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040062 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15705.326626 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15705.326626 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21933.301233 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21933.301233 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19982.242244 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19982.242244 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.083678 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.083678 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 32983753 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32983753 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9574420 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9574420 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5910665 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5910665 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49536 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49536 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79144 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79144 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71002 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71002 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15485085 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15485085 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15534621 # number of overall hits +system.cpu1.dcache.overall_hits::total 15534621 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 219558 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 219558 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 398300 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 398300 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30127 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30127 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18119 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18119 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23397 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23397 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 617858 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 617858 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 647985 # number of overall misses +system.cpu1.dcache.overall_misses::total 647985 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453411003 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3453411003 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8719629262 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8719629262 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362936751 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 362936751 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542268315 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 542268315 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 468000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 468000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12173040265 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12173040265 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12173040265 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12173040265 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793978 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9793978 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308965 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6308965 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79663 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79663 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97263 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97263 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94399 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94399 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16102943 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16102943 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16182606 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16182606 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022418 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022418 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063132 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.063132 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378181 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378181 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186289 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186289 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247852 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247852 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038369 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038369 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040042 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040042 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15728.923578 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15728.923578 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21892.114642 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21892.114642 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.727468 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.727468 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23176.831004 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23176.831004 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19719.316375 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19719.316375 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18803.989392 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18803.989392 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1116254 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 47 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39673 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.191489 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.136365 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19702.003154 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19702.003154 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18785.990825 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18785.990825 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1110000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39631 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.008377 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116918 # number of writebacks -system.cpu1.dcache.writebacks::total 116918 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79804 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79804 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306588 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306588 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13195 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13195 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 386392 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 386392 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 386392 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 386392 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139958 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 139958 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91844 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91844 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28639 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28639 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23447 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23447 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 231802 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 231802 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 260441 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 260441 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829576308 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829576308 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2203829941 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2203829941 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493924497 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493924497 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86545750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86545750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 495264707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495264707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 567000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 567000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4033406249 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4033406249 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4527330746 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4527330746 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298504494 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298504494 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826458496 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826458496 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4124962990 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4124962990 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014291 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014291 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014558 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014558 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359624 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359624 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050918 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050918 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248432 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248432 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014396 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014396 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016095 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13072.323897 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13072.323897 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23995.361058 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23995.361058 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17246.569259 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17246.569259 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17476.928514 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17476.928514 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21122.732418 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21122.732418 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 117436 # number of writebacks +system.cpu1.dcache.writebacks::total 117436 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79714 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 79714 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306518 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306518 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 386232 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 386232 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 386232 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 386232 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139844 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 139844 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91782 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91782 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28626 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28626 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4932 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4932 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23397 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23397 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 231626 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 231626 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 260252 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 260252 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827153559 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827153559 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2193887187 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2193887187 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494621242 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494621242 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494306685 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494306685 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 448000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 448000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4021040746 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4021040746 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4515661988 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4515661988 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298831492 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298831492 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826840995 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826840995 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125672487 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125672487 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014548 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014548 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359339 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359339 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050708 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050708 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247852 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247852 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014384 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014384 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016082 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.016082 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13065.655724 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13065.655724 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23903.240145 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23903.240145 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17278.741075 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17278.741075 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17627.686537 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17627.686537 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21126.925888 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21126.925888 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17400.221952 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.221952 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17383.325767 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17383.325767 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17360.057791 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17360.057791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17351.113490 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17351.113490 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -3244,57 +3241,57 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 36453 # number of replacements -system.iocache.tags.tagsinuse 14.560241 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.560234 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254140751000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.560241 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.560234 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328407 # Number of tag accesses -system.iocache.tags.data_accesses 328407 # Number of data accesses +system.iocache.tags.tag_accesses 328359 # Number of tag accesses +system.iocache.tags.data_accesses 328359 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses system.iocache.ReadReq_misses::total 247 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 21 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 21 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 15 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 15 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses system.iocache.demand_misses::total 247 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 247 # number of overall misses system.iocache.overall_misses::total 247 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36245 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36245 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36239 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36239 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000579 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000579 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000414 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000414 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124827.437247 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -3309,32 +3306,32 @@ system.iocache.demand_mshr_misses::realview.ide 247 system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2249753293 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2249753293 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2254879547 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2254879547 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2758 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 65705e13f..6d0567284 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index a9f72b356..4fa33566b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:06:55 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:28:40 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x5387b00 0x5387b00 + 0: system.cpu.isa: ISA system set to: 0x443e680 0x443e680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 @@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2826845674500 because m5_exit instruction encountered +Exiting @ tick 2826844351500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 303143490..b8a9581f1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826846 # Number of seconds simulated -sim_ticks 2826845674500 # Number of ticks simulated -final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826844 # Number of seconds simulated +sim_ticks 2826844351500 # Number of ticks simulated +final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98010 # Simulator instruction rate (inst/s) -host_op_rate 118881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2448127815 # Simulator tick rate (ticks/s) -host_mem_usage 558668 # Number of bytes of host memory used -host_seconds 1154.70 # Real time elapsed on the host -sim_insts 113172343 # Number of instructions simulated -sim_ops 137271263 # Number of ops (including micro ops) simulated +host_inst_rate 97337 # Simulator instruction rate (inst/s) +host_op_rate 118064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2430592330 # Simulator tick rate (ticks/s) +host_mem_usage 558776 # Number of bytes of host memory used +host_seconds 1163.03 # Real time elapsed on the host +sim_insts 113205077 # Number of instructions simulated +sim_ops 137311743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory @@ -28,110 +28,110 @@ system.realview.nvmem.bw_total::total 45 # To system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory -system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory +system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory +system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory -system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory +system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory +system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 172183 # Number of read requests accepted -system.physmem.writeReqs 131246 # Number of write requests accepted -system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 172165 # Number of read requests accepted +system.physmem.writeReqs 131231 # Number of write requests accepted +system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10992 # Per bank write bursts +system.physmem.perBankRdBursts::0 10989 # Per bank write bursts system.physmem.perBankRdBursts::1 10130 # Per bank write bursts -system.physmem.perBankRdBursts::2 11200 # Per bank write bursts -system.physmem.perBankRdBursts::3 11425 # Per bank write bursts +system.physmem.perBankRdBursts::2 11201 # Per bank write bursts +system.physmem.perBankRdBursts::3 11419 # Per bank write bursts system.physmem.perBankRdBursts::4 13122 # Per bank write bursts -system.physmem.perBankRdBursts::5 10553 # Per bank write bursts -system.physmem.perBankRdBursts::6 11175 # Per bank write bursts -system.physmem.perBankRdBursts::7 11538 # Per bank write bursts -system.physmem.perBankRdBursts::8 10354 # Per bank write bursts -system.physmem.perBankRdBursts::9 11059 # Per bank write bursts -system.physmem.perBankRdBursts::10 10499 # Per bank write bursts +system.physmem.perBankRdBursts::5 10546 # Per bank write bursts +system.physmem.perBankRdBursts::6 11171 # Per bank write bursts +system.physmem.perBankRdBursts::7 11539 # Per bank write bursts +system.physmem.perBankRdBursts::8 10356 # Per bank write bursts +system.physmem.perBankRdBursts::9 11055 # Per bank write bursts +system.physmem.perBankRdBursts::10 10496 # Per bank write bursts system.physmem.perBankRdBursts::11 9259 # Per bank write bursts system.physmem.perBankRdBursts::12 10183 # Per bank write bursts system.physmem.perBankRdBursts::13 10761 # Per bank write bursts system.physmem.perBankRdBursts::14 10049 # Per bank write bursts -system.physmem.perBankRdBursts::15 9748 # Per bank write bursts +system.physmem.perBankRdBursts::15 9745 # Per bank write bursts system.physmem.perBankWrBursts::0 8312 # Per bank write bursts system.physmem.perBankWrBursts::1 7765 # Per bank write bursts system.physmem.perBankWrBursts::2 8704 # Per bank write bursts -system.physmem.perBankWrBursts::3 8608 # Per bank write bursts +system.physmem.perBankWrBursts::3 8604 # Per bank write bursts system.physmem.perBankWrBursts::4 7611 # Per bank write bursts -system.physmem.perBankWrBursts::5 7956 # Per bank write bursts -system.physmem.perBankWrBursts::6 8259 # Per bank write bursts +system.physmem.perBankWrBursts::5 7949 # Per bank write bursts +system.physmem.perBankWrBursts::6 8258 # Per bank write bursts system.physmem.perBankWrBursts::7 8579 # Per bank write bursts -system.physmem.perBankWrBursts::8 7842 # Per bank write bursts -system.physmem.perBankWrBursts::9 8532 # Per bank write bursts -system.physmem.perBankWrBursts::10 7844 # Per bank write bursts +system.physmem.perBankWrBursts::8 7843 # Per bank write bursts +system.physmem.perBankWrBursts::9 8531 # Per bank write bursts +system.physmem.perBankWrBursts::10 7842 # Per bank write bursts system.physmem.perBankWrBursts::11 6872 # Per bank write bursts system.physmem.perBankWrBursts::12 7611 # Per bank write bursts system.physmem.perBankWrBursts::13 8198 # Per bank write bursts system.physmem.perBankWrBursts::14 7543 # Per bank write bursts -system.physmem.perBankWrBursts::15 7119 # Per bank write bursts +system.physmem.perBankWrBursts::15 7118 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2826845408500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 2826844140500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168635 # Read request sizes (log2) +system.physmem.readPktSize::6 168617 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126865 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126850 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -174,116 +174,118 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62171 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.209036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.794963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.700925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23473 37.76% 37.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14721 23.68% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6339 10.20% 71.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3681 5.92% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2625 4.22% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1528 2.46% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1121 1.80% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1145 1.84% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.317098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads -system.physmem.totQLat 2068507750 # Total ticks spent queuing -system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads +system.physmem.totQLat 2071957750 # Total ticks spent queuing +system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s @@ -292,87 +294,87 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing -system.physmem.readRowHits 142034 # Number of row buffer hits during reads -system.physmem.writeRowHits 95196 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes -system.physmem.avgGap 9316332.35 # Average gap between requests -system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states -system.physmem.memoryStateTime::REF 94394560000 # Time in different power states +system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing +system.physmem.readRowHits 141999 # Number of row buffer hits during reads +system.physmem.writeRowHits 95218 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes +system.physmem.avgGap 9317341.50 # Average gap between requests +system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states +system.physmem.memoryStateTime::REF 94394300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states +system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.338580 # Core power per rank (mW) -system.physmem.averagePower::1 669.240432 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 67851 # Transaction distribution -system.membus.trans_dist::ReadResp 67850 # Transaction distribution +system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.335912 # Core power per rank (mW) +system.physmem.averagePower::1 669.239814 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 67834 # Transaction distribution +system.membus.trans_dist::ReadResp 67833 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 90641 # Transaction distribution +system.membus.trans_dist::Writeback 90626 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135128 # Transaction distribution -system.membus.trans_dist::ReadExResp 135128 # Transaction distribution +system.membus.trans_dist::ReadExReq 135127 # Transaction distribution +system.membus.trans_dist::ReadExResp 135127 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 205 # Total snoops (count) -system.membus.snoop_fanout::samples 300256 # Request fanout histogram +system.membus.snoop_fanout::samples 300222 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 300256 # Request fanout histogram -system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 300222 # Request fanout histogram +system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -413,9 +415,8 @@ system.cf0.dma_write_bytes 2318336 # Nu system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59035 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -506,24 +507,24 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46931803 # Number of BP lookups -system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits +system.cpu.branchPred.lookups 46964481 # Number of BP lookups +system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -547,10 +548,10 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25464394 # DTB read hits -system.cpu.dtb.read_misses 60419 # DTB read misses -system.cpu.dtb.write_hits 19915991 # DTB write hits -system.cpu.dtb.write_misses 9380 # DTB write misses +system.cpu.dtb.read_hits 25471928 # DTB read hits +system.cpu.dtb.read_misses 60410 # DTB read misses +system.cpu.dtb.write_hits 19919780 # DTB write hits +system.cpu.dtb.write_misses 9388 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID @@ -559,13 +560,13 @@ system.cpu.dtb.flush_entries 4324 # Nu system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25524813 # DTB read accesses -system.cpu.dtb.write_accesses 19925371 # DTB write accesses +system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25532338 # DTB read accesses +system.cpu.dtb.write_accesses 19929168 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45380385 # DTB hits -system.cpu.dtb.misses 69799 # DTB misses -system.cpu.dtb.accesses 45450184 # DTB accesses +system.cpu.dtb.hits 45391708 # DTB hits +system.cpu.dtb.misses 69798 # DTB misses +system.cpu.dtb.accesses 45461506 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -587,8 +588,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66292387 # ITB inst hits -system.cpu.itb.inst_misses 11931 # ITB inst misses +system.cpu.itb.inst_hits 66240861 # ITB inst hits +system.cpu.itb.inst_misses 11936 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -601,94 +602,94 @@ system.cpu.itb.flush_entries 3095 # Nu system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66304318 # ITB inst accesses -system.cpu.itb.hits 66292387 # DTB hits -system.cpu.itb.misses 11931 # DTB misses -system.cpu.itb.accesses 66304318 # DTB accesses -system.cpu.numCycles 260551438 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66252797 # ITB inst accesses +system.cpu.itb.hits 66240861 # DTB hits +system.cpu.itb.misses 11936 # DTB misses +system.cpu.itb.accesses 66252797 # DTB accesses +system.cpu.numCycles 260549216 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125305 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254586778 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563008 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882453 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -696,9 +697,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -727,13 +728,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -761,97 +762,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued -system.cpu.iq.rate 0.550119 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued +system.cpu.iq.rate 0.550285 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200946 # number of nop insts executed -system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed -system.cpu.iew.exec_branches 26532601 # Number of branches executed -system.cpu.iew.exec_stores 20878795 # Number of stores executed -system.cpu.iew.exec_rate 0.546502 # Inst execution rate -system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63282838 # num instructions producing a value -system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value +system.cpu.iew.exec_nop 200927 # number of nop insts executed +system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed +system.cpu.iew.exec_branches 26544157 # Number of branches executed +system.cpu.iew.exec_stores 20882594 # Number of stores executed +system.cpu.iew.exec_rate 0.546668 # Inst execution rate +system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63301722 # num instructions producing a value +system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back +system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113327248 # Number of instructions committed -system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113359982 # Number of instructions committed +system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45519928 # Number of memory references committed -system.cpu.commit.loads 24920655 # Number of loads committed -system.cpu.commit.membars 814679 # Number of memory barriers committed -system.cpu.commit.branches 26048896 # Number of branches committed +system.cpu.commit.refs 45531388 # Number of memory references committed +system.cpu.commit.loads 24928306 # Number of loads committed +system.cpu.commit.membars 814674 # Number of memory barriers committed +system.cpu.commit.branches 26060542 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120245785 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892513 # Number of function calls committed. +system.cpu.commit.int_insts 120282409 # Number of committed integer instructions. +system.cpu.commit.function_calls 4896404 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -879,55 +880,55 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction -system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction +system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373356629 # The number of ROB reads -system.cpu.rob.rob_writes 292965429 # The number of ROB writes -system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393139912 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113172343 # Number of Instructions Simulated -system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155828809 # number of integer regfile reads -system.cpu.int_regfile_writes 88634133 # number of integer regfile writes +system.cpu.rob.rob_reads 373371044 # The number of ROB reads +system.cpu.rob.rob_writes 293051212 # The number of ROB writes +system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113205077 # Number of Instructions Simulated +system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155870959 # number of integer regfile reads +system.cpu.int_regfile_writes 88663005 # number of integer regfile writes system.cpu.fp_regfile_reads 9591 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503010933 # number of cc regfile reads -system.cpu.cc_regfile_writes 53185281 # number of cc regfile writes -system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution +system.cpu.cc_regfile_reads 503160195 # number of cc regfile reads +system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes +system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795251 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31166 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128727 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121302864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98352737 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46636 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219917661 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65503 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3561986 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65488 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -936,31 +937,31 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3525536 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36450 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3525412 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3561986 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503006527 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849563150 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334496858 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19512240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74894955 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1894110 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373809 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64308148 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894622 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.942469 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1894038 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373809 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -969,250 +970,250 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 170 system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68184330 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68184330 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64308148 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64308148 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64308148 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64308148 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64308148 # number of overall hits -system.cpu.icache.overall_hits::total 64308148 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981542 # number of overall misses -system.cpu.icache.overall_misses::total 1981542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763338374 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26763338374 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26763338374 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26763338374 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26763338374 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26763338374 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66289690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66289690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66289690 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66289690 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66289690 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66289690 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029892 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029892 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029892 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029892 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029892 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029892 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.319005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.319005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.319005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.319005 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2089 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68132740 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68132740 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64256715 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64256715 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64256715 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64256715 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64256715 # number of overall hits +system.cpu.icache.overall_hits::total 64256715 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981457 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981457 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981457 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981457 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981457 # number of overall misses +system.cpu.icache.overall_misses::total 1981457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763157130 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26763157130 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26763157130 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26763157130 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26763157130 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26763157130 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66238172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66238172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66238172 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66238172 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66238172 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66238172 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.806925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.806925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.806925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.806925 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.086538 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86900 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86900 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86900 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86900 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86900 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86900 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894642 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894642 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894642 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894642 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894642 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894642 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22157720096 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22157720096 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22157720096 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22157720096 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22157720096 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22157720096 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202542500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202542500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202542500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 202542500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028581 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028581 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028581 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11694.937669 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11694.937669 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86887 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86887 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86887 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86887 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86887 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86887 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22160408840 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22160408840 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22160408840 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22160408840 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22160408840 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22160408840 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.801301 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.801301 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98637 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65077.786040 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3021048 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163850 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.437888 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 98619 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65077.788296 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3020959 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.439371 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49563.565409 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.530935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.672892 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.756280 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612651 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617936 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157326 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.079203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157327 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.079218 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7016 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28438268 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28438268 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53837 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11652 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874630 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528067 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2468186 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 695424 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 695424 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 28437367 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28437367 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53840 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1874571 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528036 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2468107 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 695414 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 695414 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 159691 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 159691 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53837 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 11652 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1874630 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 687758 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2627877 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53837 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 11652 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1874630 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 687758 # number of overall hits -system.cpu.l2cache.overall_hits::total 2627877 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 159688 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 159688 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53840 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11660 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1874571 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 687724 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2627795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53840 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11660 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1874571 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 687724 # number of overall hits +system.cpu.l2cache.overall_hits::total 2627795 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 19979 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 13624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33629 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2734 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2734 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 19966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 13620 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33612 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2733 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2733 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19979 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 150561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 170566 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19966 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 150557 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 170549 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19979 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 150561 # number of overall misses -system.cpu.l2cache.overall_misses::total 170566 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1661750 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 19966 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 150557 # number of overall misses +system.cpu.l2cache.overall_misses::total 170549 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1458500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1496766000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1081319750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2580283750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1500107250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078643000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2580745000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9921795191 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9921795191 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1661750 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9922806190 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9922806190 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1458500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1496766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11003114941 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12502078941 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1661750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1500107250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11001449190 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12503551190 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1458500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1496766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11003114941 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12502078941 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53856 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11659 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894609 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 541691 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2501815 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 695424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 695424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 1500107250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11001449190 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12503551190 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53859 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11667 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894537 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 541656 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2501719 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 695414 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 695414 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2767 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2767 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11659 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1894609 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 838319 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2798443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11659 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1894609 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 838319 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2798443 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53859 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 11667 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1894537 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 838281 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2798344 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53859 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11667 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1894537 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 838281 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2798344 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010545 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013442 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987717 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987717 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025145 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013436 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987712 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987712 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461646 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461646 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461650 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461650 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010545 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.179599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060950 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.179602 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060946 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010545 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.179599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060950 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87460.526316 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.179602 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060946 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76763.157895 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74916.962811 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79368.742660 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76727.935710 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.231529 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.231529 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75133.088751 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79195.521292 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76780.465310 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.309550 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.309550 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72455.181514 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72455.181514 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72462.564464 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72462.564464 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73297.602928 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73313.541504 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73297.602928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73313.541504 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1221,8 +1222,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 90641 # number of writebacks -system.cpu.l2cache.writebacks::total 90641 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 90626 # number of writebacks +system.cpu.l2cache.writebacks::total 90626 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits @@ -1234,96 +1235,96 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 112 system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19954 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13512 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33492 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2734 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19941 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13508 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33475 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2733 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2733 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 150449 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 170429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19941 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 150445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 170412 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19954 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 150449 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 170429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1426250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19941 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 150445 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 170412 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1223500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1244689750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 905485750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152053000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27405734 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27405734 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1248209500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902938000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152822250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27396733 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27396733 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8208319809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8208319809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1426250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8209305810 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8209305810 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1223500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1244689750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9113805559 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10360372809 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1426250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1248209500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112243810 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10362128060 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1223500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1244689750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9113805559 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10360372809 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157860000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387400000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545260000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107351500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107351500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157860000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494751500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652611500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1248209500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112243810 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10362128060 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387481250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545358250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107341000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107341000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494822250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652699250 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024944 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013387 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987717 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987717 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024938 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987712 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987712 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461646 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461646 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461650 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461650 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060901 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060897 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060901 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060897 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62377.956801 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67013.451007 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64255.732712 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.043160 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.043160 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62595.130635 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66844.684631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64311.344287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59942.307842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59942.307842 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59949.508241 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59949.508241 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1333,13 +1334,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 837784 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958472 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40159350 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838296 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.905931 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244993250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958472 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 837746 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1347,170 +1348,170 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179375223 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179375223 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23322313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23322313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15585229 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15585229 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346650 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346650 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441994 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441994 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460302 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460302 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38907542 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38907542 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39254192 # number of overall hits -system.cpu.dcache.overall_hits::total 39254192 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700487 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700487 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3573434 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3573434 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177076 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177076 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26736 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26736 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits +system.cpu.dcache.overall_hits::total 39265074 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4273921 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4273921 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4450997 # number of overall misses -system.cpu.dcache.overall_misses::total 4450997 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9902093641 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9902093641 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135168862785 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135168862785 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356751499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 356751499 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses +system.cpu.dcache.overall_misses::total 4451402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145070956426 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145070956426 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145070956426 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145070956426 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24022800 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24022800 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19158663 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19158663 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523726 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523726 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468730 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468730 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460307 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460307 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43181463 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43181463 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43705189 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43705189 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029159 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029159 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186518 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186518 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057039 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098976 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33943.293857 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33943.293857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.912650 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks -system.cpu.dcache.writebacks::total 695424 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks +system.cpu.dcache.writebacks::total 695414 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3560465 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414191 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299265 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713456 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832762 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5344701667 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713418 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17226829872 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1519,57 +1520,53 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328020 # Number of tag accesses -system.iocache.tags.data_accesses 328020 # Number of data accesses +system.iocache.tags.tag_accesses 327996 # Number of tag accesses +system.iocache.tags.data_accesses 327996 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses system.iocache.demand_misses::total 220 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 220 # number of overall misses system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1584,28 +1581,28 @@ system.iocache.demand_mshr_misses::realview.ide 220 system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index b371e25ee..c717b9b07 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.realview.vram system.physmem system.realview.nvmem +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 6a3bc0040..ed22091e6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:14:55 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:41:22 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x5395b00 0x5395b00 - 0: system.cpu1.isa: ISA system set to: 0x5395b00 0x5395b00 - 0: system.cpu2.isa: ISA system set to: 0x5395b00 0x5395b00 + 0: system.cpu0.isa: ISA system set to: 0x40eb680 0x40eb680 + 0: system.cpu1.isa: ISA system set to: 0x40eb680 0x40eb680 + 0: system.cpu2.isa: ISA system set to: 0x40eb680 0x40eb680 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3943053d7..271261101 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.817969 # Nu sim_ticks 2817968959500 # Number of ticks simulated final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310224 # Simulator instruction rate (inst/s) -host_op_rate 376688 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6925358539 # Simulator tick rate (ticks/s) -host_mem_usage 560716 # Number of bytes of host memory used -host_seconds 406.91 # Real time elapsed on the host -sim_insts 126231917 # Number of instructions simulated -sim_ops 153276568 # Number of ops (including micro ops) simulated +host_inst_rate 311387 # Simulator instruction rate (inst/s) +host_op_rate 378101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6951332904 # Simulator tick rate (ticks/s) +host_mem_usage 560824 # Number of bytes of host memory used +host_seconds 405.39 # Real time elapsed on the host +sim_insts 126231916 # Number of instructions simulated +sim_ops 153276567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory @@ -131,7 +131,7 @@ system.physmem.perBankWrBursts::14 3934 # Pe system.physmem.perBankWrBursts::15 3898 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 2816402816000 # Total gap between requests +system.physmem.totGap 2816402817000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) @@ -298,12 +298,12 @@ system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Wr system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads -system.physmem.totQLat 1185317250 # Total ticks spent queuing -system.physmem.totMemAccLat 2923442250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1185318250 # Total ticks spent queuing +system.physmem.totMemAccLat 2923443250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12786.59 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12786.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31536.59 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31536.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s @@ -318,12 +318,12 @@ system.physmem.readRowHits 76736 # Nu system.physmem.writeRowHits 50876 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes -system.physmem.avgGap 17540686.68 # Average gap between requests +system.physmem.avgGap 17540686.69 # Average gap between requests system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2704844342250 # Time in different power states +system.physmem.memoryStateTime::IDLE 2704844337250 # Time in different power states system.physmem.memoryStateTime::REF 94098160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 19026363250 # Time in different power states +system.physmem.memoryStateTime::ACT 19026368250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ) @@ -335,28 +335,28 @@ system.physmem.writeEnergy::0 224758800 # En system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 70810444215 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 69981019830 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1628666804250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1629394369500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1884329287755 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1884181443675 # Total energy per rank (pJ) +system.physmem.actBackEnergy::0 70810447635 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 69981022395 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1628666801250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1629394367250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1884329288175 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1884181443990 # Total energy per rank (pJ) system.physmem.averagePower::0 668.683537 # Core power per rank (mW) system.physmem.averagePower::1 668.631072 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74237 # Transaction distribution -system.membus.trans_dist::ReadResp 74236 # Transaction distribution +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74236 # Transaction distribution +system.membus.trans_dist::ReadResp 74235 # Transaction distribution system.membus.trans_dist::WriteReq 27571 # Transaction distribution system.membus.trans_dist::WriteResp 27571 # Transaction distribution system.membus.trans_dist::Writeback 92896 # Transaction distribution @@ -368,21 +368,21 @@ system.membus.trans_dist::UpgradeResp 4551 # Tr system.membus.trans_dist::ReadExReq 137042 # Transaction distribution system.membus.trans_dist::ReadExResp 137042 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 579193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 579191 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652018 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17102703 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17102699 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19429167 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19429163 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 125 # Total snoops (count) system.membus.snoop_fanout::samples 304844 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram @@ -407,16 +407,16 @@ system.membus.respLayer3.occupancy 23918727 # La system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 100821 # number of replacements -system.l2c.tags.tagsinuse 65118.790978 # Cycle average of tags in use +system.l2c.tags.tagsinuse 65118.790980 # Cycle average of tags in use system.l2c.tags.total_refs 2895106 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 166061 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 17.433991 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49797.187016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49797.187018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 5291.837037 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2854.503749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2854.503750 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 1121.421966 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 949.242692 # Average occupied blocks per requestor @@ -552,23 +552,23 @@ system.l2c.ReadReq_miss_latency::total 1331208246 # nu system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 325486 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 994399991 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 994400991 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 4662408726 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5656808717 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5656809717 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 148548750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1186690241 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1186691241 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.dtb.walker 7339250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 615969000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 5029395222 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6988016963 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6988017963 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 148548750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1186690241 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1186691241 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.dtb.walker 7339250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 615969000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 5029395222 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6988016963 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6988017963 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 4967 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 2546 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 866509 # number of ReadReq accesses(hits+misses) @@ -675,23 +675,23 @@ system.l2c.ReadReq_avg_miss_latency::total 39244.369152 # system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 62.838798 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 305.333959 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 128.260950 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70464.851970 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70464.922832 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74749.234072 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 40733.682696 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 40733.689897 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 72604.472141 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71114.654581 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71114.714508 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 76309.340932 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 75122.783343 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 40441.317193 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 40441.322980 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 72604.472141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71114.654581 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71114.714508 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 76309.340932 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 75122.783343 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 40441.317193 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 40441.322980 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -752,23 +752,23 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10666566 system.l2c.UpgradeReq_mshr_miss_latency::total 14326932 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 813880009 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 813881009 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3892439774 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4706319783 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4706320783 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 122695750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 973958759 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 973959759 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 514237000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 4200079770 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5817197029 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5817198029 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 122695750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 973958759 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 973959759 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 514237000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 4200079770 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5817197029 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5817198029 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 943995500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1580248500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 2524244000 # number of ReadReq MSHR uncacheable cycles @@ -819,23 +819,23 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.903132 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.973994 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.780757 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.793832 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -883,8 +883,8 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2443721 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2443718 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2443720 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2443717 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution @@ -894,16 +894,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 15 # Tr system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616609 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616607 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6218459 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187260 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6218457 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187256 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213301515 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213301511 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 51755 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram @@ -1087,7 +1087,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 67954631 # ITB inst hits +system.cpu0.itb.inst_hits 67954632 # ITB inst hits system.cpu0.itb.inst_misses 2810 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1104,10 +1104,10 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67957441 # ITB inst accesses -system.cpu0.itb.hits 67954631 # DTB hits +system.cpu0.itb.inst_accesses 67957442 # ITB inst accesses +system.cpu0.itb.hits 67954632 # DTB hits system.cpu0.itb.misses 2810 # DTB misses -system.cpu0.itb.accesses 67957441 # DTB accesses +system.cpu0.itb.accesses 67957442 # DTB accesses system.cpu0.numCycles 82556870 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1124,7 +1124,7 @@ system.cpu0.num_int_register_writes 49334420 # nu system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written system.cpu0.num_cc_register_reads 245867738 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29383073 # number of times the CC registers were written +system.cpu0.num_cc_register_writes 29383072 # number of times the CC registers were written system.cpu0.num_mem_refs 26220754 # number of memory refs system.cpu0.num_load_insts 14652166 # Number of load instructions system.cpu0.num_store_insts 11568588 # Number of store instructions @@ -1190,16 +1190,16 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 104537930 # Number of tag accesses system.cpu0.icache.tags.data_accesses 104537930 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67090157 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21677955 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu0.inst 67090158 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 21677954 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 12120896 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 100889008 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67090157 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21677955 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 67090158 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 21677954 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 12120896 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 100889008 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 67090157 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 21677955 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 67090158 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 21677954 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 12120896 # number of overall hits system.cpu0.icache.overall_hits::total 100889008 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 866515 # number of ReadReq misses @@ -1223,16 +1223,16 @@ system.cpu0.icache.demand_miss_latency::total 13450125930 system.cpu0.icache.overall_miss_latency::cpu1.inst 3389079250 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu2.inst 10061046680 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 13450125930 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956672 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928102 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956673 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928101 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 12853831 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 102738605 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67956672 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 21928102 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 67956673 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 21928101 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 12853831 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 102738605 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67956672 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 21928102 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 67956673 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 21928101 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 12853831 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 102738605 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012751 # miss rate for ReadReq accesses @@ -1312,7 +1312,7 @@ system.cpu0.dcache.tags.tagsinuse 511.996800 # Cy system.cpu0.dcache.tags.total_refs 47004235 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 834243 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 56.343577 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853552 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.631337 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.511911 # Average occupied blocks per requestor @@ -1385,20 +1385,20 @@ system.cpu0.dcache.overall_misses::total 2415821 # nu system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905009250 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5267719081 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 6172728331 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312526367 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312527367 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70730774620 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 72043300987 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 72043301987 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46439000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132211248 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 178650248 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 181001 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 181001 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2217535617 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 2217536617 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu2.data 75998493701 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 78216029318 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2217535617 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::total 78216030318 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2217536617 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu2.data 75998493701 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 78216029318 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 78216030318 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 13978898 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 4464539 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 8831614 # number of ReadReq accesses(hits+misses) @@ -1457,20 +1457,20 @@ system.cpu0.dcache.overall_miss_rate::total 0.049804 # system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15234.307141 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16643.399254 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 10902.316965 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.293090 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.322544 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46242.623438 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.544929 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.545514 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.986602 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13638.461729 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10253.701888 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23753.032595 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23753.043306 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41167.876557 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34378.677509 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19537.930880 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34378.677948 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19537.939691 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39756.878574 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32376.583082 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32376.583496 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 377833 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 25059 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 25141 # number of cycles access was blocked @@ -1518,9 +1518,9 @@ system.cpu0.dcache.overall_mshr_misses::total 437625 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 783780250 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2132755212 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2916535462 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238573617 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238574617 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5438601702 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677175319 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677176319 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253255500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658822506 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 912078006 # number of SoftPFReq MSHR miss cycles @@ -1529,12 +1529,12 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35809251 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57420251 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022353867 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022354867 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7571356914 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9593710781 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275609367 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9593711781 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275610367 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8230179420 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10505788787 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10505789787 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019366000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1693120500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712486500 # number of ReadReq MSHR uncacheable cycles @@ -1567,9 +1567,9 @@ system.cpu0.dcache.overall_mshr_miss_rate::total 0.009022 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13217.873586 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13255.489335 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13245.359580 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.137164 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.166618 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.981212 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.987715 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency @@ -1578,12 +1578,12 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12420.829344 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13561.703118 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.673509 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.684233 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26972.070614 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.376888 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.314206 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.379562 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.323056 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25352.804212 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.372550 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.374835 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1657,7 +1657,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 21928102 # ITB inst hits +system.cpu1.itb.inst_hits 21928101 # ITB inst hits system.cpu1.itb.inst_misses 848 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1674,26 +1674,26 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 21928950 # ITB inst accesses -system.cpu1.itb.hits 21928102 # DTB hits +system.cpu1.itb.inst_accesses 21928949 # ITB inst accesses +system.cpu1.itb.hits 21928101 # DTB hits system.cpu1.itb.misses 848 # DTB misses -system.cpu1.itb.accesses 21928950 # DTB accesses +system.cpu1.itb.accesses 21928949 # DTB accesses system.cpu1.numCycles 158012618 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21219740 # Number of instructions committed -system.cpu1.committedOps 25418010 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22602371 # Number of integer alu accesses +system.cpu1.committedInsts 21219739 # Number of instructions committed +system.cpu1.committedOps 25418009 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22602370 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses system.cpu1.num_func_calls 2405283 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22602371 # number of integer instructions +system.cpu1.num_int_insts 22602370 # number of integer instructions system.cpu1.num_fp_insts 1626 # number of float instructions -system.cpu1.num_int_register_reads 41665137 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15857681 # number of times the integer registers were written +system.cpu1.num_int_register_reads 41665136 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15857680 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92378686 # number of times the CC registers were read +system.cpu1.num_cc_register_reads 92378683 # number of times the CC registers were read system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written system.cpu1.num_mem_refs 8126078 # number of memory refs system.cpu1.num_load_insts 4682102 # Number of load instructions @@ -1704,7 +1704,7 @@ system.cpu1.not_idle_fraction 0.041047 # Pe system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles system.cpu1.Branches 5257577 # Number of branches fetched system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17988056 68.83% 68.83% # Class of executed instruction +system.cpu1.op_class::IntAlu 17988055 68.83% 68.83% # Class of executed instruction system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction @@ -1737,7 +1737,7 @@ system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Cl system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26134332 # Class of executed instruction +system.cpu1.op_class::total 26134331 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.branchPred.lookups 17411527 # Number of BP lookups diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 9bcc8ea41..8d6175787 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.vram system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index adbb69884..154a76987 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -32,6 +32,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1] warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[5] warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1] @@ -43,7 +44,7 @@ warn: Ignoring write to miscreg pmcr warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6] warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] warn: CP14 unimplemented crn[4], opc1[5], crm[12], opc2[1] -warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] +warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[1] warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -57,7 +58,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 4796b8caa..ade00a610 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:21:54 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:48:14 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x422cb00 0x422cb00 - 0: system.cpu1.isa: ISA system set to: 0x422cb00 0x422cb00 + 0: system.cpu0.isa: ISA system set to: 0x4f45680 0x4f45680 + 0: system.cpu1.isa: ISA system set to: 0x4f45680 0x4f45680 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 9eb62fabd..c06812645 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,141 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804329 # Number of seconds simulated -sim_ticks 2804328920000 # Number of ticks simulated -final_tick 2804328920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804327 # Number of seconds simulated +sim_ticks 2804326619500 # Number of ticks simulated +final_tick 2804326619500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115537 # Simulator instruction rate (inst/s) -host_op_rate 140231 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2770199215 # Simulator tick rate (ticks/s) -host_mem_usage 563788 # Number of bytes of host memory used -host_seconds 1012.32 # Real time elapsed on the host -sim_insts 116960928 # Number of instructions simulated -sim_ops 141958852 # Number of ops (including micro ops) simulated +host_inst_rate 119116 # Simulator instruction rate (inst/s) +host_op_rate 144575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2855979889 # Simulator tick rate (ticks/s) +host_mem_usage 563896 # Number of bytes of host memory used +host_seconds 981.91 # Real time elapsed on the host +sim_insts 116961561 # Number of instructions simulated +sim_ops 141959724 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 4992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 739456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5170528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4648772 # Number of bytes read from this memory -system.physmem.bytes_read::total 11204324 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 739456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1375040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6110656 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 740544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5179680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 636864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4641732 # Number of bytes read from this memory +system.physmem.bytes_read::total 11208612 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 740544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 636864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1377408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6113984 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8446516 # Number of bytes written to this memory +system.physmem.bytes_written::total 8449844 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 78 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 68 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11554 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81308 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 72638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175587 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95479 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11571 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 69 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 72528 # Number of read requests responded to by this memory +system.physmem.num_reads::total 175654 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 95531 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136084 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136136 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 1780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 1552 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 263684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1843767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 226644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1657713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3995367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 263684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 226644 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2179008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 826699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 264072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1847032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 227101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1655204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3996900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 264072 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 227101 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491172 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2180197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 826700 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3011956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2179008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 827041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3013145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2180197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 827042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1552 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 263684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1850013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 226644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1657716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7007324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175588 # Number of read requests accepted -system.physmem.writeReqs 136084 # Number of write requests accepted -system.physmem.readBursts 175588 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136084 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11230016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 8460224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11204388 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8446516 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3871 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4656 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11119 # Per bank write bursts -system.physmem.perBankRdBursts::1 11133 # Per bank write bursts -system.physmem.perBankRdBursts::2 11709 # Per bank write bursts -system.physmem.perBankRdBursts::3 11218 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 264072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1853278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 227101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1655207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7010045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175655 # Number of read requests accepted +system.physmem.writeReqs 136136 # Number of write requests accepted +system.physmem.readBursts 175655 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136136 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11233984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue +system.physmem.bytesWritten 8463616 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11208676 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8449844 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3872 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4658 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11108 # Per bank write bursts +system.physmem.perBankRdBursts::1 11142 # Per bank write bursts +system.physmem.perBankRdBursts::2 11724 # Per bank write bursts +system.physmem.perBankRdBursts::3 11223 # Per bank write bursts system.physmem.perBankRdBursts::4 11369 # Per bank write bursts -system.physmem.perBankRdBursts::5 11386 # Per bank write bursts -system.physmem.perBankRdBursts::6 11957 # Per bank write bursts -system.physmem.perBankRdBursts::7 11810 # Per bank write bursts -system.physmem.perBankRdBursts::8 10209 # Per bank write bursts -system.physmem.perBankRdBursts::9 10442 # Per bank write bursts -system.physmem.perBankRdBursts::10 10595 # Per bank write bursts -system.physmem.perBankRdBursts::11 9762 # Per bank write bursts -system.physmem.perBankRdBursts::12 10419 # Per bank write bursts -system.physmem.perBankRdBursts::13 11416 # Per bank write bursts -system.physmem.perBankRdBursts::14 10636 # Per bank write bursts -system.physmem.perBankRdBursts::15 10289 # Per bank write bursts -system.physmem.perBankWrBursts::0 8317 # Per bank write bursts -system.physmem.perBankWrBursts::1 8433 # Per bank write bursts -system.physmem.perBankWrBursts::2 9040 # Per bank write bursts -system.physmem.perBankWrBursts::3 8546 # Per bank write bursts -system.physmem.perBankWrBursts::4 8342 # Per bank write bursts -system.physmem.perBankWrBursts::5 8537 # Per bank write bursts -system.physmem.perBankWrBursts::6 8976 # Per bank write bursts -system.physmem.perBankWrBursts::7 8813 # Per bank write bursts -system.physmem.perBankWrBursts::8 7760 # Per bank write bursts -system.physmem.perBankWrBursts::9 7806 # Per bank write bursts -system.physmem.perBankWrBursts::10 7935 # Per bank write bursts -system.physmem.perBankWrBursts::11 7392 # Per bank write bursts -system.physmem.perBankWrBursts::12 7884 # Per bank write bursts +system.physmem.perBankRdBursts::5 11393 # Per bank write bursts +system.physmem.perBankRdBursts::6 11953 # Per bank write bursts +system.physmem.perBankRdBursts::7 11818 # Per bank write bursts +system.physmem.perBankRdBursts::8 10217 # Per bank write bursts +system.physmem.perBankRdBursts::9 10450 # Per bank write bursts +system.physmem.perBankRdBursts::10 10599 # Per bank write bursts +system.physmem.perBankRdBursts::11 9773 # Per bank write bursts +system.physmem.perBankRdBursts::12 10412 # Per bank write bursts +system.physmem.perBankRdBursts::13 11414 # Per bank write bursts +system.physmem.perBankRdBursts::14 10639 # Per bank write bursts +system.physmem.perBankRdBursts::15 10297 # Per bank write bursts +system.physmem.perBankWrBursts::0 8312 # Per bank write bursts +system.physmem.perBankWrBursts::1 8440 # Per bank write bursts +system.physmem.perBankWrBursts::2 9043 # Per bank write bursts +system.physmem.perBankWrBursts::3 8548 # Per bank write bursts +system.physmem.perBankWrBursts::4 8346 # Per bank write bursts +system.physmem.perBankWrBursts::5 8542 # Per bank write bursts +system.physmem.perBankWrBursts::6 8974 # Per bank write bursts +system.physmem.perBankWrBursts::7 8818 # Per bank write bursts +system.physmem.perBankWrBursts::8 7763 # Per bank write bursts +system.physmem.perBankWrBursts::9 7812 # Per bank write bursts +system.physmem.perBankWrBursts::10 7942 # Per bank write bursts +system.physmem.perBankWrBursts::11 7398 # Per bank write bursts +system.physmem.perBankWrBursts::12 7887 # Per bank write bursts system.physmem.perBankWrBursts::13 8744 # Per bank write bursts -system.physmem.perBankWrBursts::14 8047 # Per bank write bursts -system.physmem.perBankWrBursts::15 7619 # Per bank write bursts +system.physmem.perBankWrBursts::14 8046 # Per bank write bursts +system.physmem.perBankWrBursts::15 7629 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2804328669500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times write queue was full causing retry +system.physmem.totGap 2804326433500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175033 # Read request sizes (log2) +system.physmem.readPktSize::6 175100 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131703 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60900 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1514 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131755 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 104424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61078 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1503 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -165,133 +177,135 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.565754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.964808 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.021120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24334 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15675 24.25% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6689 10.35% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3630 5.61% 77.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2748 4.25% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1525 2.36% 84.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1125 1.74% 86.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1111 1.72% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7813 12.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64650 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.160877 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 477.303834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.665033 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.572173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.227913 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24436 37.67% 37.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15780 24.33% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6593 10.16% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3751 5.78% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2794 4.31% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1520 2.34% 84.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1090 1.68% 86.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1132 1.75% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7770 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6698 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.205584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 477.627003 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6695 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.709408 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.238406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.151792 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 14 0.21% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.09% 0.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.06% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 11 0.16% 0.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5779 86.16% 86.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 101 1.51% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 51 0.76% 88.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 232 3.46% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 200 2.98% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.31% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.33% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.18% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 28 0.42% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.12% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.07% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 157 2.34% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.16% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.07% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads -system.physmem.totQLat 2725885000 # Total ticks spent queuing -system.physmem.totMemAccLat 6015928750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15534.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6698 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6698 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.743804 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.225845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.527754 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 13 0.19% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.13% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.06% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 9 0.13% 0.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5778 86.26% 86.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 106 1.58% 88.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.64% 89.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 223 3.33% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 204 3.05% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.25% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.33% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.22% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 32 0.48% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.15% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 143 2.13% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.15% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.07% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6698 # Writes before turning the bus around for reads +system.physmem.totQLat 2733630250 # Total ticks spent queuing +system.physmem.totMemAccLat 6024836500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 877655000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15573.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34284.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34323.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s @@ -299,345 +313,333 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.75 # Average write queue length when enqueuing -system.physmem.readRowHits 145120 # Number of row buffer hits during reads -system.physmem.writeRowHits 97889 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes -system.physmem.avgGap 8997692.03 # Average gap between requests -system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2678489596250 # Time in different power states -system.physmem.memoryStateTime::REF 93642640000 # Time in different power states +system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.73 # Average write queue length when enqueuing +system.physmem.readRowHits 145110 # Number of row buffer hits during reads +system.physmem.writeRowHits 97798 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.94 # Row buffer hit rate for writes +system.physmem.avgGap 8994250.74 # Average gap between requests +system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2678438745750 # Time in different power states +system.physmem.memoryStateTime::REF 93642380000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32196672750 # Time in different power states +system.physmem.memoryStateTime::ACT 32245482750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 258567120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 230186880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 141083250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 125598000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 715260000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 653390400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 447145920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 409451760 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 183165003840 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 183165003840 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 77778018765 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 76614000390 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1614369982500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1615391051250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1876875061395 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1876588682520 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.278202 # Core power per rank (mW) -system.physmem.averagePower::1 669.176082 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 251 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 251 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 251 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 251 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 251 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 251 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 67981 # Transaction distribution -system.membus.trans_dist::ReadResp 67980 # Transaction distribution +system.physmem.actEnergy::0 259141680 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 231245280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 141396750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 126175500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 715486200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 653647800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 447269040 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 409672080 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 183164495280 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 183164495280 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 77839312860 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 76923425745 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1614311544000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1615114953750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1876878645810 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1876623615435 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.281339 # Core power per rank (mW) +system.physmem.averagePower::1 669.190397 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 68041 # Transaction distribution +system.membus.trans_dist::ReadResp 68040 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 95479 # Transaction distribution +system.membus.trans_dist::Writeback 95531 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4633 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 23 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4656 # Transaction distribution -system.membus.trans_dist::ReadExReq 138435 # Transaction distribution -system.membus.trans_dist::ReadExResp 138435 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4632 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4658 # Transaction distribution +system.membus.trans_dist::ReadExReq 138441 # Transaction distribution +system.membus.trans_dist::ReadExResp 138441 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572340 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572528 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645052 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645240 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17495585 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17339160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17503137 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19814881 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19822433 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 234 # Total snoops (count) -system.membus.snoop_fanout::samples 310978 # Request fanout histogram +system.membus.snoop_fanout::samples 311110 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 310978 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 311110 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 310978 # Request fanout histogram -system.membus.reqLayer0.occupancy 81489000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 311110 # Request fanout histogram +system.membus.reqLayer0.occupancy 81518499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1718500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1433405250 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1434327498 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1729661846 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1730433594 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38504711 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38513958 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104201 # number of replacements -system.l2c.tags.tagsinuse 65131.975269 # Cycle average of tags in use -system.l2c.tags.total_refs 3107275 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169441 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.338389 # Average number of references to valid blocks. +system.l2c.tags.replacements 104268 # number of replacements +system.l2c.tags.tagsinuse 65131.307742 # Cycle average of tags in use +system.l2c.tags.total_refs 3106944 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169509 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.329080 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48640.203385 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 54.461812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48616.163532 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.311212 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5568.717985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2872.344417 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.548233 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4966.062481 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2988.636721 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.742191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000831 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5571.967356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2874.440506 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.347195 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4984.192297 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2991.885408 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.741824 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000737 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.084972 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.075776 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045603 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993835 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 70 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3222 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8954 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52610 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001068 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994415 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 29225778 # Number of tag accesses -system.l2c.tags.data_accesses 29225778 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 36725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 8774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 958768 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 271288 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36918 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 8011 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 964418 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 269869 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2554771 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 703572 # number of Writeback hits -system.l2c.Writeback_hits::total 703572 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 105 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 45 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 77545 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 79094 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156639 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 36725 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 8774 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 958768 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 348833 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36918 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 8011 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 964418 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 348963 # number of demand (read+write) hits -system.l2c.demand_hits::total 2711410 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 36725 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 8774 # number of overall hits -system.l2c.overall_hits::cpu0.inst 958768 # number of overall hits -system.l2c.overall_hits::cpu0.data 348833 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36918 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 8011 # number of overall hits -system.l2c.overall_hits::cpu1.inst 964418 # number of overall hits -system.l2c.overall_hits::cpu1.data 348963 # number of overall hits -system.l2c.overall_hits::total 2711410 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 78 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.085021 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.076053 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65178 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 63 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3243 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8995 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52594 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000961 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994537 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 29221748 # Number of tag accesses +system.l2c.tags.data_accesses 29221748 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 36519 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 8855 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 959908 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 271615 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 36602 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7424 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 964068 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 269451 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2554442 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 703423 # number of Writeback hits +system.l2c.Writeback_hits::total 703423 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 37 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 59 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 96 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 77798 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78748 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156546 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 36519 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 8855 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 959908 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 349413 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36602 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7424 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 964068 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 348199 # number of demand (read+write) hits +system.l2c.demand_hits::total 2710988 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 36519 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 8855 # number of overall hits +system.l2c.overall_hits::cpu0.inst 959908 # number of overall hits +system.l2c.overall_hits::cpu0.data 349413 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36602 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7424 # number of overall hits +system.l2c.overall_hits::cpu1.inst 964068 # number of overall hits +system.l2c.overall_hits::cpu1.data 348199 # number of overall hits +system.l2c.overall_hits::total 2710988 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 68 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10910 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7138 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 62 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7955 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36080 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1305 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1437 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu0.inst 10928 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7151 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 69 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 9955 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7971 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36143 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1299 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1443 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 6 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 17 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 23 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74623 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 65703 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140326 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 78 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::cpu0.data 8 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 18 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 26 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 74760 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 65571 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140331 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 68 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10910 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 81761 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 73658 # number of demand (read+write) misses -system.l2c.demand_misses::total 176406 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 78 # number of overall misses +system.l2c.demand_misses::cpu0.inst 10928 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 81911 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 69 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 9955 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 73542 # number of demand (read+write) misses +system.l2c.demand_misses::total 176474 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 68 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10910 # number of overall misses -system.l2c.overall_misses::cpu0.data 81761 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 62 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9936 # number of overall misses -system.l2c.overall_misses::cpu1.data 73658 # number of overall misses -system.l2c.overall_misses::total 176406 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 6586000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 10928 # number of overall misses +system.l2c.overall_misses::cpu0.data 81911 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 69 # number of overall misses +system.l2c.overall_misses::cpu1.inst 9955 # number of overall misses +system.l2c.overall_misses::cpu1.data 73542 # number of overall misses +system.l2c.overall_misses::total 176474 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5396500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 832891250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 575497992 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5167000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 747110750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 644595992 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2811923484 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 329986 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 419482 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 749468 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 92496 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162493 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 254989 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5741186064 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5103227796 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10844413860 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 6586000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 829990750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 573729742 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5378000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 749581500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 653390493 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2817541485 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 304487 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 465980 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 770467 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116995 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162993 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 279988 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5741255809 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5109104302 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10850360111 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 5396500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 832891250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6316684056 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 5167000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 747110750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5747823788 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 13656337344 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 6586000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 829990750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6314985551 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 5378000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 749581500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5762494795 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 13667901596 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 5396500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 832891250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6316684056 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 5167000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 747110750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5747823788 # number of overall miss cycles -system.l2c.overall_miss_latency::total 13656337344 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 36803 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 8775 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 969678 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 278426 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 36980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 8011 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 974354 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 277824 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2590851 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 703572 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 703572 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1352 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2847 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 21 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 47 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 68 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 152168 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 144797 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296965 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 36803 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 8775 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 969678 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 430594 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 36980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 8011 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 974354 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 422621 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2887816 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 36803 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 8775 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 969678 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 430594 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 36980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 8011 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 974354 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 422621 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2887816 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000114 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.011251 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.025637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010198 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.028633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.965237 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.961204 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.963119 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.285714 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.361702 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.338235 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.490399 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.453759 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.472534 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000114 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.011251 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.189880 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010198 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.174289 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.061086 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000114 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.011251 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.189880 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010198 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.174289 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.061086 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 829990750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6314985551 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 5378000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 749581500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5762494795 # number of overall miss cycles +system.l2c.overall_miss_latency::total 13667901596 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 36587 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 8856 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 970836 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 278766 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 36671 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7424 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 974023 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 277422 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2590585 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 703423 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 703423 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1336 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1502 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2838 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 29 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 50 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 79 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 152558 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 144319 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296877 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 36587 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8856 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 970836 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 431324 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36671 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7424 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 974023 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 421741 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2887462 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 36587 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8856 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 970836 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 431324 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36671 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7424 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 974023 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 421741 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2887462 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000113 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.011256 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.025652 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010220 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.028732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013952 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.972305 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.960719 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.966173 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.275862 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.360000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.329114 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.490043 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.454348 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.472691 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000113 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.011256 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.189906 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010220 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.174377 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.061117 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000113 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.011256 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.189906 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010220 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.174377 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.061117 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76342.002750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 80624.543570 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75192.305757 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 81030.294406 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 77935.795011 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 252.862835 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 291.915101 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 273.328957 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15416 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9558.411765 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 11086.478261 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76935.878536 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77671.153463 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 77280.146658 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75950.837299 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80230.700881 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75296.986439 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81970.956342 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 77955.385137 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 234.401078 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 322.924463 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 280.987236 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14624.375000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9055.166667 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 10768.769231 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76795.824090 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77917.132604 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77319.766203 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76342.002750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 77257.910936 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75192.305757 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 78033.937766 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 77414.245230 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 75950.837299 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77095.695950 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75296.986439 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78356.514577 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 77449.945012 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76342.002750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 77257.910936 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75192.305757 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 78033.937766 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 77414.245230 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 75950.837299 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77095.695950 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75296.986439 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78356.514577 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 77449.945012 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,166 +648,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95479 # number of writebacks -system.l2c.writebacks::total 95479 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 71 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 95531 # number of writebacks +system.l2c.writebacks::total 95531 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 73 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 66 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 71 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 150 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 73 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 66 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 148 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 71 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 150 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 73 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 66 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 148 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 78 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 150 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 68 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 10904 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7067 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 62 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 9931 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 7889 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1305 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1437 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 10921 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7078 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 69 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9951 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7905 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 35993 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1299 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1443 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 6 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 17 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 23 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 74623 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 65703 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140326 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 78 # number of demand (read+write) MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 18 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 26 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 74760 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 65571 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140331 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 68 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 10904 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 81690 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 62 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9931 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 73592 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176258 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 78 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 10921 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 81838 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 69 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9951 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 73476 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176324 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 68 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 10904 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 81690 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 62 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9931 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 73592 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176258 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 10921 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 81838 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 69 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9951 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 73476 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176324 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 695263500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 482934742 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 621792250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 542490992 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2352561484 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13058305 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14434936 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 27493241 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 60006 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 170017 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 230023 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4809749936 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4286056704 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9095806640 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 692294000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 481153492 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 624075250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 550752493 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2357413735 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12992798 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14497943 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 27490741 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 80008 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 260026 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4808098691 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4293415698 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9101514389 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 695263500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5292684678 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 621792250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4828547696 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 11448368124 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 692294000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5289252183 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 624075250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4844168191 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 11458928124 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 695263500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5292684678 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 621792250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4828547696 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 11448368124 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 36174500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2949055750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430218500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5415448750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2226044000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1876060498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4102104498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 36174500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5175099750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4306278998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9517553248 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025382 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028396 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013869 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.965237 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.961204 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.963119 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.361702 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.338235 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490399 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.453759 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.472534 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.189715 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061035 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.189715 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061035 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 692294000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5289252183 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 624075250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4844168191 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 11458928124 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 35706500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2951899000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2427344000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5414949500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2228650000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1873529499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4102179499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 35706500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5180549000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4300873499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9517128999 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025390 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013894 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.972305 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.960719 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.966173 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.360000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.329114 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490043 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454348 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472691 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061065 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061065 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68336.598557 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68765.495247 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 65472.600579 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.363985 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.188587 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.710795 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67978.735801 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69671.409614 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65496.450282 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.153965 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.084546 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.799052 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64453.987859 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65233.805214 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64819.111498 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64313.786664 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65477.355813 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64857.475462 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -855,59 +857,60 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2655300 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2655214 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2655325 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2655239 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 703572 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2847 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 68 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296965 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296965 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3889644 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533488 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43405 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169876 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6636413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124460352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99828001 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 67144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 295132 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224650629 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 69040 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3663181 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099289 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 703423 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36238 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2838 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 79 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2917 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296877 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296877 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891298 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533043 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42437 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6635850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124513216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99808865 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 293032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224680233 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69343 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3662983 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.009961 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099307 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3626705 99.00% 99.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3626496 99.00% 99.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36487 1.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3663181 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4671577230 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3662983 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4670881246 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 8759110629 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 8762800197 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3910283961 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3909656420 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26690343 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26229350 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96888385 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96621860 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30210 # Transaction distribution system.iobus.trans_dist::ReadResp 30210 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteReq 59030 # Transaction distribution system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 8 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -998,23 +1001,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326614549 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326627644 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36835289 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36841042 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 26968745 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14109241 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 549589 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 16704483 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12571056 # Number of BTB hits +system.cpu0.branchPred.lookups 27349422 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14250256 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 549515 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 17066610 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12886962 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.255583 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6684107 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29871 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.509794 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6758521 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 30298 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1038,25 +1041,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14281958 # DTB read hits -system.cpu0.dtb.read_misses 49036 # DTB read misses -system.cpu0.dtb.write_hits 10331652 # DTB write hits -system.cpu0.dtb.write_misses 7432 # DTB write misses +system.cpu0.dtb.read_hits 14278108 # DTB read hits +system.cpu0.dtb.read_misses 49273 # DTB read misses +system.cpu0.dtb.write_hits 10337716 # DTB write hits +system.cpu0.dtb.write_misses 7471 # DTB write misses system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3418 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 971 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1307 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3414 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 948 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1297 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 583 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14330994 # DTB read accesses -system.cpu0.dtb.write_accesses 10339084 # DTB write accesses +system.cpu0.dtb.perms_faults 559 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14327381 # DTB read accesses +system.cpu0.dtb.write_accesses 10345187 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24613610 # DTB hits -system.cpu0.dtb.misses 56468 # DTB misses -system.cpu0.dtb.accesses 24670078 # DTB accesses +system.cpu0.dtb.hits 24615824 # DTB hits +system.cpu0.dtb.misses 56744 # DTB misses +system.cpu0.dtb.accesses 24672568 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1078,720 +1081,720 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 20359986 # ITB inst hits -system.cpu0.itb.inst_misses 8688 # ITB inst misses +system.cpu0.itb.inst_hits 20514368 # ITB inst hits +system.cpu0.itb.inst_misses 8789 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2307 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2304 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20368674 # ITB inst accesses -system.cpu0.itb.hits 20359986 # DTB hits -system.cpu0.itb.misses 8688 # DTB misses -system.cpu0.itb.accesses 20368674 # DTB accesses -system.cpu0.numCycles 107845593 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20523157 # ITB inst accesses +system.cpu0.itb.hits 20514368 # DTB hits +system.cpu0.itb.misses 8789 # DTB misses +system.cpu0.itb.accesses 20523157 # DTB accesses +system.cpu0.numCycles 107867607 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 40386810 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 105587816 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26968745 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19255163 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 62197124 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3245751 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 127625 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 7153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 414 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 560512 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 142803 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20358682 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 375797 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3540 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 105045556 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.208380 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.316447 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 40554205 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 105662539 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 27349422 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19645483 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61985766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3245353 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 132544 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 7121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 440 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 622961 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 144030 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 269 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20513111 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 376873 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3476 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 105069976 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.208080 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.305286 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 76194887 72.54% 72.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3754274 3.57% 76.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2490616 2.37% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7859227 7.48% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1696652 1.62% 87.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1110270 1.06% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6030562 5.74% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1172073 1.12% 95.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4736995 4.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75961238 72.30% 72.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3886755 3.70% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2398368 2.28% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8188948 7.79% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1668369 1.59% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1057044 1.01% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6240721 5.94% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1068642 1.02% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4599891 4.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 105045556 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.250068 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.979065 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27992831 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58288752 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15795686 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1494186 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1473806 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1905882 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 151125 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 87429633 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 488960 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1473806 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28854522 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7825241 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44530433 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16415738 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 5945509 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 83590953 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2363 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1232745 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 241627 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3747183 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 86230749 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 384928079 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 93177414 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5669 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72449468 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13781265 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1547727 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1453455 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8907873 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 15026911 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11459129 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1951942 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2729865 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 80431590 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1054195 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 77118742 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91388 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10043438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24751793 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 115145 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 105045556 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.734146 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.428326 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 105069976 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.253546 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.979558 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 28001193 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58307153 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15793340 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1494905 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1473111 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1905219 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 151604 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 87425197 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 489487 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1473111 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28862922 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7852670 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44540857 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16413726 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 5926414 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 83594857 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2128 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1233256 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 243031 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3726809 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 86235184 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 384969647 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 93192750 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5702 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72438827 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13796341 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1547496 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1453336 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8912532 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 15029778 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11466004 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1956224 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2714292 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 80433839 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1054374 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 77107853 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 91926 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10053145 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24795847 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 115089 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 105069976 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.733871 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.427930 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74311546 70.74% 70.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10189117 9.70% 80.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7864547 7.49% 87.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6570455 6.25% 94.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2322662 2.21% 96.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1491632 1.42% 97.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1567348 1.49% 99.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 489722 0.47% 99.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 238527 0.23% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74334112 70.75% 70.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10187384 9.70% 80.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7871575 7.49% 87.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6574512 6.26% 94.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2321319 2.21% 96.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1487177 1.42% 97.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1563743 1.49% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 491068 0.47% 99.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 239086 0.23% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 105045556 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 105069976 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 112665 9.94% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 535473 47.24% 57.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 485278 42.82% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 112390 9.87% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 534190 46.93% 56.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 491756 43.20% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2200 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 51451834 66.72% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57694 0.07% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4462 0.01% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14684703 19.04% 85.84% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10917839 14.16% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2199 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51438430 66.71% 66.71% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57761 0.07% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4468 0.01% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14680887 19.04% 85.83% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10924099 14.17% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 77118742 # Type of FU issued -system.cpu0.iq.rate 0.715085 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1133419 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014697 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 260495273 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91574151 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 74667012 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12574 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6644 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5487 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 78243199 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6762 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 345945 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 77107853 # Type of FU issued +system.cpu0.iq.rate 0.714838 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1138339 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014763 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 260503389 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91586031 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 74660496 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12558 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6677 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 78237256 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6737 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 345558 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2206741 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2565 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 52530 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1128151 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2209259 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2417 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 52309 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1126312 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 207860 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 209627 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 207644 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 205299 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1473806 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5382891 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2162428 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 81613092 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 131628 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 15026911 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11459129 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 550936 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 43632 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2106388 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 52530 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 254626 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 219922 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 474548 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 76513772 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14449148 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 548624 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1473111 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5378277 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2195764 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 81614966 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 130944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 15029778 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11466004 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 550994 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44204 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2139047 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 52309 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 254090 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 219689 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 473779 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76503781 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14445333 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 547436 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 127307 # number of nop insts executed -system.cpu0.iew.exec_refs 25261391 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14437195 # Number of branches executed -system.cpu0.iew.exec_stores 10812243 # Number of stores executed -system.cpu0.iew.exec_rate 0.709475 # Inst execution rate -system.cpu0.iew.wb_sent 75851893 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 74672499 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 39010696 # num instructions producing a value -system.cpu0.iew.wb_consumers 67649101 # num instructions consuming a value +system.cpu0.iew.exec_nop 126753 # number of nop insts executed +system.cpu0.iew.exec_refs 25264055 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14430009 # Number of branches executed +system.cpu0.iew.exec_stores 10818722 # Number of stores executed +system.cpu0.iew.exec_rate 0.709238 # Inst execution rate +system.cpu0.iew.wb_sent 75844960 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 74665993 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 39001048 # num instructions producing a value +system.cpu0.iew.wb_consumers 67639279 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.692402 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576662 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.692200 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576604 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11320580 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 939050 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 400483 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102489063 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685035 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.574738 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11323076 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 939285 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 399913 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102514186 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.684864 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.574695 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75163014 73.34% 73.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12241374 11.94% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6264234 6.11% 91.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2647997 2.58% 93.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1295474 1.26% 95.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 837997 0.82% 96.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1889450 1.84% 97.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 409985 0.40% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1739538 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75189561 73.35% 73.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12242134 11.94% 85.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6265138 6.11% 91.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2642512 2.58% 93.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1297372 1.27% 95.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 836423 0.82% 96.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1889134 1.84% 97.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 413413 0.40% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1738499 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102489063 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57892234 # Number of instructions committed -system.cpu0.commit.committedOps 70208613 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102514186 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 57883100 # Number of instructions committed +system.cpu0.commit.committedOps 70208236 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23151148 # Number of memory references committed -system.cpu0.commit.loads 12820170 # Number of loads committed -system.cpu0.commit.membars 372459 # Number of memory barriers committed -system.cpu0.commit.branches 13651808 # Number of branches committed +system.cpu0.commit.refs 23160211 # Number of memory references committed +system.cpu0.commit.loads 12820519 # Number of loads committed +system.cpu0.commit.membars 372556 # Number of memory barriers committed +system.cpu0.commit.branches 13646736 # Number of branches committed system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61466111 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2656847 # Number of function calls committed. +system.cpu0.commit.int_insts 61470931 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2656843 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46997024 66.94% 66.94% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55979 0.08% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4462 0.01% 67.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12820170 18.26% 85.29% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10330978 14.71% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46987548 66.93% 66.93% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 56009 0.08% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4468 0.01% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12820519 18.26% 85.27% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10339692 14.73% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70208613 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1739538 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 70208236 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1738499 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 169616941 # The number of ROB reads -system.cpu0.rob.rob_writes 165619058 # The number of ROB writes -system.cpu0.timesIdled 398870 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2800037 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2442123265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 57820351 # Number of Instructions Simulated -system.cpu0.committedOps 70136730 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.865184 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.865184 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.536140 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.536140 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 83228446 # number of integer regfile reads -system.cpu0.int_regfile_writes 47576245 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16184 # number of floating regfile reads -system.cpu0.fp_regfile_writes 12998 # number of floating regfile writes -system.cpu0.cc_regfile_reads 270476207 # number of cc regfile reads -system.cpu0.cc_regfile_writes 28213628 # number of cc regfile writes -system.cpu0.misc_regfile_reads 191272649 # number of misc regfile reads -system.cpu0.misc_regfile_writes 720305 # number of misc regfile writes -system.cpu0.icache.tags.replacements 1943673 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.578352 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38923517 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1944185 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.020480 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 169645518 # The number of ROB reads +system.cpu0.rob.rob_writes 165622521 # The number of ROB writes +system.cpu0.timesIdled 399235 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2797631 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2442097834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 57811199 # Number of Instructions Simulated +system.cpu0.committedOps 70136335 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.865860 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.865860 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.535946 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.535946 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 83226933 # number of integer regfile reads +system.cpu0.int_regfile_writes 47573974 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16207 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13000 # number of floating regfile writes +system.cpu0.cc_regfile_reads 270444340 # number of cc regfile reads +system.cpu0.cc_regfile_writes 28203341 # number of cc regfile writes +system.cpu0.misc_regfile_reads 191459430 # number of misc regfile reads +system.cpu0.misc_regfile_writes 720407 # number of misc regfile writes +system.cpu0.icache.tags.replacements 1944509 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.580286 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39079293 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1945021 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.091965 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.782570 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 236.795782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.536685 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.462492 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999176 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.092053 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.488233 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541195 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.457985 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999180 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42951658 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42951658 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19318996 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19604521 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38923517 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19318996 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19604521 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38923517 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19318996 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19604521 # number of overall hits -system.cpu0.icache.overall_hits::total 38923517 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1039021 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1044832 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2083853 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1039021 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1044832 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2083853 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1039021 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1044832 # number of overall misses -system.cpu0.icache.overall_misses::total 2083853 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14217432245 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14193731102 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28411163347 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14217432245 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14193731102 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28411163347 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14217432245 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14193731102 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28411163347 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 20358017 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20649353 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41007370 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 20358017 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20649353 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41007370 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 20358017 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20649353 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41007370 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051037 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050599 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050817 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051037 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050599 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050817 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051037 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050599 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13683.488827 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13584.701753 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.957552 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.488827 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13584.701753 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13633.957552 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.488827 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13584.701753 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13633.957552 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8339 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43109447 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43109447 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19472177 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19607116 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39079293 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19472177 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19607116 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 39079293 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19472177 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19607116 # number of overall hits +system.cpu0.icache.overall_hits::total 39079293 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1040272 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1044765 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2085037 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1040272 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1044765 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2085037 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1040272 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1044765 # number of overall misses +system.cpu0.icache.overall_misses::total 2085037 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14234369484 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14196293397 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28430662881 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14234369484 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14196293397 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28430662881 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14234369484 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14196293397 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28430662881 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20512449 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20651881 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41164330 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20512449 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20651881 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41164330 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20512449 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20651881 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41164330 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050714 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050589 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050652 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050714 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050589 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050652 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050714 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050589 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050652 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13683.315021 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13588.025438 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13635.567561 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13635.567561 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13635.567561 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8976 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 489 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 503 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.053170 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.844930 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69244 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70320 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 139564 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 69244 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 70320 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 139564 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 69244 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 70320 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 139564 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969777 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974512 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1944289 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 969777 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 974512 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1944289 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 969777 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 974512 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1944289 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11614628478 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11591128360 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 23205756838 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11614628478 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11591128360 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 23205756838 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11614628478 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11591128360 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 23205756838 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49940000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49940000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49940000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 49940000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047413 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047413 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047413 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11935.343376 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11935.343376 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11935.343376 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69341 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70578 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 139919 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 69341 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 70578 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 139919 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 69341 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 70578 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 139919 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 970931 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974187 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1945118 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 970931 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 974187 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1945118 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 970931 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 974187 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1945118 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11624310724 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11588912543 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23213223267 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11624310724 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11588912543 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23213223267 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11624310724 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11588912543 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23213223267 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49455500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 49455500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047253 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047253 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047253 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11934.095138 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 852682 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984423 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42512914 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 853194 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.827957 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 852532 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984435 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42510984 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853044 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.834456 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 329.938362 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 182.046061 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.644411 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.355559 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 328.580964 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 183.403471 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.641760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.358210 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189863403 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189863403 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12602173 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12737013 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25339186 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7727036 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8174827 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15901863 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180867 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181606 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362473 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207945 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238852 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446797 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213795 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459419 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20329209 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20911840 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41241049 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20510076 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21093446 # number of overall hits -system.cpu0.dcache.overall_hits::total 41603522 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 421777 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 407630 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 829407 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1909127 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1794923 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3704050 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96495 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 85144 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 181639 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13429 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14216 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27645 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 47 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 68 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2330904 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2202553 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4533457 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2427399 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2287697 # number of overall misses -system.cpu0.dcache.overall_misses::total 4715096 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7013958136 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6635684452 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13649642588 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84643454348 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74838228910 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 159481683258 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 181700494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 211428245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 393128739 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 350006 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 828017 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1178023 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 91657412484 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 81473913362 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 173131325846 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 91657412484 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 81473913362 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 173131325846 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 13023950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13144643 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26168593 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9636163 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9969750 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19605913 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277362 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266750 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 544112 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221374 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253068 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474442 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 213816 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 245671 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459487 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22660113 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 23114393 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45774506 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22937475 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23381143 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46318618 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032385 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031011 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031695 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198121 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.180037 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188925 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.347903 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.319190 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.333826 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060662 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056175 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058268 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000098 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000191 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000148 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.102864 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095289 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.099039 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.105827 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097844 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.101797 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16629.541525 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16278.695022 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16457.110427 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44336.209350 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41694.395197 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43056.028741 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13530.456028 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14872.555219 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14220.609116 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16666.952381 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17617.382979 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17323.867647 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39322.688744 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36990.670990 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 38189.691850 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37759.516455 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35613.944225 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36718.515561 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1117471 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 160932 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 70035 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2415 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.955893 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 66.638509 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 189858417 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189858417 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12600621 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12736293 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25336914 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7729736 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8172690 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15902426 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180938 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181427 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 362365 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207885 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238844 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446729 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213819 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245596 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459415 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20330357 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20908983 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41239340 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20511295 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21090410 # number of overall hits +system.cpu0.dcache.overall_hits::total 41601705 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 423569 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 406804 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 830373 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1914715 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1788827 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3703542 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96924 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84951 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 181875 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13440 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14180 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27620 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 29 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 50 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 79 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2338284 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2195631 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4533915 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2435208 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2280582 # number of overall misses +system.cpu0.dcache.overall_misses::total 4715790 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7009049435 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6678797631 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13687847066 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84691128349 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74764779722 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 159455908071 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 183084493 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 209418995 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 392503488 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480508 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 880018 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 1360526 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 91700177784 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 81443577353 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 173143755137 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 91700177784 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 81443577353 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 173143755137 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13024190 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13143097 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26167287 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9644451 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9961517 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19605968 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277862 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266378 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 544240 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221325 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253024 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 474349 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 213848 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 245646 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459494 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 22668641 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23104614 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45773255 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22946503 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23370992 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46317495 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032522 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030952 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031733 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198530 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.179574 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188899 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.348821 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.318911 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.334182 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060725 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056042 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058227 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000136 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000204 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000172 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.103151 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095030 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.099052 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106125 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097582 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.101814 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16547.597759 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16417.728515 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16483.974149 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44231.715085 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41795.422208 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43054.974959 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13622.358110 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14768.617419 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14210.843157 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16569.241379 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17600.360000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17221.848101 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39216.869202 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37093.472151 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 38188.575467 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37655.993978 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35711.751366 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36715.747550 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1113759 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 155988 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70298 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2399 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.843395 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 65.022093 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 703572 # number of writebacks -system.cpu0.dcache.writebacks::total 703572 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 210384 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 193413 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 403797 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1755618 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1648654 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3404272 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9415 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8951 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18366 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1966002 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1842067 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3808069 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1966002 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1842067 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3808069 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211393 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 214217 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 425610 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 153509 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 146269 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 299778 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 63030 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58365 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 121395 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4014 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5265 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 47 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 68 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 364902 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 360486 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 725388 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 427932 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 418851 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 846783 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2857072417 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2926033619 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5783106036 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6788582559 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6159862377 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12948444936 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 975244760 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 899933504 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1875178264 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46933501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81366752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 128300253 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 307994 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 733983 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1041977 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9645654976 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9085895996 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 18731550972 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10620899736 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9985829500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 20606729236 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3170906750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2613622501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784529251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2427957377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2008001500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4435958877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5598864127 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4621624001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220488128 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016231 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016297 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016264 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015931 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014671 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015290 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227248 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.218800 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223107 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020805 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019558 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000098 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000191 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000148 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016103 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015596 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015847 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018656 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017914 # mshr miss rate for overall accesses +system.cpu0.dcache.writebacks::writebacks 703423 # number of writebacks +system.cpu0.dcache.writebacks::total 703423 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211999 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 192913 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 404912 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1760835 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1643027 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3403862 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9519 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8988 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18507 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1972834 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1835940 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3808774 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1972834 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1835940 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3808774 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211570 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 213891 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 425461 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 153880 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 145800 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299680 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 63289 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58360 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 121649 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3921 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5192 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9113 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 29 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 50 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 79 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 365450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 359691 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 725141 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 428739 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 418051 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 846790 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2855948132 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2928153928 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5784102060 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6788973337 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6163703908 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12952677245 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 974890008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 904686758 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1879576766 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46893501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79693003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 126586504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422492 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 779982 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1202474 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9644921469 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9091857836 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18736779305 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10619811477 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9996544594 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 20616356071 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3173945001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2610547002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784492003 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2430732877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005306500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436039377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5604677878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4615853502 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220531380 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016244 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016274 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015955 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014636 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227771 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.219087 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223521 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017716 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020520 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019212 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000136 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000204 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000172 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016121 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015568 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015842 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018684 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.018282 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13515.454235 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13659.203607 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.805822 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44222.700682 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42113.245985 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43193.446270 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15472.707600 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15419.061150 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15446.915145 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.451669 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15454.273884 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13826.948270 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14666.380952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15616.659574 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15323.191176 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26433.549216 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25204.573814 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25822.802379 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24819.129525 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23841.006706 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24335.312868 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13498.833162 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13689.935191 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13594.905432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44118.620594 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42275.061097 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43221.693957 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15403.782774 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15501.829301 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15450.819703 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11959.576894 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15349.191641 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13890.760891 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14568.689655 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15599.640000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15221.189873 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26391.904416 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25276.856624 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25838.808321 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.875092 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23912.260930 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24346.480321 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1802,15 +1805,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27347291 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14229080 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 552926 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17264130 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 12844736 # Number of BTB hits +system.cpu1.branchPred.lookups 27353552 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14236577 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 553412 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17312116 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12843593 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.401293 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6762355 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29663 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.188464 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6764103 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29805 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1834,25 +1837,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14380313 # DTB read hits -system.cpu1.dtb.read_misses 50338 # DTB read misses -system.cpu1.dtb.write_hits 10697385 # DTB write hits -system.cpu1.dtb.write_misses 9618 # DTB write misses +system.cpu1.dtb.read_hits 14379922 # DTB read hits +system.cpu1.dtb.read_misses 49648 # DTB read misses +system.cpu1.dtb.write_hits 10687800 # DTB write hits +system.cpu1.dtb.write_misses 9435 # DTB write misses system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 785 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1275 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 765 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1285 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14430651 # DTB read accesses -system.cpu1.dtb.write_accesses 10707003 # DTB write accesses +system.cpu1.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14429570 # DTB read accesses +system.cpu1.dtb.write_accesses 10697235 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25077698 # DTB hits -system.cpu1.dtb.misses 59956 # DTB misses -system.cpu1.dtb.accesses 25137654 # DTB accesses +system.cpu1.dtb.hits 25067722 # DTB hits +system.cpu1.dtb.misses 59083 # DTB misses +system.cpu1.dtb.accesses 25126805 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1874,377 +1877,381 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20651138 # ITB inst hits -system.cpu1.itb.inst_misses 8123 # ITB inst misses +system.cpu1.itb.inst_hits 20653653 # ITB inst hits +system.cpu1.itb.inst_misses 7569 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2271 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2278 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1349 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1323 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20659261 # ITB inst accesses -system.cpu1.itb.hits 20651138 # DTB hits -system.cpu1.itb.misses 8123 # DTB misses -system.cpu1.itb.accesses 20659261 # DTB accesses -system.cpu1.numCycles 107249974 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20661222 # ITB inst accesses +system.cpu1.itb.hits 20653653 # DTB hits +system.cpu1.itb.misses 7569 # DTB misses +system.cpu1.itb.accesses 20661222 # DTB accesses +system.cpu1.numCycles 107242523 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40725468 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106761765 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27347291 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19607091 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 61565472 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3230729 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 119361 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 4162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 473 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 476136 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 133238 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20649355 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 381272 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3428 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104639861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.227831 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.325701 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40712684 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 106782026 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27353552 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19607696 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 61803081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3231443 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 109598 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 4239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 431 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 249521 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 135474 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20651884 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 381778 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3230 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104630887 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.228118 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.325936 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 75287195 71.95% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3919090 3.75% 75.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2500009 2.39% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8110720 7.75% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1591501 1.52% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1177075 1.12% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6154172 5.88% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1148436 1.10% 95.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4751663 4.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 75276432 71.94% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3916697 3.74% 75.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2503204 2.39% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8106458 7.75% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1592842 1.52% 87.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1179592 1.13% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6154126 5.88% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1149786 1.10% 95.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4751750 4.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104639861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.254986 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.995448 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27852312 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57848791 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15754577 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1718968 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1464898 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1977106 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 152502 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 89215039 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 494329 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1464898 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28797360 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6699621 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 45356537 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16519675 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 5801450 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 85333745 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2191 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1572004 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 242988 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 3188310 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 88168045 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 393456751 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 95320905 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6151 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 74288331 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13879714 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1591572 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1490290 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10044487 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15194391 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11866887 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2182296 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2756146 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 82055126 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1162203 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78681977 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95018 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10109005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25435903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 107068 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104639861 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.751931 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.430939 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104630887 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.255063 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.995706 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27864157 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57830739 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15747454 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1722658 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1465635 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1976909 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 152146 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89229365 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 493204 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1465635 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28812184 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6716141 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 45339545 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16513270 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 5783839 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85351560 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2174 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1570337 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 239520 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 3169707 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 88205068 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 393510505 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 95333289 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6152 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 74299663 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13905405 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1590806 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1489461 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10064978 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15196570 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11856807 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2179914 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2787279 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 82067057 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1161463 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78685046 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94868 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10122036 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25487135 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 106552 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104630887 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.752025 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.430826 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72959997 69.72% 69.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10709404 10.23% 79.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8056823 7.70% 87.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6679323 6.38% 94.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2498342 2.39% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1545149 1.48% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1464114 1.40% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 496511 0.47% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 230198 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72948465 69.72% 69.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10708543 10.23% 79.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8057357 7.70% 87.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6681907 6.39% 94.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2500436 2.39% 96.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1544614 1.48% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1464658 1.40% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 495950 0.47% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 228957 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104639861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104630887 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 103205 8.90% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 536017 46.20% 55.10% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 520896 44.90% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 103296 8.95% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 535211 46.35% 55.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 516097 44.70% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 137 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52524607 66.76% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 58923 0.07% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4123 0.01% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14785011 18.79% 85.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11309172 14.37% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 138 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52538123 66.77% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 58820 0.07% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4114 0.01% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14784683 18.79% 85.64% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11299162 14.36% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78681977 # Type of FU issued -system.cpu1.iq.rate 0.733632 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1160123 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014744 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 263245129 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 93371477 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 76291260 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13827 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7286 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6040 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79834510 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7453 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 367216 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78685046 # Type of FU issued +system.cpu1.iq.rate 0.733711 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1154609 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014674 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 263236691 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 93395575 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 76291766 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13765 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7276 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6039 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79832108 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7409 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 367192 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2201674 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2649 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 53639 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1152377 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2204039 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2671 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 53511 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1150974 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 193043 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 153958 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 193750 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 155367 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1464898 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4313031 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2150253 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 83357725 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132748 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15194391 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11866887 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 585663 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 47230 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2090333 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 53639 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 255743 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 221088 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 476831 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 78071744 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14543565 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 550444 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1465635 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4317272 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2160865 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 83369977 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 136369 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15196570 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11856807 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 585220 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 46964 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2101356 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 53511 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 256264 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 221755 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 478019 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 78073190 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14542904 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 552934 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 140396 # number of nop insts executed -system.cpu1.iew.exec_refs 25744293 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14514927 # Number of branches executed -system.cpu1.iew.exec_stores 11200728 # Number of stores executed -system.cpu1.iew.exec_rate 0.727942 # Inst execution rate -system.cpu1.iew.wb_sent 77444184 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 76297300 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39931831 # num instructions producing a value -system.cpu1.iew.wb_consumers 69996884 # num instructions consuming a value +system.cpu1.iew.exec_nop 141457 # number of nop insts executed +system.cpu1.iew.exec_refs 25733696 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14521478 # Number of branches executed +system.cpu1.iew.exec_stores 11190792 # Number of stores executed +system.cpu1.iew.exec_rate 0.728006 # Inst execution rate +system.cpu1.iew.wb_sent 77444186 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 76297805 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39935797 # num instructions producing a value +system.cpu1.iew.wb_consumers 69997959 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.711397 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570480 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.711451 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570528 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11439631 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1055135 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 402423 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102076918 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.704421 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.588048 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11451015 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1054911 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 403289 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102066180 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.704508 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.588054 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73994277 72.49% 72.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12594887 12.34% 84.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6447399 6.32% 91.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2674121 2.62% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1416644 1.39% 95.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 932745 0.91% 96.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1821915 1.78% 97.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 428135 0.42% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1766795 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73979517 72.48% 72.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12597540 12.34% 84.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6450417 6.32% 91.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2677104 2.62% 93.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1410201 1.38% 95.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 931945 0.91% 96.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1826334 1.79% 97.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 426802 0.42% 98.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1766320 1.73% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102076918 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 59223599 # Number of instructions committed -system.cpu1.commit.committedOps 71905144 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102066180 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 59233366 # Number of instructions committed +system.cpu1.commit.committedOps 71906393 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23707227 # Number of memory references committed -system.cpu1.commit.loads 12992717 # Number of loads committed -system.cpu1.commit.membars 441930 # Number of memory barriers committed -system.cpu1.commit.branches 13739507 # Number of branches committed +system.cpu1.commit.refs 23698364 # Number of memory references committed +system.cpu1.commit.loads 12992531 # Number of loads committed +system.cpu1.commit.membars 441834 # Number of memory barriers committed +system.cpu1.commit.branches 13745002 # Number of branches committed system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 63021848 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2684059 # Number of function calls committed. +system.cpu1.commit.int_insts 63017798 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2684230 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48136675 66.94% 66.94% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57123 0.08% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 12992717 18.07% 85.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10714510 14.90% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48146836 66.96% 66.96% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57080 0.08% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4113 0.01% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 12992531 18.07% 85.11% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10705833 14.89% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71905144 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1766795 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 71906393 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1766320 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171176371 # The number of ROB reads -system.cpu1.rob.rob_writes 169257009 # The number of ROB writes -system.cpu1.timesIdled 392905 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2610113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2951402872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 59140577 # Number of Instructions Simulated -system.cpu1.committedOps 71822122 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.813475 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.813475 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551427 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551427 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84961864 # number of integer regfile reads -system.cpu1.int_regfile_writes 48575931 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16615 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13105 # number of floating regfile writes -system.cpu1.cc_regfile_reads 275730923 # number of cc regfile reads -system.cpu1.cc_regfile_writes 28983730 # number of cc regfile writes -system.cpu1.misc_regfile_reads 192710320 # number of misc regfile reads -system.cpu1.misc_regfile_writes 799493 # number of misc regfile writes +system.cpu1.rob.rob_reads 171177235 # The number of ROB reads +system.cpu1.rob.rob_writes 169283950 # The number of ROB writes +system.cpu1.timesIdled 392418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2611636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2951410112 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 59150362 # Number of Instructions Simulated +system.cpu1.committedOps 71823389 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.813049 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.813049 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551557 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551557 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84951910 # number of integer regfile reads +system.cpu1.int_regfile_writes 48574213 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16611 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13102 # number of floating regfile writes +system.cpu1.cc_regfile_reads 275725718 # number of cc regfile reads +system.cpu1.cc_regfile_writes 28996859 # number of cc regfile writes +system.cpu1.misc_regfile_reads 192674093 # number of misc regfile reads +system.cpu1.misc_regfile_writes 799402 # number of misc regfile writes system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 0.982033 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.982061 # Cycle average of tags in use system.iocache.tags.total_refs 16 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234020639000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.982033 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061377 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061377 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 234012764000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.982061 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061379 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061379 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328241 # Number of tag accesses -system.iocache.tags.data_accesses 328241 # Number of data accesses +system.iocache.tags.tag_accesses 328305 # Number of tag accesses +system.iocache.tags.data_accesses 328305 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 8 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 8 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29659377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29662377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29662377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29662377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29662377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29662377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29662377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36232 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36232 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000221 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000221 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119113.963855 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119113.963855 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119113.963855 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 119126.012048 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119126.012048 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119126.012048 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119126.012048 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2259,28 +2266,28 @@ system.iocache.demand_mshr_misses::realview.ide 249 system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16710377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16710377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2222587461 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2222587461 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16710377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16710377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16710377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16710377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16713377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16713377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2228741309 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2228741309 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16713377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16713377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16713377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16713377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67109.947791 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67109.947791 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67121.995984 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67121.995984 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index be576cc47..8c1381ed5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram +memories=system.realview.nvmem system.physmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 787f38780..28734ef64 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:26:21 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:48:18 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x3fa4b00 0x3fa4b00 - 0: system.cpu1.isa: ISA system set to: 0x3fa4b00 0x3fa4b00 + 0: system.cpu0.isa: ISA system set to: 0x4989680 0x4989680 + 0: system.cpu1.isa: ISA system set to: 0x4989680 0x4989680 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e78ea31b3..fd62dd2fe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,15 +4,27 @@ sim_seconds 2.904683 # Nu sim_ticks 2904682547500 # Number of ticks simulated final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 708228 # Simulator instruction rate (inst/s) -host_op_rate 853902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18288406087 # Simulator tick rate (ticks/s) -host_mem_usage 555560 # Number of bytes of host memory used -host_seconds 158.83 # Real time elapsed on the host -sim_insts 112485368 # Number of instructions simulated -sim_ops 135622164 # Number of ops (including micro ops) simulated +host_inst_rate 680974 # Simulator instruction rate (inst/s) +host_op_rate 821042 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17584626781 # Simulator tick rate (ticks/s) +host_mem_usage 555668 # Number of bytes of host memory used +host_seconds 165.18 # Real time elapsed on the host +sim_insts 112485367 # Number of instructions simulated +sim_ops 135622163 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory @@ -117,7 +129,7 @@ system.physmem.perBankWrBursts::14 7309 # Pe system.physmem.perBankWrBursts::15 7126 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2904682126000 # Total gap between requests +system.physmem.totGap 2904682181000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) @@ -228,20 +240,20 @@ system.physmem.wrQLenPdf::60 18 # Wh system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.331590 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.690243 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.870742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21229 36.29% 36.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14764 25.24% 61.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5739 9.81% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3179 5.43% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2288 3.91% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1563 2.67% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1023 1.75% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1098 1.88% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7614 13.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.865343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5740 9.81% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3179 5.43% 76.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2292 3.92% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1563 2.67% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58500 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes @@ -283,12 +295,12 @@ system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Wr system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads -system.physmem.totQLat 1486718500 # Total ticks spent queuing -system.physmem.totMemAccLat 4649281000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1487003250 # Total ticks spent queuing +system.physmem.totMemAccLat 4649565750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8814.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8816.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27564.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27566.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s @@ -299,49 +311,37 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing -system.physmem.readRowHits 139009 # Number of row buffer hits during reads +system.physmem.readRowHits 139006 # Number of row buffer hits during reads system.physmem.writeRowHits 90713 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes -system.physmem.avgGap 9939406.19 # Average gap between requests +system.physmem.avgGap 9939406.38 # Average gap between requests system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2756104323000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2756104234500 # Time in different power states system.physmem.memoryStateTime::REF 96993520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 51578552000 # Time in different power states +system.physmem.memoryStateTime::ACT 51578640500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 224721000 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 217516320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 122615625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 118684500 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 122623875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 118688625 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ) system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86947680015 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 86005039095 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1666535934000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1667362812000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1944635925720 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1944428021475 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.484538 # Core power per rank (mW) -system.physmem.averagePower::1 669.412962 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 70577 # Transaction distribution -system.membus.trans_dist::ReadResp 70577 # Transaction distribution +system.physmem.actBackEnergy::0 86947691130 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 86007166335 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1666535924250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1667360946000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1944635950455 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1944428294400 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.484547 # Core power per rank (mW) +system.physmem.averagePower::1 669.413056 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 70576 # Transaction distribution +system.membus.trans_dist::ReadResp 70576 # Transaction distribution system.membus.trans_dist::WriteReq 27613 # Transaction distribution system.membus.trans_dist::WriteResp 27613 # Transaction distribution system.membus.trans_dist::Writeback 82818 # Transaction distribution @@ -353,21 +353,21 @@ system.membus.trans_dist::UpgradeResp 4512 # Tr system.membus.trans_dist::ReadExReq 129059 # Transaction distribution system.membus.trans_dist::ReadExResp 129059 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545872 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545870 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 618569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 618567 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15710305 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18029601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 219 # Total snoops (count) system.membus.snoop_fanout::samples 283020 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram @@ -382,13 +382,13 @@ system.membus.snoop_fanout::max_value 1 # Re system.membus.snoop_fanout::total 283020 # Request fanout histogram system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1336695500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1640330738 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1640331988 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) @@ -508,25 +508,25 @@ system.l2c.UpgradeReq_miss_latency::cpu1.data 231490 system.l2c.UpgradeReq_miss_latency::total 463980 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 45998 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 45998 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4342067899 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4342132899 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 4712323819 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9054391718 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9054456718 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 74500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 591637750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4732980399 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4733045399 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 566500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 717694500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 5241329319 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11284357968 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11284422968 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 74500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 591637750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4732980399 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4733045399 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 566500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 717694500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 5241329319 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11284357968 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11284422968 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 6207 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3384 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 844619 # number of ReadReq accesses(hits+misses) @@ -609,25 +609,25 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 161.767994 system.l2c.UpgradeReq_avg_miss_latency::total 170.080645 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 22999 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69654.745961 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69655.788681 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68789.031575 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69201.486675 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69201.983461 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 72584.682861 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70159.804314 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70160.767848 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 72729.479124 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 69400.438529 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70084.391551 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70084.795250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 72584.682861 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70159.804314 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70160.767848 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 72729.479124 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 69400.438529 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70084.391551 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70084.795250 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -683,36 +683,36 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14335431 system.l2c.UpgradeReq_mshr_miss_latency::total 27310228 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20002 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3544164101 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3544229101 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3834753681 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7378917782 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7378982782 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 488618750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3871171601 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3871236601 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 479000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 592932000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 4276118181 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9229444532 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9229509532 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 62500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 488618750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3871171601 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3871236601 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 479000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 592932000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 4276118181 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9229444532 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474790500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2494979250 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::total 9229509532 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474215000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2495734500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2890261000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5860030750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5860210500 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1979887500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2118425500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 4098313000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474790500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4474866750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474215000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4475622000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5008686500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9958343750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9958523500 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for ReadReq accesses @@ -758,25 +758,25 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56854.903204 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56855.945923 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55978.536742 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56396.066844 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56396.563631 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57384.696131 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57321.826037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57384.696131 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57321.826037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -826,8 +826,8 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2301461 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2301446 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2301460 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2301445 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution system.toL2Bus.trans_dist::Writeback 686956 # Transaction distribution @@ -837,16 +837,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 2 # Tr system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 295910 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 295910 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415394 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457263 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5925128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5925126 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868197 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46148 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205689601 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205689597 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 53732 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3283133 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram @@ -863,13 +863,13 @@ system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.toL2Bus.snoop_fanout::total 3283133 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4418861248 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 4418860748 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7658492249 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782893262 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3782893012 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1064,20 +1064,20 @@ system.cpu0.itb.accesses 58036248 # DT system.cpu0.numCycles 2905319694 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56513152 # Number of instructions committed -system.cpu0.committedOps 68067865 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60172056 # Number of integer alu accesses +system.cpu0.committedInsts 56513151 # Number of instructions committed +system.cpu0.committedOps 68067864 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60172055 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses system.cpu0.num_func_calls 4924591 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 7649382 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60172056 # number of integer instructions +system.cpu0.num_int_insts 60172055 # number of integer instructions system.cpu0.num_fp_insts 6287 # number of float instructions -system.cpu0.num_int_register_reads 109432778 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41532373 # number of times the integer registers were written +system.cpu0.num_int_register_reads 109432777 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41532372 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245794862 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26123490 # number of times the CC registers were written +system.cpu0.num_cc_register_reads 245794859 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26123489 # number of times the CC registers were written system.cpu0.num_mem_refs 22763355 # number of memory refs system.cpu0.num_load_insts 12450624 # Number of load instructions system.cpu0.num_store_insts 10312731 # Number of store instructions @@ -1087,7 +1087,7 @@ system.cpu0.not_idle_fraction 0.075576 # Pe system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles system.cpu0.Branches 12983474 # Number of branches fetched system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46789640 67.21% 67.21% # Class of executed instruction +system.cpu0.op_class::IntAlu 46789639 67.21% 67.21% # Class of executed instruction system.cpu0.op_class::IntMult 58624 0.08% 67.30% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction @@ -1120,7 +1120,7 @@ system.cpu0.op_class::MemRead 12450624 17.88% 85.19% # Cl system.cpu0.op_class::MemWrite 10312731 14.81% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69618096 # Class of executed instruction +system.cpu0.op_class::total 69618095 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 1698167 # number of replacements @@ -1222,10 +1222,10 @@ system.cpu0.icache.demand_mshr_miss_latency::total 19874171251 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830070251 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044101000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 19874171251 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 598490500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses @@ -1255,7 +1255,7 @@ system.cpu0.dcache.tags.total_refs 43241496 # To system.cpu0.dcache.tags.sampled_refs 823497 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 52.509597 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068899 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068900 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781856 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy @@ -1312,20 +1312,20 @@ system.cpu0.dcache.overall_misses::total 820469 # nu system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2867929500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3066278250 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 5934207750 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744425374 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744490374 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6031803093 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11776228467 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11776293467 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 135157750 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 145057500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 280215250 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52002 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 52002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8612354874 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8612419874 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu1.data 9098081343 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17710436217 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8612354874 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::total 17710501217 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8612419874 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 9098081343 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17710436217 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17710501217 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 11778885 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 11739375 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 23518260 # number of ReadReq accesses(hits+misses) @@ -1370,20 +1370,20 @@ system.cpu0.dcache.overall_miss_rate::total 0.019012 # system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14536.618683 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14919.319642 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.880595 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38246.448777 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38246.881547 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40627.504567 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.084500 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.302139 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12146.827537 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12456.633748 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12305.254260 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26001 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26001 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24784.824882 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24785.011940 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25701.520786 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25247.423240 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21211.913043 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25247.515901 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21212.073135 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21951.968959 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21585.746953 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21585.826176 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -1429,9 +1429,9 @@ system.cpu0.dcache.overall_mshr_misses::total 817721 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467791750 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647821500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115613250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416554578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416619578 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704545869 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121100447 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121165447 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles @@ -1440,21 +1440,21 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884346328 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884411328 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352367369 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16236713697 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580384578 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16236778697 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580449578 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094611369 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17674995947 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2687639750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17675060947 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688394500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5790667250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791422000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4852954750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4853709500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220469750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221224500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016725 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses @@ -1478,9 +1478,9 @@ system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.670914 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.865085 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12719.109819 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.481328 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.914098 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.247538 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.533886 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.751524 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency @@ -1489,12 +1489,12 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.501570 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.688783 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.807486 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.843160 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.664959 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.935903 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.825517 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22027.037543 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.946843 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21615.026332 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index e4e3f0a2b..aaf42338c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index c57bb127b..62e4f1a91 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:58:03 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x530db00 0x530db00 - 0: system.cpu1.isa: ISA system set to: 0x530db00 0x530db00 + 0: system.cpu0.isa: ISA system set to: 0x53ff680 0x53ff680 + 0: system.cpu1.isa: ISA system set to: 0x53ff680 0x53ff680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2802882496500 because m5_exit instruction encountered +Exiting @ tick 2802882713500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 53a29a0e7..560fdc0dc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,312 +1,313 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.802882 # Number of seconds simulated -sim_ticks 2802882496500 # Number of ticks simulated -final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.802883 # Number of seconds simulated +sim_ticks 2802882713500 # Number of ticks simulated +final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1330236 # Simulator instruction rate (inst/s) -host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25395755903 # Simulator tick rate (ticks/s) -host_mem_usage 564312 # Number of bytes of host memory used -host_seconds 110.37 # Real time elapsed on the host -sim_insts 146815698 # Number of instructions simulated -sim_ops 178892459 # Number of ops (including micro ops) simulated +host_inst_rate 1349319 # Simulator instruction rate (inst/s) +host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25757810314 # Simulator tick rate (ticks/s) +host_mem_usage 564420 # Number of bytes of host memory used +host_seconds 108.82 # Real time elapsed on the host +sim_insts 146828498 # Number of instructions simulated +sim_ops 178908222 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory -system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory +system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory +system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory +system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 75963 # Transaction distribution -system.membus.trans_dist::ReadResp 75963 # Transaction distribution -system.membus.trans_dist::WriteReq 30903 # Transaction distribution -system.membus.trans_dist::WriteResp 30903 # Transaction distribution -system.membus.trans_dist::Writeback 95019 # Transaction distribution +system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 75957 # Transaction distribution +system.membus.trans_dist::ReadResp 75957 # Transaction distribution +system.membus.trans_dist::WriteReq 30905 # Transaction distribution +system.membus.trans_dist::WriteResp 30905 # Transaction distribution +system.membus.trans_dist::Writeback 94881 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution -system.membus.trans_dist::ReadExReq 196321 # Transaction distribution -system.membus.trans_dist::ReadExResp 152216 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution +system.membus.trans_dist::ReadExReq 196326 # Transaction distribution +system.membus.trans_dist::ReadExResp 152193 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20432864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 460731 # Request fanout histogram +system.membus.snoop_fanout::samples 460689 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 460731 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460731 # Request fanout histogram +system.membus.snoop_fanout::total 460689 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 107723 # number of replacements -system.l2c.tags.tagsinuse 62123.921751 # Cycle average of tags in use -system.l2c.tags.total_refs 208051 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168144 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237338 # Average number of references to valid blocks. +system.l2c.tags.replacements 107632 # number of replacements +system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use +system.l2c.tags.total_refs 207938 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48622.171138 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.975943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7348.709599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3778.182164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1628.255131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 741.773959 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741915 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.112132 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.057357 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024845 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947936 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60415 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60384 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1884 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13069 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921860 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4905185 # Number of tag accesses -system.l2c.tags.data_accesses 4905185 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 74 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28057 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 75985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11512 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11347 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127129 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 225966 # number of Writeback hits -system.l2c.Writeback_hits::total 225966 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 512 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.921387 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4903910 # Number of tag accesses +system.l2c.tags.data_accesses 4903910 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits +system.l2c.ReadReq_hits::total 127193 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits +system.l2c.Writeback_hits::total 225882 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 577 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 56 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 11 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13971 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3083 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17054 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28057 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89956 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14430 # number of demand (read+write) hits -system.l2c.demand_hits::total 144183 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28057 # number of overall hits -system.l2c.overall_hits::cpu0.data 89956 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11512 # number of overall hits -system.l2c.overall_hits::cpu1.data 14430 # number of overall hits -system.l2c.overall_hits::total 144183 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses +system.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16962 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits +system.l2c.demand_hits::total 144155 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 59 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28044 # number of overall hits +system.l2c.overall_hits::cpu0.data 89938 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11456 # number of overall hits +system.l2c.overall_hits::cpu1.data 14516 # number of overall hits +system.l2c.overall_hits::total 144155 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16897 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11316 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2330 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1142 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31697 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9967 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3302 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13269 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 763 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1181 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1944 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15814 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152610 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31692 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 9982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152600 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16897 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 148112 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16888 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 148089 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2330 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16956 # number of demand (read+write) misses -system.l2c.demand_misses::total 184307 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2363 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16941 # number of demand (read+write) misses +system.l2c.demand_misses::total 184292 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16897 # number of overall misses -system.l2c.overall_misses::cpu0.data 148112 # number of overall misses +system.l2c.overall_misses::cpu0.inst 16888 # number of overall misses +system.l2c.overall_misses::cpu0.data 148089 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2330 # number of overall misses -system.l2c.overall_misses::cpu1.data 16956 # number of overall misses -system.l2c.overall_misses::total 184307 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 76 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 44954 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 87301 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 44 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13842 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12489 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 158826 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 225966 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225966 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10479 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3367 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13846 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2011 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150767 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18897 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169664 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44954 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238068 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 44 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13842 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31386 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328490 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44954 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238068 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 44 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13842 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31386 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328490 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.026316 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375873 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.129621 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.168328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.091440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.199571 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951140 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980695 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958327 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.931624 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.990772 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966683 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907334 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.836852 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899484 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.026316 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375873 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.622142 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.168328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.540241 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.561073 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.026316 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375873 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.622142 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.168328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses +system.l2c.overall_misses::cpu1.inst 2363 # number of overall misses +system.l2c.overall_misses::cpu1.data 16941 # number of overall misses +system.l2c.overall_misses::total 184292 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,8 +316,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95019 # number of writebacks -system.l2c.writebacks::total 95019 # number of writebacks +system.l2c.writebacks::writebacks 94881 # number of writebacks +system.l2c.writebacks::total 94881 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -355,34 +356,34 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram system.iobus.trans_dist::ReadReq 31002 # Transaction distribution system.iobus.trans_dist::ReadResp 31002 # Transaction distribution system.iobus.trans_dist::WriteReq 59433 # Transaction distribution @@ -461,9 +462,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20338466 # DTB read hits +system.cpu0.dtb.read_hits 20339791 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16389914 # DTB write hits +system.cpu0.dtb.write_hits 16391007 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -474,12 +475,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20345337 # DTB read accesses -system.cpu0.dtb.write_accesses 16391007 # DTB write accesses +system.cpu0.dtb.read_accesses 20346662 # DTB read accesses +system.cpu0.dtb.write_accesses 16392100 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36728380 # DTB hits +system.cpu0.dtb.hits 36730798 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36736344 # DTB accesses +system.cpu0.dtb.accesses 36738762 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -501,7 +502,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 97433991 # ITB inst hits +system.cpu0.itb.inst_hits 97439560 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -518,38 +519,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses -system.cpu0.itb.hits 97433991 # DTB hits +system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses +system.cpu0.itb.hits 97439560 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97437349 # DTB accesses -system.cpu0.numCycles 5605766965 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442918 # DTB accesses +system.cpu0.numCycles 5605767393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95421538 # Number of instructions committed -system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses +system.cpu0.committedInsts 95427097 # Number of instructions committed +system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 7999979 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100756647 # number of integer instructions +system.cpu0.num_func_calls 8000275 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762762 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written -system.cpu0.num_mem_refs 37871263 # number of memory refs -system.cpu0.num_load_insts 20596038 # Number of load instructions -system.cpu0.num_store_insts 17275225 # Number of store instructions -system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles -system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles -system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles -system.cpu0.Branches 21940727 # Number of branches fetched +system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873781 # number of memory refs +system.cpu0.num_load_insts 20597370 # Number of load instructions +system.cpu0.num_store_insts 17276411 # Number of store instructions +system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles +system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles +system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles +system.cpu0.Branches 21941666 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -577,19 +578,19 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116875407 # Class of executed instruction +system.cpu0.op_class::total 116882229 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1109428 # number of replacements +system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1109631 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy @@ -598,32 +599,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195982615 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195982615 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96326384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96326384 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96326384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96326384 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96326384 # number of overall hits -system.cpu0.icache.overall_hits::total 96326384 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1109949 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1109949 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1109949 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1109949 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1109949 # number of overall misses -system.cpu0.icache.overall_misses::total 1109949 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97436333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97436333 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97436333 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97436333 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97436333 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011392 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011392 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011392 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011392 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011392 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011392 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits +system.cpu0.icache.overall_hits::total 96331750 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses +system.cpu0.icache.overall_misses::total 1110152 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441902 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441902 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441902 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441902 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441902 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441902 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,123 +643,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 252470 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16140.899010 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1809063 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268660 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.733652 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 1814551000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8130.897895 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.403919 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.095149 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4678.277611 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3330.224436 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.496271 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000086 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285539 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.203261 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985162 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5558 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 252387 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16137.494570 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1809761 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268581 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.738232 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.802195 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.197687 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081095 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.849314 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.564278 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201328 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16188 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5625 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7524 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39435786 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39435786 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7516 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3210 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1064995 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 352145 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1427866 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511188 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511188 # number of Writeback hits +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39447588 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39447588 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7603 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3246 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065220 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351970 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428039 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511617 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511617 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94088 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94088 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7516 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3210 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1064995 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446233 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1521954 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7516 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3210 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1064995 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446233 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1521954 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44954 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128031 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173336 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26217 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26217 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18426 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18426 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175429 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175429 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44954 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303460 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44954 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303460 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7732 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3345 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1109949 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480176 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601202 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511188 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511188 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26234 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26234 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18426 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18426 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7732 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3345 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1109949 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749693 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1870719 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7732 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3345 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1109949 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749693 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1870719 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040359 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040501 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266633 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108254 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94214 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94214 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7603 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3246 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065220 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446184 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522253 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7603 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3246 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065220 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446184 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522253 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 205 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 119 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44932 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128186 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173442 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26232 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26232 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175300 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175300 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 205 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 119 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44932 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303486 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348742 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 205 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 119 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44932 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303486 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348742 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7808 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3365 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601481 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,81 +768,81 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks -system.cpu0.l2cache.writebacks::total 192932 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks +system.cpu0.l2cache.writebacks::total 192916 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 693475 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.745909 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35929913 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966301 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966301 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 693468 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15689235 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15689235 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346054 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34796558 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34796558 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35142612 # number of overall hits -system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295751 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100324 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668861 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769185 # number of overall misses -system.cpu0.dcache.overall_misses::total 769185 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19480433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446378 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses +system.cpu0.dcache.overall_misses::total 769179 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,45 +851,45 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks -system.cpu0.dcache.writebacks::total 511188 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks +system.cpu0.dcache.writebacks::total 511617 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 321922 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322119 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -912,9 +913,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12172110 # DTB read hits +system.cpu1.dtb.read_hits 12173926 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7585805 # DTB write hits +system.cpu1.dtb.write_hits 7587211 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -925,12 +926,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12174963 # DTB read accesses -system.cpu1.dtb.write_accesses 7586311 # DTB write accesses +system.cpu1.dtb.read_accesses 12176779 # DTB read accesses +system.cpu1.dtb.write_accesses 7587717 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19757915 # DTB hits +system.cpu1.dtb.hits 19761137 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19761274 # DTB accesses +system.cpu1.dtb.accesses 19764496 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -952,7 +953,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 53664371 # ITB inst hits +system.cpu1.itb.inst_hits 53671662 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -969,38 +970,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses -system.cpu1.itb.hits 53664371 # DTB hits +system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses +system.cpu1.itb.hits 53671662 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53666105 # DTB accesses -system.cpu1.numCycles 5605295863 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673396 # DTB accesses +system.cpu1.numCycles 5605296302 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51394160 # Number of instructions committed -system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses +system.cpu1.committedInsts 51401401 # Number of instructions committed +system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170283 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56976202 # number of integer instructions +system.cpu1.num_func_calls 9170855 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984315 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written -system.cpu1.num_mem_refs 20022980 # number of memory refs -system.cpu1.num_load_insts 12287666 # Number of load instructions -system.cpu1.num_store_insts 7735314 # Number of store instructions -system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles -system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles -system.cpu1.Branches 15216192 # Number of branches fetched +system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026390 # number of memory refs +system.cpu1.num_load_insts 12289548 # Number of load instructions +system.cpu1.num_store_insts 7736842 # Number of store instructions +system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles +system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles +system.cpu1.Branches 15217497 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -1024,56 +1025,56 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65450545 # Class of executed instruction +system.cpu1.op_class::total 65459543 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 523179 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 523402 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits -system.cpu1.icache.overall_hits::total 53141770 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses -system.cpu1.icache.overall_misses::total 523691 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits +system.cpu1.icache.overall_hits::total 53148838 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses +system.cpu1.icache.overall_misses::total 523914 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1092,121 +1093,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 48552 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15311.760536 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716558 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63379 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.305922 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48605 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8243.045220 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.958358 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015688 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3303.816337 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.924934 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.503116 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201649 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229488 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934556 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14809 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 540 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9336 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4933 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903870 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15206583 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15206583 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3143 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1725 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 509849 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99406 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614123 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120669 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120669 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19820 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19820 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3143 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1725 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 509849 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119226 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 633943 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3143 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1725 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 509849 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119226 # number of overall hits -system.cpu1.l2cache.overall_hits::total 633943 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13842 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73217 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87678 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28845 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28845 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22527 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22527 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43793 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43793 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13842 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117010 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131471 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13842 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117010 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131471 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3491 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523691 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172623 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 701801 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120669 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120669 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28853 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28853 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22527 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22527 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63613 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63613 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3491 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 523691 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 236236 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3491 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 523691 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 236236 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135772 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026432 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424144 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.124933 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9351 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4901 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15213580 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15213580 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3243 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1759 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510095 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99336 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614433 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120654 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19759 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19759 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3243 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1759 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510095 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119095 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634192 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3243 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1759 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510095 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119095 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634192 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 343 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13819 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73339 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87768 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28855 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28855 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22557 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22557 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43856 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43856 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 343 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13819 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117195 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131624 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 343 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13819 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117195 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131624 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3586 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2026 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 702201 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 765816 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3586 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2026 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 765816 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.131787 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026376 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688428 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688428 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135772 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026432 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495310 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171765 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135772 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026432 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495310 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171765 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1215,80 +1216,80 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 33034 # number of writebacks -system.cpu1.l2cache.writebacks::total 33034 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks +system.cpu1.l2cache.writebacks::total 32966 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 191901 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.757627 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19500351 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192255 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.429617 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105851562500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 191947 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7396120 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits -system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30716 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229056 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259772 # number of overall misses -system.cpu1.dcache.overall_misses::total 259772 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306283 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses +system.cpu1.dcache.overall_misses::total 259834 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1297,52 +1298,52 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks -system.cpu1.dcache.writebacks::total 120669 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks +system.cpu1.dcache.writebacks::total 120654 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707355 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1773789 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33516936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22861090 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499577 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499552 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 8b9ee8e26..ce59aa175 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 624db6e54..f25d6db4c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:56:38 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x55e4b00 0x55e4b00 + 0: system.cpu.isa: ISA system set to: 0x5299680 0x5299680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 @@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2783853461500 because m5_exit instruction encountered +Exiting @ tick 2783854177000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e8036ea95..5bbc68c06 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783853 # Number of seconds simulated -sim_ticks 2783853461500 # Number of ticks simulated -final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783854177000 # Number of ticks simulated +final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1369296 # Simulator instruction rate (inst/s) -host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26699855189 # Simulator tick rate (ticks/s) -host_mem_usage 553552 # Number of bytes of host memory used -host_seconds 104.26 # Real time elapsed on the host -sim_insts 142769281 # Number of instructions simulated -sim_ops 173798567 # Number of ops (including micro ops) simulated +host_inst_rate 1378246 # Simulator instruction rate (inst/s) +host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26874016957 # Simulator tick rate (ticks/s) +host_mem_usage 553624 # Number of bytes of host memory used +host_seconds 103.59 # Real time elapsed on the host +sim_insts 142771179 # Number of instructions simulated +sim_ops 173800939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory @@ -21,56 +21,56 @@ system.physmem.bytes_read::cpu.data 10345892 # Nu system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory +system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74236 # Transaction distribution -system.membus.trans_dist::ReadResp 74236 # Transaction distribution +system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74235 # Transaction distribution +system.membus.trans_dist::ReadResp 74235 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101898 # Transaction distribution +system.membus.trans_dist::Writeback 101899 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -79,33 +79,33 @@ system.membus.trans_dist::UpgradeResp 4509 # Tr system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322857 # Request fanout histogram +system.membus.snoop_fanout::samples 322858 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322857 # Request fanout histogram +system.membus.snoop_fanout::total 322858 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -222,9 +222,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525428 # DTB read hits +system.cpu.dtb.read_hits 31525864 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23123837 # DTB write hits +system.cpu.dtb.write_hits 23124034 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -235,12 +235,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534008 # DTB read accesses -system.cpu.dtb.write_accesses 23125285 # DTB write accesses +system.cpu.dtb.read_accesses 31534444 # DTB read accesses +system.cpu.dtb.write_accesses 23125482 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54649265 # DTB hits +system.cpu.dtb.hits 54649898 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54659293 # DTB accesses +system.cpu.dtb.accesses 54659926 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -262,7 +262,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 147035651 # ITB inst hits +system.cpu.itb.inst_hits 147037671 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -279,38 +279,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147040413 # ITB inst accesses -system.cpu.itb.hits 147035651 # DTB hits +system.cpu.itb.inst_accesses 147042433 # ITB inst accesses +system.cpu.itb.hits 147037671 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147040413 # DTB accesses -system.cpu.numCycles 5567710004 # number of cpu cycles simulated +system.cpu.itb.accesses 147042433 # DTB accesses +system.cpu.numCycles 5567711435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142769281 # Number of instructions committed -system.cpu.committedOps 173798567 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses +system.cpu.committedInsts 142771179 # Number of instructions committed +system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls -system.cpu.num_int_insts 153158502 # number of integer instructions +system.cpu.num_func_calls 16873782 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls +system.cpu.num_int_insts 153160639 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285052059 # number of times the integer registers were read -system.cpu.num_int_register_writes 107176408 # number of times the integer registers were written +system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read +system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written -system.cpu.num_mem_refs 55937812 # number of memory refs -system.cpu.num_load_insts 31855061 # Number of load instructions -system.cpu.num_store_insts 24082751 # Number of store instructions -system.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles -system.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles -system.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.968016 # Percentage of idle cycles -system.cpu.Branches 36396067 # Number of branches fetched +system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written +system.cpu.num_mem_refs 55938446 # number of memory refs +system.cpu.num_load_insts 31855497 # Number of load instructions +system.cpu.num_store_insts 24082949 # Number of store instructions +system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles +system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles +system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.968015 # Percentage of idle cycles +system.cpu.Branches 36396779 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -338,19 +338,19 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177215263 # Class of executed instruction +system.cpu.op_class::total 177217756 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 1698994 # number of replacements +system.cpu.icache.tags.replacements 1699006 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy @@ -360,26 +360,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148738270 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits -system.cpu.icache.overall_hits::total 145339246 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses -system.cpu.icache.overall_misses::total 1699512 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits +system.cpu.icache.overall_hits::total 145341254 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses +system.cpu.icache.overall_misses::total 1699524 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -396,16 +396,16 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -422,29 +422,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348887 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses @@ -468,47 +468,47 @@ system.cpu.l2cache.overall_misses::cpu.data 163398 # system.cpu.l2cache.overall_misses::total 181765 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -518,15 +518,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks -system.cpu.l2cache.writebacks::total 101898 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks +system.cpu.l2cache.writebacks::total 101899 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -535,56 +535,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits -system.cpu.dcache.overall_hits::total 52862837 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits +system.cpu.dcache.overall_hits::total 52863480 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses -system.cpu.dcache.overall_misses::total 814075 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses @@ -601,29 +601,29 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682038 # number of writebacks -system.cpu.dcache.writebacks::total 682038 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks +system.cpu.dcache.writebacks::total 682036 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36632 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram @@ -641,12 +641,12 @@ system.cpu.toL2Bus.snoop_fanout::min_value 5 # system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 1f2cdefde..a40d111c2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 0ab3b3eb3..f808cc158 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:58:33 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x5550b00 0x5550b00 - 0: system.cpu1.isa: ISA system set to: 0x5550b00 0x5550b00 + 0: system.cpu0.isa: ISA system set to: 0x4f96680 0x4f96680 + 0: system.cpu1.isa: ISA system set to: 0x4f96680 0x4f96680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2866929256000 because m5_exit instruction encountered +Exiting @ tick 2866923142000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 391ab3c97..00e66bf9d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,185 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.866929 # Number of seconds simulated -sim_ticks 2866929256000 # Number of ticks simulated -final_tick 2866929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.866923 # Number of seconds simulated +sim_ticks 2866923142000 # Number of ticks simulated +final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 703930 # Simulator instruction rate (inst/s) -host_op_rate 851474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15295798763 # Simulator tick rate (ticks/s) -host_mem_usage 599572 # Number of bytes of host memory used -host_seconds 187.43 # Real time elapsed on the host -sim_insts 131939289 # Number of instructions simulated -sim_ops 159593891 # Number of ops (including micro ops) simulated +host_inst_rate 699616 # Simulator instruction rate (inst/s) +host_op_rate 846245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15203294122 # Simulator tick rate (ticks/s) +host_mem_usage 599680 # Number of bytes of host memory used +host_seconds 188.57 # Real time elapsed on the host +sim_insts 131928295 # Number of instructions simulated +sim_ops 159578500 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 234148 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 830144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9620672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 440928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365312 # Number of bytes read from this memory -system.physmem.bytes_read::total 12542872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 234148 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory +system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 284024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6392960 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8729040 # Number of bytes written to this memory +system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 150323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 21333 # Number of read requests responded to by this memory -system.physmem.num_reads::total 205140 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 99890 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory +system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140550 # Number of write requests responded to by this memory +system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 289559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3355741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 153798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 476228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4375020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81672 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2229898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 808648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3044735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2229898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 808983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 295734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3355741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 153812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 476228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7419755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 205141 # Number of read requests accepted -system.physmem.writeReqs 140550 # Number of write requests accepted -system.physmem.readBursts 205141 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140550 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13114752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14272 # Total number of bytes read from write queue -system.physmem.bytesWritten 8743552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12542936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8729040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 223 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3913 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15151 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12845 # Per bank write bursts -system.physmem.perBankRdBursts::1 12298 # Per bank write bursts -system.physmem.perBankRdBursts::2 13022 # Per bank write bursts -system.physmem.perBankRdBursts::3 12754 # Per bank write bursts -system.physmem.perBankRdBursts::4 21257 # Per bank write bursts -system.physmem.perBankRdBursts::5 12515 # Per bank write bursts -system.physmem.perBankRdBursts::6 12829 # Per bank write bursts -system.physmem.perBankRdBursts::7 12945 # Per bank write bursts -system.physmem.perBankRdBursts::8 12057 # Per bank write bursts +system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 205337 # Number of read requests accepted +system.physmem.writeReqs 140504 # Number of write requests accepted +system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue +system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12555480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8726096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 262 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15133 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12897 # Per bank write bursts +system.physmem.perBankRdBursts::1 12279 # Per bank write bursts +system.physmem.perBankRdBursts::2 13044 # Per bank write bursts +system.physmem.perBankRdBursts::3 12666 # Per bank write bursts +system.physmem.perBankRdBursts::4 21207 # Per bank write bursts +system.physmem.perBankRdBursts::5 12512 # Per bank write bursts +system.physmem.perBankRdBursts::6 12819 # Per bank write bursts +system.physmem.perBankRdBursts::7 13070 # Per bank write bursts +system.physmem.perBankRdBursts::8 12092 # Per bank write bursts system.physmem.perBankRdBursts::9 12100 # Per bank write bursts -system.physmem.perBankRdBursts::10 12212 # Per bank write bursts -system.physmem.perBankRdBursts::11 11004 # Per bank write bursts -system.physmem.perBankRdBursts::12 11810 # Per bank write bursts -system.physmem.perBankRdBursts::13 12145 # Per bank write bursts -system.physmem.perBankRdBursts::14 11734 # Per bank write bursts -system.physmem.perBankRdBursts::15 11391 # Per bank write bursts -system.physmem.perBankWrBursts::0 8757 # Per bank write bursts -system.physmem.perBankWrBursts::1 8655 # Per bank write bursts -system.physmem.perBankWrBursts::2 9184 # Per bank write bursts -system.physmem.perBankWrBursts::3 8823 # Per bank write bursts -system.physmem.perBankWrBursts::4 8606 # Per bank write bursts -system.physmem.perBankWrBursts::5 8736 # Per bank write bursts -system.physmem.perBankWrBursts::6 8840 # Per bank write bursts -system.physmem.perBankWrBursts::7 8881 # Per bank write bursts -system.physmem.perBankWrBursts::8 8404 # Per bank write bursts -system.physmem.perBankWrBursts::9 8549 # Per bank write bursts -system.physmem.perBankWrBursts::10 8595 # Per bank write bursts -system.physmem.perBankWrBursts::11 8133 # Per bank write bursts -system.physmem.perBankWrBursts::12 8369 # Per bank write bursts -system.physmem.perBankWrBursts::13 8306 # Per bank write bursts -system.physmem.perBankWrBursts::14 8199 # Per bank write bursts -system.physmem.perBankWrBursts::15 7581 # Per bank write bursts +system.physmem.perBankRdBursts::10 12291 # Per bank write bursts +system.physmem.perBankRdBursts::11 10982 # Per bank write bursts +system.physmem.perBankRdBursts::12 11837 # Per bank write bursts +system.physmem.perBankRdBursts::13 12135 # Per bank write bursts +system.physmem.perBankRdBursts::14 11741 # Per bank write bursts +system.physmem.perBankRdBursts::15 11403 # Per bank write bursts +system.physmem.perBankWrBursts::0 8736 # Per bank write bursts +system.physmem.perBankWrBursts::1 8619 # Per bank write bursts +system.physmem.perBankWrBursts::2 9216 # Per bank write bursts +system.physmem.perBankWrBursts::3 8724 # Per bank write bursts +system.physmem.perBankWrBursts::4 8630 # Per bank write bursts +system.physmem.perBankWrBursts::5 8715 # Per bank write bursts +system.physmem.perBankWrBursts::6 8820 # Per bank write bursts +system.physmem.perBankWrBursts::7 8946 # Per bank write bursts +system.physmem.perBankWrBursts::8 8394 # Per bank write bursts +system.physmem.perBankWrBursts::9 8545 # Per bank write bursts +system.physmem.perBankWrBursts::10 8627 # Per bank write bursts +system.physmem.perBankWrBursts::11 8114 # Per bank write bursts +system.physmem.perBankWrBursts::12 8397 # Per bank write bursts +system.physmem.perBankWrBursts::13 8288 # Per bank write bursts +system.physmem.perBankWrBursts::14 8182 # Per bank write bursts +system.physmem.perBankWrBursts::15 7606 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2866928814500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 2866922767000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 195371 # Read request sizes (log2) +system.physmem.readPktSize::6 195567 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136114 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 121124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 501 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136068 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 121119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 7029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 5390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -209,117 +191,120 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 80974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.941463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.852686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.869933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39277 48.51% 48.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16073 19.85% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6267 7.74% 76.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3406 4.21% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3201 3.95% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1947 2.40% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1140 1.41% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1004 1.24% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8659 10.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 80974 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.475461 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 574.843547 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6723 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.317965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.827449 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.656598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5486 81.59% 81.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 426 6.34% 87.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.22% 89.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 201 2.99% 92.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 197 2.93% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.31% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.28% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.24% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 29 0.43% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.07% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.04% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 175 2.60% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.12% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.10% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 6 0.09% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads -system.physmem.totQLat 5972474500 # Total ticks spent queuing -system.physmem.totMemAccLat 9814687000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1024590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29145.68 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 81121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.529616 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 151.748883 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.565122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39339 48.49% 48.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16179 19.94% 68.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6333 7.81% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3376 4.16% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3166 3.90% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1954 2.41% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1081 1.33% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1008 1.24% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8685 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81121 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.132444 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6710 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5518 82.21% 82.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.34% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.18% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads +system.physmem.totQLat 6009454502 # Total ticks spent queuing +system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47895.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s @@ -327,584 +312,607 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing -system.physmem.readRowHits 175001 # Number of row buffer hits during reads -system.physmem.writeRowHits 85560 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.62 # Row buffer hit rate for writes -system.physmem.avgGap 8293327.90 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731384342500 # Time in different power states -system.physmem.memoryStateTime::REF 95733040000 # Time in different power states +system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing +system.physmem.readRowHits 175010 # Number of row buffer hits during reads +system.physmem.writeRowHits 85502 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes +system.physmem.avgGap 8289713.39 # Average gap between requests +system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states +system.physmem.memoryStateTime::REF 95732780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 39811853000 # Time in different power states +system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 323167320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 288996120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 176331375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 157686375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 861627000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 736725600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 456723360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 428561280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187253826240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187253826240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82374692850 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81185757210 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647898682250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648941608250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919345050395 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1918993161075 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.477790 # Core power per rank (mW) -system.physmem.averagePower::1 669.355049 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 228441 # Transaction distribution -system.membus.trans_dist::ReadResp 228440 # Transaction distribution -system.membus.trans_dist::WriteReq 31177 # Transaction distribution -system.membus.trans_dist::WriteResp 31177 # Transaction distribution -system.membus.trans_dist::Writeback 99890 # Transaction distribution +system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.491656 # Core power per rank (mW) +system.physmem.averagePower::1 669.352997 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 228669 # Transaction distribution +system.membus.trans_dist::ReadResp 228668 # Transaction distribution +system.membus.trans_dist::WriteReq 31179 # Transaction distribution +system.membus.trans_dist::WriteResp 31179 # Transaction distribution +system.membus.trans_dist::Writeback 99844 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85859 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41212 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15151 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 28398 # Transaction distribution -system.membus.trans_dist::ReadExResp 11478 # Transaction distribution +system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 28316 # Transaction distribution +system.membus.trans_dist::ReadExResp 11444 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 800720 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 873436 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18952616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19144659 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21463955 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129081 # Total snoops (count) -system.membus.snoop_fanout::samples 475718 # Request fanout histogram +system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 128959 # Total snoops (count) +system.membus.snoop_fanout::samples 475734 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 475718 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 475718 # Request fanout histogram -system.membus.reqLayer0.occupancy 88161999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 475734 # Request fanout histogram +system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 20500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12079498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1514580499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1969894164 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38592409 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 132728 # number of replacements -system.l2c.tags.tagsinuse 64199.829322 # Cycle average of tags in use -system.l2c.tags.total_refs 489645 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197292 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.481829 # Average number of references to valid blocks. +system.l2c.tags.replacements 132855 # number of replacements +system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use +system.l2c.tags.total_refs 486769 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12574.713731 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.829645 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1158.059566 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1408.624866 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38786.462390 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.540569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007801 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.338892 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 908.008157 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8820.200180 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.191875 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017671 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021494 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.591834 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000039 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008184 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134586 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979612 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44718 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19841 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5098 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39452 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1574 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18054 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.682343 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.302750 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6148253 # Number of tag accesses -system.l2c.tags.data_accesses 6148253 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 159 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 10419 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 29225 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168428 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 62 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4147 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 10318 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47800 # number of ReadReq hits -system.l2c.ReadReq_hits::total 270735 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 240561 # number of Writeback hits -system.l2c.Writeback_hits::total 240561 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 9666 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1017 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10683 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 240 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 136 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4189 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2493 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6682 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 159 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 10419 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 33414 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 168428 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 62 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4147 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 47800 # number of demand (read+write) hits -system.l2c.demand_hits::total 277417 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 127 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 159 # number of overall hits -system.l2c.overall_hits::cpu0.inst 10419 # number of overall hits -system.l2c.overall_hits::cpu0.data 33414 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 168428 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 62 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4147 # number of overall hits -system.l2c.overall_hits::cpu1.data 12811 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 47800 # number of overall hits -system.l2c.overall_hits::total 277417 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6123027 # Number of tag accesses +system.l2c.tags.data_accesses 6123027 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits +system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits +system.l2c.Writeback_hits::total 239796 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits +system.l2c.demand_hits::total 274907 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits +system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits +system.l2c.overall_hits::cpu0.data 33021 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 166586 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits +system.l2c.overall_hits::cpu1.inst 4197 # number of overall hits +system.l2c.overall_hits::cpu1.data 12797 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 47730 # number of overall hits +system.l2c.overall_hits::total 274907 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3095 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6926 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3114 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6976 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 769 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1418 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq misses -system.l2c.ReadReq_misses::total 183878 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8558 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4221 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12779 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 889 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1310 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2199 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 6118 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5533 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 11651 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.data 1415 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq misses +system.l2c.ReadReq_misses::total 184109 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8503 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4264 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 881 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1309 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2190 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 6116 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5504 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 11620 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3095 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 13044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3114 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 13092 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 769 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6951 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) misses -system.l2c.demand_misses::total 195529 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.demand_misses::cpu1.data 6919 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) misses +system.l2c.demand_misses::total 195729 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3095 # number of overall misses -system.l2c.overall_misses::cpu0.data 13044 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 150324 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3114 # number of overall misses +system.l2c.overall_misses::cpu0.data 13092 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 150483 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 769 # number of overall misses -system.l2c.overall_misses::cpu1.data 6951 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 21333 # number of overall misses -system.l2c.overall_misses::total 195529 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 510000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.data 6919 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 21339 # number of overall misses +system.l2c.overall_misses::total 195729 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 706500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 268587999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 563686749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 328000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 94250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 70493000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 122227750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18379241574 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8946128 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10070574 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 19016702 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1175950 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2179907 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3355857 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 485246640 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 404862686 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 890109326 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 510000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 269607250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 570989749 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 266750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 88750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 69445999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 122855750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18430164853 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8530144 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 9612086 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 18142230 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132453 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2244405 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3376858 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 492352141 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 397195181 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 889547322 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 706500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 268587999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1048933389 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 328000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 94250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 70493000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 527090436 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19269350900 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 510000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 269607250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1063341890 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 266750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 88750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 69445999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 520050931 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19319712175 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 706500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 268587999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1048933389 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 328000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 94250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 70493000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 527090436 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19269350900 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 134 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 160 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 13514 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 36151 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 66 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 4916 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11736 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69133 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 454613 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 240561 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 240561 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 18224 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5238 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 23462 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 269607250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1063341890 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 266750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 88750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 69445999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 520050931 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19319712175 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 146 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 134 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 13324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 35839 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 317069 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 52 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 4966 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 11686 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69069 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 452332 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 239796 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 239796 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 18165 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5198 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 23363 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1129 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1446 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2575 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 10307 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 8026 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18333 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 134 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 160 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 13514 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 46458 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318752 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 66 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 4916 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19762 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69133 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 472946 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 134 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 160 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 13514 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 46458 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318752 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 66 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 4916 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19762 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69133 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 472946 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.229022 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.191585 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.156428 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.120825 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.404471 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.469601 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805842 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.544668 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787422 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.905947 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.853981 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.593577 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.689385 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.635521 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.006250 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.229022 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.280770 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.156428 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.351736 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.413428 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.006250 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.229022 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.280770 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.156428 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.351736 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.413428 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average ReadReq miss latency +system.l2c.SCUpgradeReq_accesses::cpu1.data 1460 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2589 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 10274 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8030 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18304 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 146 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 134 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 13324 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 46113 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 317069 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 4966 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 19716 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69069 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 470636 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 146 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 134 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 13324 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 46113 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 317069 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 4966 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 19716 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69069 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 470636 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007463 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.233714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.194648 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021277 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.154853 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.121085 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.407022 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.468098 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.820316 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.546462 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.780337 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.896575 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.845886 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.595289 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.685430 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.634834 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.007463 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.233714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.283911 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.021277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.154853 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.350933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.415882 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.007463 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.233714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.283911 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.154853 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.350933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.415882 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86781.259774 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 81387.055876 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 94250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91668.400520 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 86197.284908 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 99953.455954 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1045.352652 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2385.826581 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1488.121293 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1322.778403 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1664.051145 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1526.083220 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79314.586466 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73172.363275 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76397.676251 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86579.078356 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 81850.594753 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90306.890767 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 86823.851590 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 100104.638301 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.192285 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2254.241557 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1421.025300 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1285.417707 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1714.595111 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1541.944292 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80502.312132 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72164.822129 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76553.125818 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98549.836086 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 98706.436834 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98549.836086 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 98706.436834 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99890 # number of writebacks -system.l2c.writebacks::total 99890 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 99844 # number of writebacks +system.l2c.writebacks::total 99844 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 3095 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6926 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3114 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6976 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 769 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1418 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 183878 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8558 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4221 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12779 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 889 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1310 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2199 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 6118 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5533 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 11651 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1414 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 184108 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8503 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4264 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12767 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 881 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1309 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2190 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 6116 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5504 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 11620 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 3095 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 13044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3114 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 13092 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 769 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6951 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195529 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6918 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 195728 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 3095 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 13044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 3114 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 13092 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 769 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6951 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195529 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 423500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.data 6918 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 195728 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 607500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230146499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 477536249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 278000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 81250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60929000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 104521250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16097880074 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86272013 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42559203 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 128831216 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8927886 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13175305 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 22103191 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 408771858 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 334873814 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 743645672 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 423500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230914750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 484247749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 228750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59892499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105166750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 16146124355 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 85791947 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42794256 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 128586203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8846879 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13136807 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 21983686 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 415913357 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 327528317 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 743441674 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 607500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 230146499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 886308107 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 278000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 81250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 60929000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 439395064 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16841525746 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 423500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 230914750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 900161106 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 228750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 59892499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 432695067 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16889566029 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 607500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 230146499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 886308107 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 278000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 81250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 60929000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 439395064 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16841525746 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476853500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4797337250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9261250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814340500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6097792500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540127500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712608500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4252736000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476853500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337464750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9261250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526949000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10350528500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191585 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120825 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.404471 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.469601 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.805842 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.544668 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787422 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.905947 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.853981 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593577 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.689385 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.635521 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.413428 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.413428 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 230914750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 900161106 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 228750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 59892499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 432695067 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16889566029 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796970001 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814272500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6097046501 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540071000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712688499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4252759499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337041001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526960999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10349806000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.194648 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120999 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.407020 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.468098 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.820316 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.546462 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.780337 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.896575 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845886 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595289 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.685430 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.634834 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.415880 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.415880 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69416.248423 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74375.353607 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87699.200225 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.609197 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10071.763374 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10041.860386 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10038.212785 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68004.146010 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59507.325036 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63979.490017 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -956,50 +964,50 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 633918 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 633902 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31177 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31177 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 240561 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 96369 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41588 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137957 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39943 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39943 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1258028 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 400059 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1658087 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37640280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8288315 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45928595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 305065 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1044371 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.034928 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.183598 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 304794 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1007893 96.51% 96.51% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36478 3.49% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1044371 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1521180751 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2136308825 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 850635338 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31019 # Transaction distribution system.iobus.trans_dist::ReadResp 31019 # Transaction distribution -system.iobus.trans_dist::WriteReq 59408 # Transaction distribution +system.iobus.trans_dist::WriteReq 59414 # Transaction distribution system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 32 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1090,13 +1098,13 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326676322 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36842591 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1121,25 +1129,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24353899 # DTB read hits -system.cpu0.dtb.read_misses 6408 # DTB read misses -system.cpu0.dtb.write_hits 18126722 # DTB write hits -system.cpu0.dtb.write_misses 1115 # DTB write misses +system.cpu0.dtb.read_hits 24351510 # DTB read hits +system.cpu0.dtb.read_misses 6410 # DTB read misses +system.cpu0.dtb.write_hits 18124813 # DTB write hits +system.cpu0.dtb.write_misses 1105 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1442 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24360307 # DTB read accesses -system.cpu0.dtb.write_accesses 18127837 # DTB write accesses +system.cpu0.dtb.read_accesses 24357920 # DTB read accesses +system.cpu0.dtb.write_accesses 18125918 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42480621 # DTB hits -system.cpu0.dtb.misses 7523 # DTB misses -system.cpu0.dtb.accesses 42488144 # DTB accesses +system.cpu0.dtb.hits 42476323 # DTB hits +system.cpu0.dtb.misses 7515 # DTB misses +system.cpu0.dtb.accesses 42483838 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1161,8 +1169,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 115074724 # ITB inst hits -system.cpu0.itb.inst_misses 3350 # ITB inst misses +system.cpu0.itb.inst_hits 115065468 # ITB inst hits +system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1171,45 +1179,45 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 115078074 # ITB inst accesses -system.cpu0.itb.hits 115074724 # DTB hits -system.cpu0.itb.misses 3350 # DTB misses -system.cpu0.itb.accesses 115078074 # DTB accesses -system.cpu0.numCycles 5733858512 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses +system.cpu0.itb.hits 115065468 # DTB hits +system.cpu0.itb.misses 3349 # DTB misses +system.cpu0.itb.accesses 115068817 # DTB accesses +system.cpu0.numCycles 5733846284 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 111430460 # Number of instructions committed -system.cpu0.committedOps 134719109 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 119427816 # Number of integer alu accesses +system.cpu0.committedInsts 111421342 # Number of instructions committed +system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 12527987 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14980229 # number of instructions that are conditional controls -system.cpu0.num_int_insts 119427816 # number of integer instructions +system.cpu0.num_func_calls 12527292 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls +system.cpu0.num_int_insts 119417138 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 220379706 # number of times the integer registers were read -system.cpu0.num_int_register_writes 83050844 # number of times the integer registers were written +system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read +system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 488414813 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 49991768 # number of times the CC registers were written -system.cpu0.num_mem_refs 43590115 # number of memory refs -system.cpu0.num_load_insts 24600281 # Number of load instructions -system.cpu0.num_store_insts 18989834 # Number of store instructions -system.cpu0.num_idle_cycles 5477713409.888090 # Number of idle cycles -system.cpu0.num_busy_cycles 256145102.111911 # Number of busy cycles +system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written +system.cpu0.num_mem_refs 43585643 # number of memory refs +system.cpu0.num_load_insts 24597805 # Number of load instructions +system.cpu0.num_store_insts 18987838 # Number of store instructions +system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles +system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles -system.cpu0.Branches 28216928 # Number of branches fetched +system.cpu0.Branches 28215087 # Number of branches fetched system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 94734127 68.43% 68.43% # Class of executed instruction -system.cpu0.op_class::IntMult 104105 0.08% 68.51% # Class of executed instruction +system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction +system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction @@ -1233,24 +1241,24 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::MemRead 24600281 17.77% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 18989834 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 138438000 # Class of executed instruction +system.cpu0.op_class::total 138425707 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2074 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1061133 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483144 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 114013070 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1061645 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 107.392838 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12807152500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483144 # Average occupied blocks per requestor +system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1060721 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1258,44 +1266,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 231211102 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 231211102 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 114013070 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 114013070 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 114013070 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 114013070 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 114013070 # number of overall hits -system.cpu0.icache.overall_hits::total 114013070 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1061654 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1061654 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1061654 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1061654 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1061654 # number of overall misses -system.cpu0.icache.overall_misses::total 1061654 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000777256 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9000777256 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9000777256 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9000777256 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9000777256 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9000777256 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 115074724 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115074724 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 115074724 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115074724 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 115074724 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115074724 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.070309 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.070309 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8478.070309 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8478.070309 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 231192178 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 231192178 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 114004226 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 114004226 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 114004226 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 114004226 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 114004226 # number of overall hits +system.cpu0.icache.overall_hits::total 114004226 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1061242 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1061242 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1061242 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1061242 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1061242 # number of overall misses +system.cpu0.icache.overall_misses::total 1061242 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8993016265 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8993016265 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8993016265 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8993016265 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8993016265 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8993016265 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065468 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115065468 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 115065468 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115065468 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 115065468 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115065468 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009223 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009223 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009223 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009223 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009223 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009223 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8474.048582 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8474.048582 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8474.048582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8474.048582 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1304,360 +1312,360 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061654 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1061654 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061654 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1061654 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061654 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1061654 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407609744 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407609744 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407609744 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7407609744 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407609744 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7407609744 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719278000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719278000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719278000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 719278000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.423665 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061242 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1061242 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061242 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1061242 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061242 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1061242 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7400481735 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7400481735 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7400481735 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7400481735 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7400481735 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7400481735 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009223 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009223 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6973.415804 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923568 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 227909 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9246862 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 529 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9920146 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228501 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9247232 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 457 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 49 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 448219 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778472 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 42 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 443914 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 777982 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 358131 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16113.840521 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1936015 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 374364 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.171477 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6748.405331 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.298352 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.117074 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 799.968206 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1087.232896 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7475.818663 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.411890 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000140 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048826 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.066359 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.456288 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983511 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7939 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8291 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 355628 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16102.172005 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1937789 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 371860 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.211071 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2843494453500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6709.486955 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.515536 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.136878 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 805.451650 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1129.365506 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7457.215481 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.409515 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.049161 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.068931 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455152 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982799 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8004 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8222 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1966 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4890 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 915 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1974 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4878 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1002 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2895 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4675 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.484558 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.506042 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 38026831 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 38026831 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 6990 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3189 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045942 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 372788 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428909 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 483936 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 483936 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10087 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 10087 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2033 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2033 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212805 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 212805 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 6990 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3189 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1045942 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 585593 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1641714 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 6990 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3189 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1045942 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 585593 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1641714 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 263 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 219 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15712 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 83577 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 99771 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29878 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 29878 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19321 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19321 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44921 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44921 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 263 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 219 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 15712 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 128498 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 144692 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 263 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 219 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 15712 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 128498 # number of overall misses -system.cpu0.l2cache.overall_misses::total 144692 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6061000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4899500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598206723 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2260687668 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 2869854891 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 524614292 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 524614292 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377658880 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377658880 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1333497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1333497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1506710587 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1506710587 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6061000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4899500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598206723 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 3767398255 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 4376565478 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6061000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4899500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598206723 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 3767398255 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 4376565478 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7253 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3408 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061654 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456365 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1528680 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 483936 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 483936 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39965 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 39965 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21354 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21354 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257726 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 257726 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7253 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3408 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1061654 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 714091 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1786406 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7253 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3408 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1061654 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 714091 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1786406 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064261 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014800 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183136 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.065266 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.747604 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.747604 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.904795 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.904795 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4665 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 528 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.488525 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.501831 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 38047907 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 38047907 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7536 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3405 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045714 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 373715 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1430370 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 484430 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 484430 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10145 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 10145 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2013 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2013 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213040 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 213040 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7536 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3405 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1045714 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 586755 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1643410 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7536 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3405 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1045714 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 586755 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1643410 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 196 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15528 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 83217 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 99215 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29791 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 29791 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19296 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19296 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44826 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44826 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 196 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 15528 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 128043 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 144041 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 196 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 15528 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 128043 # number of overall misses +system.cpu0.l2cache.overall_misses::total 144041 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6536750 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 592785719 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2259626174 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 2863295143 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522985276 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 522985276 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377523884 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377523884 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1293996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1293996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513538321 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1513538321 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6536750 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 592785719 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 3773164495 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 4376833464 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6536750 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 592785719 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 3773164495 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 4376833464 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7810 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3601 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061242 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456932 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1529585 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 484430 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 484430 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39936 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 39936 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21309 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21309 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257866 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 257866 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7810 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3601 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1061242 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 714798 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1787451 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7810 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3601 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1061242 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 714798 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1787451 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054429 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014632 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182121 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.064864 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745969 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745969 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905533 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905533 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174298 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174298 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064261 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014800 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179946 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.080996 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064261 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014800 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179946 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.080996 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22372.146119 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38073.238480 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27049.160271 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28764.419430 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17558.547828 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17558.547828 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19546.549350 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.549350 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190499.571429 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190499.571429 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33541.341177 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33541.341177 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 30247.459970 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 30247.459970 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 5815 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173834 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173834 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054429 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014632 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179132 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.080585 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054429 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014632 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179132 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.080585 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22176.020408 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38175.278143 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27153.420263 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28859.498493 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17555.143365 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17555.143365 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19564.877902 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19564.877902 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 161749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 161749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33764.741913 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33764.741913 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 30386.025257 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 30386.025257 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 74 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 76.513158 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 74.675676 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 205462 # number of writebacks -system.cpu0.l2cache.writebacks::total 205462 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2206 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2737 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 4943 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1219 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1219 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2206 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3956 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6162 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2206 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3956 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6162 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 263 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 219 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13506 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80840 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 94828 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 448214 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29878 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29878 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19321 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19321 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43702 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43702 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 263 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 219 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13506 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124542 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 138530 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 263 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 219 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13506 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124542 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 586744 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3366500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457538021 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1656533968 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2121657489 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17785493022 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 490939499 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 490939499 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261550596 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261550596 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1060497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1060497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1074359119 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1074359119 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3366500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457538021 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2730893087 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 3196016608 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3366500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457538021 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2730893087 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 20981509630 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647388500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328873750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5976262250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987021005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987021005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647388500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315894755 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9963283255 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177139 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062033 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 204753 # number of writebacks +system.cpu0.l2cache.writebacks::total 204753 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2208 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2732 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 4940 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1247 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1247 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2208 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3979 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6187 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2208 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3979 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6187 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 274 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 196 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13320 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80485 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 94275 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 443910 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29791 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29791 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19296 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19296 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43579 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43579 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 274 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 196 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13320 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124064 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 137854 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 274 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 196 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13320 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124064 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 581764 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2974500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 455365525 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1657319721 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2120277496 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17833673651 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489027550 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489027550 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261183602 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261183602 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1027996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1027996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080146893 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080146893 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2974500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 455365525 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2737466614 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3200424389 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2974500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 455365525 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2737466614 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21034098040 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328493002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975701502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987031009 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987031009 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315524011 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962732511 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176142 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.061634 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.747604 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.747604 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.904795 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.904795 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745969 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745969 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905533 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905533 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169568 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169568 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077547 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.168999 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.168999 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077123 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.328449 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20491.513706 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22373.744980 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39680.806539 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16431.471283 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16431.471283 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13537.114849 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13537.114849 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 151499.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 151499.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24583.751750 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24583.751750 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23070.934873 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35759.223154 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1667,106 +1675,106 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 658799 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.164758 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41683742 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 659311 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 63.223186 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1016179000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.164758 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947587 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 659666 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 85573160 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 85573160 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23155425 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23155425 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17431620 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17431620 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323179 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 323179 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358328 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 358328 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353864 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 353864 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40587045 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40587045 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40910224 # number of overall hits -system.cpu0.dcache.overall_hits::total 40910224 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 360428 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 360428 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297691 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297691 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106192 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 106192 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21416 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21416 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 658119 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 658119 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 764311 # number of overall misses -system.cpu0.dcache.overall_misses::total 764311 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4473033768 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4473033768 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4445222415 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4445222415 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335592501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 335592501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473344116 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 473344116 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1450500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1450500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8918256183 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8918256183 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8918256183 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8918256183 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23515853 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23515853 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17729311 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17729311 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429371 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 429371 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379744 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 379744 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375234 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 375234 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41245164 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41245164 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 41674535 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 41674535 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015327 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015327 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016791 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016791 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247320 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247320 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056396 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056396 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015956 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015956 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018340 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018340 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12410.339286 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12410.339286 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14932.337273 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14932.337273 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15670.176550 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15670.176550 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22149.935236 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22149.935236 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits +system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses +system.cpu0.dcache.overall_misses::total 765091 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13551.130089 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13551.130089 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11668.360370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11668.360370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1775,82 +1783,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 483937 # number of writebacks -system.cpu0.dcache.writebacks::total 483937 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7364 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7364 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 7364 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 7364 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 7364 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 7364 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353064 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 353064 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297691 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297691 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96960 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 96960 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21361 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21361 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 650755 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 650755 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 747715 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 747715 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3674066732 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3674066732 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3839615585 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3839615585 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1190903244 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1190903244 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89864249 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89864249 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429815884 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429815884 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1372500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1372500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7513682317 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7513682317 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8704585561 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8704585561 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564939750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564939750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183945995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183945995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748885745 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748885745 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015014 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015014 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016791 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016791 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225819 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225819 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056927 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056927 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015778 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015778 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017942 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017942 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks +system.cpu0.dcache.writebacks::total 484431 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1858,57 +1866,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1734717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1628862 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26256 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26256 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 483936 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 598763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 81012 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43653 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 101651 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 279403 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269117 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141354 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2250253 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9809 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 20976 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4422392 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981948 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80932636 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13632 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29012 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 148957228 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 991588 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3219253 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.272771 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.445384 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 985271 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2341135 72.72% 72.72% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 878118 27.28% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3219253 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1700320883 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115643997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1603955756 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1150860061 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13723500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1933,25 +1941,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4827395 # DTB read hits -system.cpu1.dtb.read_misses 2744 # DTB read misses -system.cpu1.dtb.write_hits 4131070 # DTB write hits -system.cpu1.dtb.write_misses 524 # DTB write misses +system.cpu1.dtb.read_hits 4826536 # DTB read hits +system.cpu1.dtb.read_misses 2746 # DTB read misses +system.cpu1.dtb.write_hits 4130096 # DTB write hits +system.cpu1.dtb.write_misses 525 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4830139 # DTB read accesses -system.cpu1.dtb.write_accesses 4131594 # DTB write accesses +system.cpu1.dtb.read_accesses 4829282 # DTB read accesses +system.cpu1.dtb.write_accesses 4130621 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 8958465 # DTB hits -system.cpu1.dtb.misses 3268 # DTB misses -system.cpu1.dtb.accesses 8961733 # DTB accesses +system.cpu1.dtb.hits 8956632 # DTB hits +system.cpu1.dtb.misses 3271 # DTB misses +system.cpu1.dtb.accesses 8959903 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1973,7 +1981,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20889672 # ITB inst hits +system.cpu1.itb.inst_hits 20887785 # ITB inst hits system.cpu1.itb.inst_misses 1747 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1990,38 +1998,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20891419 # ITB inst accesses -system.cpu1.itb.hits 20889672 # DTB hits +system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses +system.cpu1.itb.hits 20887785 # DTB hits system.cpu1.itb.misses 1747 # DTB misses -system.cpu1.itb.accesses 20891419 # DTB accesses -system.cpu1.numCycles 5732950771 # number of cpu cycles simulated +system.cpu1.itb.accesses 20889532 # DTB accesses +system.cpu1.numCycles 5732937622 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20508829 # Number of instructions committed -system.cpu1.committedOps 24874782 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22190598 # Number of integer alu accesses +system.cpu1.committedInsts 20506953 # Number of instructions committed +system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1209607 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2572400 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22190598 # number of integer instructions +system.cpu1.num_func_calls 1209546 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22187475 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 39855869 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15449003 # number of times the integer registers were written +system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 90462747 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 8862782 # number of times the CC registers were written -system.cpu1.num_mem_refs 9247846 # number of memory refs -system.cpu1.num_load_insts 4946569 # Number of load instructions -system.cpu1.num_store_insts 4301277 # Number of store instructions -system.cpu1.num_idle_cycles 5671538888.273010 # Number of idle cycles -system.cpu1.num_busy_cycles 61411882.726990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010712 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989288 # Percentage of idle cycles -system.cpu1.Branches 3892747 # Number of branches fetched +system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written +system.cpu1.num_mem_refs 9246104 # number of memory refs +system.cpu1.num_load_insts 4945808 # Number of load instructions +system.cpu1.num_store_insts 4300296 # Number of store instructions +system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles +system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles +system.cpu1.Branches 3892449 # Number of branches fetched system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 16017837 63.30% 63.30% # Class of executed instruction -system.cpu1.op_class::IntMult 33571 0.13% 63.44% # Class of executed instruction +system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction +system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction @@ -2045,69 +2053,69 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4039 0.02% 63.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::MemRead 4946569 19.55% 83.00% # Class of executed instruction -system.cpu1.op_class::MemWrite 4301277 17.00% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction +system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 25303360 # Class of executed instruction +system.cpu1.op_class::total 25300005 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2751 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 565233 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.685358 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20323921 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 565745 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.924173 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 115078716000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.685358 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973995 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973995 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 565422 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 42345080 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 42345080 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20323921 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20323921 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20323921 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20323921 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20323921 # number of overall hits -system.cpu1.icache.overall_hits::total 20323921 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 565746 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 565746 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 565746 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 565746 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 565746 # number of overall misses -system.cpu1.icache.overall_misses::total 565746 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4684636281 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4684636281 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4684636281 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4684636281 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4684636281 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4684636281 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20889667 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20889667 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20889667 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20889667 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20889667 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20889667 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027083 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027083 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.027083 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027083 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.027083 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8280.458511 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8280.458511 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8280.458511 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8280.458511 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20321845 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20321845 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20321845 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20321845 # number of overall hits +system.cpu1.icache.overall_hits::total 20321845 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 565935 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 565935 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 565935 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 565935 # number of overall misses +system.cpu1.icache.overall_misses::total 565935 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4686937020 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4686937020 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4686937020 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20887780 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20887780 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20887780 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20887780 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027094 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2116,356 +2124,356 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565746 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 565746 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 565746 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 565746 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 565746 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 565746 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835844219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835844219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835844219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3835844219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835844219 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3835844219 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14025750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14025750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14025750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 14025750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027083 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027083 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027083 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6780.152611 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565935 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 565935 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 565935 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 565935 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 565935 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 565935 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3837864980 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3837864980 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3837864980 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3837864980 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3837864980 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3837864980 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027094 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027094 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027094 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6781.458966 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4613211 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23452 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471751 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 253 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4614389 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23334 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471466 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 174 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 21 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 117734 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522133 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 12 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119403 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 521875 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85099 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15602.150946 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 830949 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100297 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.284884 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2855978416500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4730.109881 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.755019 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.314200 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 871.040386 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1529.848587 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8465.082873 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.288703 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000351 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000019 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053164 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.093375 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.516668 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952280 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9308 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5882 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1130 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8114 # Occupied blocks per task id +system.cpu1.l2cache.tags.replacements 85170 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15608.903517 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 832047 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 100420 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.285670 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4763.037570 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.132590 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.368696 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 855.518210 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1503.059843 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8483.786608 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.290713 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000023 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052217 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091739 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517809 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.952692 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9266 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5973 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 72 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1188 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8006 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1134 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4474 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.568115 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359009 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 16690228 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 16690228 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3013 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1699 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560147 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 123235 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 688094 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 134926 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 134926 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1530 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1530 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 889 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 889 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39290 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 39290 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3013 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1699 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 560147 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 162525 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 727384 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3013 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1699 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 560147 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 162525 # number of overall hits -system.cpu1.l2cache.overall_hits::total 727384 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 347 # number of ReadReq misses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4453 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.565552 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364563 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 16694338 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 16694338 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3134 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1760 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560288 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 123283 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 688465 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 134894 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 134894 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1542 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1542 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 898 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 898 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39293 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 39293 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3134 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1760 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 560288 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 162576 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 727758 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3134 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1760 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 560288 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 162576 # number of overall hits +system.cpu1.l2cache.overall_hits::total 727758 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 333 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5599 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 70297 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 76525 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29432 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29432 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22334 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22334 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33500 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33500 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 347 # number of demand (read+write) misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5647 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 70211 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 76473 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29395 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29395 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22356 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22356 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33464 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33464 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 333 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 5599 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 103797 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 110025 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 347 # number of overall misses +system.cpu1.l2cache.demand_misses::cpu1.inst 5647 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 103675 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 109937 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 333 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 5599 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 103797 # number of overall misses -system.cpu1.l2cache.overall_misses::total 110025 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7263500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5687750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191326469 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1549353898 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1753631617 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537113129 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 537113129 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436542574 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436542574 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1696500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1696500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1074535378 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1074535378 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7263500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5687750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191326469 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2623889276 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2828166995 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7263500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5687750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191326469 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2623889276 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2828166995 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3360 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565746 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193532 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 764619 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 134926 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 134926 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30962 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30962 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23223 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23223 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72790 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 72790 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3360 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 565746 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 266322 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 837409 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3360 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 565746 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 266322 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 837409 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.142352 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009897 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363232 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.100083 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950585 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950585 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961719 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961719 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.overall_misses::cpu1.inst 5647 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 103675 # number of overall misses +system.cpu1.l2cache.overall_misses::total 109937 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6884250 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5668750 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192294729 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1548076900 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1752924629 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536345651 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 536345651 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436560063 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436560063 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1532500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1532500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1065249640 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1065249640 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6884250 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5668750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192294729 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2613326540 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2818174269 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6884250 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5668750 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192294729 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2613326540 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2818174269 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3467 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2042 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565935 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193494 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 764938 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 134894 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 134894 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30937 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30937 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23254 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23254 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72757 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 72757 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3467 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2042 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 565935 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 266251 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 837695 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3467 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2042 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 565935 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 266251 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 837695 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138100 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009978 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.362859 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.099973 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950157 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950157 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961383 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961383 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.460228 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.460228 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.142352 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009897 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389742 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.131387 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.142352 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009897 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389742 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.131387 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.326241 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34171.542954 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22040.114059 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22915.800287 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18249.290874 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18249.290874 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19546.098952 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.098952 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 565500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 565500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32075.682925 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32075.682925 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 25704.767053 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 25704.767053 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 1025 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.459942 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.459942 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138100 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009978 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389388 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.131238 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138100 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009978 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389388 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.131238 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20101.950355 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34052.546308 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22048.922534 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22922.137604 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18246.152441 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18246.152441 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19527.646404 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19527.646404 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 255416.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 255416.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31832.704996 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31832.704996 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 25634.447629 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 25634.447629 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 41 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.285714 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.463415 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 35099 # number of writebacks -system.cpu1.l2cache.writebacks::total 35099 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 685 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 96 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 214 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 214 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 685 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 310 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 995 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 685 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 310 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 995 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 347 # number of ReadReq MSHR misses +system.cpu1.l2cache.writebacks::writebacks 35043 # number of writebacks +system.cpu1.l2cache.writebacks::total 35043 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 682 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 211 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 211 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 682 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 997 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 682 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 997 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 333 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4914 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70201 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 75744 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 117733 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29432 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29432 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22334 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22334 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33286 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33286 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 347 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4965 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70107 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 75687 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 119401 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29395 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29395 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22356 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22356 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33253 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33253 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 333 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 282 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4914 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103487 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 109030 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 347 # number of overall MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4965 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103360 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 108940 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 333 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4914 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103487 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 226763 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3713250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143751774 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1055636432 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1207934956 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3298666709 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 431077198 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 431077198 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306544179 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306544179 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1430500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1430500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820609092 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820609092 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3713250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143751774 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1876245524 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2028544048 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3713250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143751774 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1876245524 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 5327210757 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12612250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916010500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928622750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796474001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796474001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12612250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712484501 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725096751 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362736 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099061 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4965 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103360 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 228341 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3694250 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143766018 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1054723430 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206735448 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3265998125 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430847649 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430847649 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306945673 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306945673 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1280500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1280500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 812696840 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 812696840 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3694250 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143766018 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1867420270 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2019432288 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3694250 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143766018 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1867420270 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5285430413 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 915969500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928445000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796605001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796605001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712574501 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725050001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362321 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.098945 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950585 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950585 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961719 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961719 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950157 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950157 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961383 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961383 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457288 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457288 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130199 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457042 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457042 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130047 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.270791 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15037.341804 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15947.599229 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28018.199732 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14646.547907 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14646.547907 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13725.449046 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13725.449046 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 476833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 476833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24653.280418 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24653.280418 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18605.375108 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23492.416122 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272583 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15044.481008 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15943.761121 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27353.189044 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14657.174656 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14657.174656 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13729.901279 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13729.901279 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213416.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213416.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24439.805130 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2475,105 +2483,105 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 218932 # number of replacements -system.cpu1.dcache.tags.tagsinuse 479.958616 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8645395 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 219287 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.425023 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104115576500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.958616 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937419 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.937419 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18161929 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18161929 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4463105 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4463105 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3919326 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3919326 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64192 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 64192 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87200 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87200 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79632 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79632 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8382431 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8382431 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8446623 # number of overall hits -system.cpu1.dcache.overall_hits::total 8446623 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 155171 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 155171 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 103752 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 103752 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34196 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34196 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17931 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17931 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23276 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23276 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 258923 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 258923 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 293119 # number of overall misses -system.cpu1.dcache.overall_misses::total 293119 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220270266 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2220270266 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2272762314 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2272762314 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325809000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325809000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538454705 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 538454705 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1810500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1810500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4493032580 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4493032580 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4493032580 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4493032580 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4618276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4618276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4023078 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4023078 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98388 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 98388 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102908 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102908 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8641354 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8641354 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8739742 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8739742 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033599 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033599 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025789 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025789 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347563 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347563 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170559 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170559 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226183 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226183 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029963 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029963 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033539 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033539 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18170.152250 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 218971 # number of replacements +system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits +system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses +system.cpu1.dcache.overall_misses::total 293049 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17352.775072 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2582,82 +2590,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 134926 # number of writebacks -system.cpu1.dcache.writebacks::total 134926 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12328 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12328 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 299 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 299 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154872 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 154872 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103752 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103752 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33057 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 33057 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5603 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5603 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23226 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23226 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 258624 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 258624 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 291681 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 291681 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901749734 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901749734 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2059007686 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2059007686 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496678249 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496678249 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84335500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84335500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490783295 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490783295 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1734500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1734500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3960757420 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3960757420 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4457435669 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4457435669 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961034499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961034499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794416998 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794416998 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025789 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025789 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335986 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335986 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053295 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053295 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225697 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225697 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029929 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029929 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033374 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033374 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks +system.cpu1.dcache.writebacks::total 134894 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2665,110 +2673,110 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1206103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 816776 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 134926 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 169865 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 86284 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42512 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89712 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 91056 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 78188 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131848 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880488 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9281 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2026923 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36208456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28775795 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13440 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 65005615 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 818131 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1761210 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.414931 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492710 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 817024 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1030430 58.51% 58.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 730780 41.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1761210 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 658102724 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89600499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 848922781 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 438669538 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5921500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36443 # number of replacements -system.iocache.tags.tagsinuse 14.446814 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277160524000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446814 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902926 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902926 # Average percentage of cache occupancy +system.iocache.tags.replacements 36427 # number of replacements +system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use +system.iocache.tags.total_refs 16 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328549 # Number of tag accesses -system.iocache.tags.data_accesses 328549 # Number of data accesses +system.iocache.tags.tag_accesses 328485 # Number of tag accesses +system.iocache.tags.data_accesses 328485 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses system.iocache.ReadReq_misses::total 253 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 32 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 32 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses system.iocache.demand_misses::total 253 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 253 # number of overall misses system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36256 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36256 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36250 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36250 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000883 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000883 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000717 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000717 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124954.059289 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124954.059289 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124954.059289 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124954.059289 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2783,28 +2791,28 @@ system.iocache.demand_mshr_misses::realview.ide 253 system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2247085536 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2247085536 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18456377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18456377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2245537783 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2245537783 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18456377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18456377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18456377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18456377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72950.106719 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72950.106719 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index f074dc56c..0ae66cc7f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 7ca64b9c1..ce3f5bea6 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:58:15 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x56b5b00 0x56b5b00 + 0: system.cpu.isa: ISA system set to: 0x44d4680 0x44d4680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index f83b43588..c670f647a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.902619 # Nu sim_ticks 2902619131000 # Number of ticks simulated final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744858 # Simulator instruction rate (inst/s) -host_op_rate 898074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19216925045 # Simulator tick rate (ticks/s) -host_mem_usage 553548 # Number of bytes of host memory used -host_seconds 151.05 # Real time elapsed on the host -sim_insts 112506996 # Number of instructions simulated -sim_ops 135649573 # Number of ops (including micro ops) simulated +host_inst_rate 756630 # Simulator instruction rate (inst/s) +host_op_rate 912268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19520630002 # Simulator tick rate (ticks/s) +host_mem_usage 553652 # Number of bytes of host memory used +host_seconds 148.70 # Real time elapsed on the host +sim_insts 112506995 # Number of instructions simulated +sim_ops 135649572 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory @@ -100,7 +100,7 @@ system.physmem.perBankWrBursts::14 7284 # Pe system.physmem.perBankWrBursts::15 7101 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2902618699500 # Total gap between requests +system.physmem.totGap 2902618754500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) @@ -211,20 +211,20 @@ system.physmem.wrQLenPdf::60 13 # Wh system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes @@ -268,12 +268,12 @@ system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads -system.physmem.totQLat 1491787750 # Total ticks spent queuing -system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1492072500 # Total ticks spent queuing +system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -284,49 +284,49 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing -system.physmem.readRowHits 138438 # Number of row buffer hits during reads +system.physmem.readRowHits 138435 # Number of row buffer hits during reads system.physmem.writeRowHits 90000 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes -system.physmem.avgGap 9972509.98 # Average gap between requests +system.physmem.avgGap 9972510.17 # Average gap between requests system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states system.physmem.memoryStateTime::REF 96924620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states +system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.480430 # Core power per rank (mW) -system.physmem.averagePower::1 669.392372 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 70650 # Transaction distribution -system.membus.trans_dist::ReadResp 70650 # Transaction distribution +system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.480439 # Core power per rank (mW) +system.physmem.averagePower::1 669.392466 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 70649 # Transaction distribution +system.membus.trans_dist::ReadResp 70649 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution system.membus.trans_dist::Writeback 82180 # Transaction distribution @@ -338,21 +338,21 @@ system.membus.trans_dist::UpgradeResp 4505 # Tr system.membus.trans_dist::ReadExReq 128451 # Transaction distribution system.membus.trans_dist::ReadExResp 128451 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 219 # Total snoops (count) system.membus.snoop_fanout::samples 281834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram @@ -367,13 +367,13 @@ system.membus.snoop_fanout::max_value 1 # Re system.membus.snoop_fanout::total 281834 # Request fanout histogram system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) @@ -604,20 +604,20 @@ system.cpu.itb.accesses 115610659 # DT system.cpu.numCycles 5805238262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112506996 # Number of instructions committed -system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses +system.cpu.committedInsts 112506995 # Number of instructions committed +system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses system.cpu.num_func_calls 9898964 # number of times a function call or return occured system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls -system.cpu.num_int_insts 119948924 # number of integer instructions +system.cpu.num_int_insts 119948923 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read -system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written +system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read +system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written +system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written system.cpu.num_mem_refs 45428231 # number of memory refs system.cpu.num_load_insts 24855392 # Number of load instructions system.cpu.num_store_insts 20572839 # Number of store instructions @@ -627,7 +627,7 @@ system.cpu.not_idle_fraction 0.072139 # Pe system.cpu.idle_fraction 0.927861 # Percentage of idle cycles system.cpu.Branches 25929456 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction @@ -660,7 +660,7 @@ system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Cl system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138771626 # Class of executed instruction +system.cpu.op_class::total 138771625 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed system.cpu.icache.tags.replacements 1699818 # number of replacements @@ -736,10 +736,10 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses @@ -837,18 +837,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) @@ -902,18 +902,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -954,26 +954,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses @@ -1004,18 +1004,18 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1072,16 +1072,16 @@ system.cpu.dcache.overall_misses::cpu.data 820348 # system.cpu.dcache.overall_misses::total 820348 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) @@ -1112,16 +1112,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -1156,24 +1156,24 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 817570 system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses @@ -1190,18 +1190,18 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1209,8 +1209,8 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution @@ -1220,16 +1220,16 @@ system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 52963 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram @@ -1246,13 +1246,13 @@ system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index c44b0a7f7..72e487329 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram +memories=system.realview.nvmem system.physmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr index cf30e237d..6291714a8 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -38,7 +38,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index 0605672c9..4a0c68df7 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 16:00:04 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:27:15 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x50c1b00 0x50c1b00 - 0: system.cpu1.isa: ISA system set to: 0x50c1b00 0x50c1b00 + 0: system.cpu0.isa: ISA system set to: 0x4171680 0x4171680 + 0: system.cpu1.isa: ISA system set to: 0x4171680 0x4171680 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 863689702..b1c7d16c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,93 +1,93 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783853 # Number of seconds simulated -sim_ticks 2783853461500 # Number of ticks simulated -final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783854177000 # Number of ticks simulated +final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1402368 # Simulator instruction rate (inst/s) -host_op_rate 1707157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27344724772 # Simulator tick rate (ticks/s) -host_mem_usage 555568 # Number of bytes of host memory used -host_seconds 101.81 # Real time elapsed on the host -sim_insts 142769281 # Number of instructions simulated -sim_ops 173798567 # Number of ops (including micro ops) simulated +host_inst_rate 1241693 # Simulator instruction rate (inst/s) +host_op_rate 1511561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24211403286 # Simulator tick rate (ticks/s) +host_mem_usage 555676 # Number of bytes of host memory used +host_seconds 114.98 # Real time elapsed on the host +sim_insts 142771179 # Number of instructions simulated +sim_ops 173800939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 727076 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4668128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 726948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4668448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 483904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5677444 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 484032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5677124 # Number of bytes read from this memory system.physmem.bytes_read::total 11558024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 727076 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 483904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 726948 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 484032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521088 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6521152 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8856948 # Number of bytes written to this memory +system.physmem.bytes_written::total 8857012 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73463 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88706 # Number of read requests responded to by this memory system.physmem.num_reads::total 189567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101892 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 101893 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142497 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142498 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 261130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1676973 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2039419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261176 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 173871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2039304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 261130 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 173871 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342468 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342491 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1683150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 261130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1683265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2039422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333350 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74230 # Transaction distribution -system.membus.trans_dist::ReadResp 74230 # Transaction distribution +system.physmem.bw_total::cpu1.inst 173871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2039307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333371 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74229 # Transaction distribution +system.membus.trans_dist::ReadResp 74229 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101892 # Transaction distribution +system.membus.trans_dist::Writeback 101893 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -96,48 +96,48 @@ system.membus.trans_dist::UpgradeResp 4509 # Tr system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258695 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20592391 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322845 # Request fanout histogram +system.membus.snoop_fanout::samples 322846 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322845 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322845 # Request fanout histogram +system.membus.snoop_fanout::total 322846 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.315266 # Cycle average of tags in use -system.l2c.tags.total_refs 2731077 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65155.315046 # Cycle average of tags in use +system.l2c.tags.total_refs 2731069 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.579269 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 15.579223 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.451407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48893.450806 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.249806 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.238472 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.246169 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.238625 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4020.297746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.174711 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4020.301933 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.174390 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -157,143 +157,143 @@ system.l2c.tags.age_task_id_blocks_1024::3 10700 # system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26229754 # Number of tag accesses -system.l2c.tags.data_accesses 26229754 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2286 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4988 # number of ReadReq hits +system.l2c.tags.tag_accesses 26229699 # Number of tag accesses +system.l2c.tags.data_accesses 26229699 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4981 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 258725 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201051 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682262 # number of Writeback hits -system.l2c.Writeback_hits::total 682262 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 847891 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 258771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201046 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682259 # number of Writeback hits +system.l2c.Writeback_hits::total 682259 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72309 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78732 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151041 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319080 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4988 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::cpu0.data 72299 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151042 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4718 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319012 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4981 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847748 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337457 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352092 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4715 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2286 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833389 # number of overall hits -system.l2c.overall_hits::cpu0.data 319080 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4988 # number of overall hits +system.l2c.demand_hits::cpu1.inst 847891 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337514 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352088 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4718 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833258 # number of overall hits +system.l2c.overall_hits::cpu0.data 319012 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4981 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847748 # number of overall hits -system.l2c.overall_hits::cpu1.data 337457 # number of overall hits -system.l2c.overall_hits::total 2352092 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847891 # number of overall hits +system.l2c.overall_hits::cpu1.data 337514 # number of overall hits +system.l2c.overall_hits::total 2352088 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10797 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9751 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10795 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9750 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7561 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5778 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 7563 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5779 # number of ReadReq misses system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1248 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1480 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63966 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83898 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63973 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83891 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10797 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73717 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10795 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73723 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89676 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89670 # number of demand (read+write) misses system.l2c.demand_misses::total 181759 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10797 # number of overall misses -system.l2c.overall_misses::cpu0.data 73717 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses +system.l2c.overall_misses::cpu0.data 73723 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7561 # number of overall misses -system.l2c.overall_misses::cpu1.data 89676 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses +system.l2c.overall_misses::cpu1.data 89670 # number of overall misses system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4720 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2287 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844186 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256522 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4990 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4723 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2286 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844053 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256463 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855309 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264503 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2234946 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682262 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682262 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1260 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1496 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855454 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264550 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2234941 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682259 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682259 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136275 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162630 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4720 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2287 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844186 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392797 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4990 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 136272 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162634 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4723 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844053 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392735 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855309 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427133 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533851 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2287 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844186 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392797 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4990 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855454 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427184 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533847 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4723 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844053 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392735 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4983 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855309 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427133 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533851 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855454 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427184 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533847 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.012790 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038012 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038017 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.021845 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989305 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469389 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515883 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469451 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515827 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012790 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187672 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187717 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209949 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209910 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012790 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187672 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187717 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008840 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209949 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209910 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -303,8 +303,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101892 # number of writebacks -system.l2c.writebacks::total 101892 # number of writebacks +system.l2c.writebacks::writebacks 101893 # number of writebacks +system.l2c.writebacks::total 101893 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -343,28 +343,28 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2291806 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291806 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2291797 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291797 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682262 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682259 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417070 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444902 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20772 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41576 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924320 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323083 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41544 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205252639 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924301 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322187 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205252475 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36632 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272100 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3272090 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -373,12 +373,12 @@ system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235636 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3235626 98.89% 98.89% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272100 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272090 # Request fanout histogram system.iobus.trans_dist::ReadReq 30171 # Transaction distribution system.iobus.trans_dist::ReadResp 30171 # Transaction distribution system.iobus.trans_dist::WriteReq 59016 # Transaction distribution @@ -457,25 +457,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997245 # DTB read hits -system.cpu0.dtb.read_misses 4798 # DTB read misses -system.cpu0.dtb.write_hits 11281299 # DTB write hits -system.cpu0.dtb.write_misses 897 # DTB write misses -system.cpu0.dtb.flush_tlb 2812 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 15997157 # DTB read hits +system.cpu0.dtb.read_misses 4809 # DTB read misses +system.cpu0.dtb.write_hits 11281332 # DTB write hits +system.cpu0.dtb.write_misses 894 # DTB write misses +system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3224 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 779 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16002043 # DTB read accesses -system.cpu0.dtb.write_accesses 11282196 # DTB write accesses +system.cpu0.dtb.read_accesses 16001966 # DTB read accesses +system.cpu0.dtb.write_accesses 11282226 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278544 # DTB hits -system.cpu0.dtb.misses 5695 # DTB misses -system.cpu0.dtb.accesses 27284239 # DTB accesses +system.cpu0.dtb.hits 27278489 # DTB hits +system.cpu0.dtb.misses 5703 # DTB misses +system.cpu0.dtb.accesses 27284192 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -497,55 +497,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 74797989 # ITB inst hits +system.cpu0.itb.inst_hits 74798311 # ITB inst hits system.cpu0.itb.inst_misses 2590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2812 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1905 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74800579 # ITB inst accesses -system.cpu0.itb.hits 74797989 # DTB hits +system.cpu0.itb.inst_accesses 74800901 # ITB inst accesses +system.cpu0.itb.hits 74798311 # DTB hits system.cpu0.itb.misses 2590 # DTB misses -system.cpu0.itb.accesses 74800579 # DTB accesses -system.cpu0.numCycles 5536445370 # number of cpu cycles simulated +system.cpu0.itb.accesses 74800901 # DTB accesses +system.cpu0.numCycles 5536444793 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72639024 # Number of instructions committed -system.cpu0.committedOps 87981151 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77491342 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses -system.cpu0.num_func_calls 8694279 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459647 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77491342 # number of integer instructions -system.cpu0.num_fp_insts 5273 # number of float instructions -system.cpu0.num_int_register_reads 144069707 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447285 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read +system.cpu0.committedInsts 72639683 # Number of instructions committed +system.cpu0.committedOps 87981695 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77491900 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses +system.cpu0.num_func_calls 8694354 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459791 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77491900 # number of integer instructions +system.cpu0.num_fp_insts 5289 # number of float instructions +system.cpu0.num_int_register_reads 144070444 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447556 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268877072 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31833969 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909499 # number of memory refs -system.cpu0.num_load_insts 16164843 # Number of load instructions -system.cpu0.num_store_insts 11744656 # Number of store instructions -system.cpu0.num_idle_cycles 5353619097.982533 # Number of idle cycles -system.cpu0.num_busy_cycles 182826272.017466 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles -system.cpu0.Branches 18600717 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2187 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776214 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59687 0.07% 68.90% # Class of executed instruction +system.cpu0.num_cc_register_reads 268879109 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31834194 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909453 # number of memory refs +system.cpu0.num_load_insts 16164742 # Number of load instructions +system.cpu0.num_store_insts 11744711 # Number of store instructions +system.cpu0.num_idle_cycles 5353616970.490369 # Number of idle cycles +system.cpu0.num_busy_cycles 182827822.509631 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles +system.cpu0.Branches 18600859 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776837 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -569,27 +569,27 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164843 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11744656 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164742 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11744711 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752000 # Class of executed instruction +system.cpu0.op_class::total 89752572 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1698994 # number of replacements +system.cpu0.icache.tags.replacements 1699006 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145339246 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.122338 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.541342 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888911 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110432 # Average percentage of cache occupancy +system.cpu0.icache.tags.total_refs 145341254 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121642 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542037 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -597,43 +597,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148738270 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148738270 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73955669 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71383577 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145339246 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73955669 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71383577 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145339246 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73955669 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71383577 # number of overall hits -system.cpu0.icache.overall_hits::total 145339246 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844195 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855317 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844195 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855317 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844195 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855317 # number of overall misses -system.cpu0.icache.overall_misses::total 1699512 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799864 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72238894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74799864 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72238894 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74799864 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72238894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011286 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011840 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 148740302 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148740302 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73956125 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71385129 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145341254 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73956125 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71385129 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145341254 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73956125 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71385129 # number of overall hits +system.cpu0.icache.overall_hits::total 145341254 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844062 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855462 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699524 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844062 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855462 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699524 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844062 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855462 # number of overall misses +system.cpu0.icache.overall_misses::total 1699524 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74800187 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72240591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74800187 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72240591 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74800187 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72240591 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011286 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011840 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011286 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011840 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -644,105 +644,105 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 819402 # number of replacements +system.cpu0.dcache.tags.replacements 819391 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53782968 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.595865 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.832873 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.164301 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929361 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070633 # Average percentage of cache occupancy +system.cpu0.dcache.tags.total_refs 53783615 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819903 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597534 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830642 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219231522 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219231522 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305372 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14822853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128225 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894245 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445267 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185732 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209303 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395035 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234999 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222317 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219234055 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219234055 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305331 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823339 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128670 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10894284 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445424 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185757 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209284 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234994 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222322 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236700 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223422 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236693 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223429 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199617 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268120 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52467737 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385349 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26477423 # number of overall hits -system.cpu0.dcache.overall_hits::total 52862772 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197486 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198842 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396328 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137535 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164126 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301661 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54372 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61696 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116068 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4664 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3965 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26199615 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268763 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468378 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385372 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26478047 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863419 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197455 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198864 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396319 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137533 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164129 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61720 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362968 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697989 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389393 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424664 # number of overall misses -system.cpu0.dcache.overall_misses::total 814057 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502858 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021695 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609393 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270999 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511103 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239663 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334988 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362993 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389333 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424713 # number of overall misses +system.cpu0.dcache.overall_misses::total 814046 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502786 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022203 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031817 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609553 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240102 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511106 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239657 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226288 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236700 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223424 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236693 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223431 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534638 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631088 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774742 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902087 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53676829 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012739 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013237 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.012984 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534603 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631756 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774705 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902760 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677465 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012737 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012467 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014137 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226452 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227661 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227093 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019461 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017522 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226341 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227746 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227086 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012626 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.013129 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014543 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013630 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014541 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015787 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -752,8 +752,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682262 # number of writebacks -system.cpu0.dcache.writebacks::total 682262 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682259 # number of writebacks +system.cpu0.dcache.writebacks::total 682259 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -778,25 +778,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15526476 # DTB read hits -system.cpu1.dtb.read_misses 5406 # DTB read misses -system.cpu1.dtb.write_hits 11842298 # DTB write hits -system.cpu1.dtb.write_misses 791 # DTB write misses -system.cpu1.dtb.flush_tlb 2818 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 15527003 # DTB read hits +system.cpu1.dtb.read_misses 5395 # DTB read misses +system.cpu1.dtb.write_hits 11842462 # DTB write hits +system.cpu1.dtb.write_misses 794 # DTB write misses +system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3194 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 923 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15531882 # DTB read accesses -system.cpu1.dtb.write_accesses 11843089 # DTB write accesses +system.cpu1.dtb.read_accesses 15532398 # DTB read accesses +system.cpu1.dtb.write_accesses 11843256 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368774 # DTB hits -system.cpu1.dtb.misses 6197 # DTB misses -system.cpu1.dtb.accesses 27374971 # DTB accesses +system.cpu1.dtb.hits 27369465 # DTB hits +system.cpu1.dtb.misses 6189 # DTB misses +system.cpu1.dtb.accesses 27375654 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -818,55 +818,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 72236782 # ITB inst hits -system.cpu1.itb.inst_misses 3052 # ITB inst misses +system.cpu1.itb.inst_hits 72238481 # ITB inst hits +system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2818 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2023 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72239834 # ITB inst accesses -system.cpu1.itb.hits 72236782 # DTB hits -system.cpu1.itb.misses 3052 # DTB misses -system.cpu1.itb.accesses 72239834 # DTB accesses -system.cpu1.numCycles 88012648 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72241532 # ITB inst accesses +system.cpu1.itb.hits 72238481 # DTB hits +system.cpu1.itb.misses 3051 # DTB misses +system.cpu1.itb.accesses 72241532 # DTB accesses +system.cpu1.numCycles 88014935 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70130257 # Number of instructions committed -system.cpu1.committedOps 85817416 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75667160 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses -system.cpu1.num_func_calls 8179026 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270368 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75667160 # number of integer instructions -system.cpu1.num_fp_insts 6211 # number of float instructions -system.cpu1.num_int_register_reads 140982352 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52729123 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read +system.cpu1.committedInsts 70131496 # Number of instructions committed +system.cpu1.committedOps 85819244 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75668739 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses +system.cpu1.num_func_calls 8179428 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270456 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75668739 # number of integer instructions +system.cpu1.num_fp_insts 6195 # number of float instructions +system.cpu1.num_int_register_reads 140985899 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52730443 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261962982 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30529174 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028313 # number of memory refs -system.cpu1.num_load_insts 15690218 # Number of load instructions -system.cpu1.num_store_insts 12338095 # Number of store instructions -system.cpu1.num_idle_cycles 85358107.940046 # Number of idle cycles -system.cpu1.num_busy_cycles 2654540.059954 # Number of busy cycles +system.cpu1.num_cc_register_reads 261968424 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30529611 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028993 # number of memory refs +system.cpu1.num_load_insts 15690755 # Number of load instructions +system.cpu1.num_store_insts 12338238 # Number of store instructions +system.cpu1.num_idle_cycles 85360290.427990 # Number of idle cycles +system.cpu1.num_busy_cycles 2654644.572010 # Number of busy cycles system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17795350 # Number of branches fetched -system.cpu1.op_class::No_OpClass 150 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59373450 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction +system.cpu1.Branches 17795920 # Number of branches fetched +system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59374689 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57198 0.07% 67.95% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction @@ -890,24 +890,24 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690218 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12338095 14.11% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15690755 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12338238 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87463263 # Class of executed instruction +system.cpu1.op_class::total 87465184 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |