diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/SConscript | 2 | ||||
| -rw-r--r-- | tests/configs/memtest-filter.py | 87 | ||||
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini | 610 | ||||
| -rwxr-xr-x | tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr | 74 | ||||
| -rwxr-xr-x | tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout | 10 | ||||
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 1747 |
6 files changed, 2529 insertions, 1 deletions
diff --git a/tests/SConscript b/tests/SConscript index 64f0067c7..ec2b4b121 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -344,7 +344,7 @@ configs += ['simple-atomic', 'simple-atomic-mp', 'inorder-timing', 'minor-timing', 'minor-timing-mp', 'o3-timing', 'o3-timing-mp', - 'rubytest', 'memtest', + 'rubytest', 'memtest', 'memtest-filter', 'tgen-simple-mem', 'tgen-dram-ctrl'] if env['PROTOCOL'] != 'None': diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py new file mode 100644 index 000000000..4de009d76 --- /dev/null +++ b/tests/configs/memtest-filter.py @@ -0,0 +1,87 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * +m5.util.addToPath('../configs/common') +from Caches import * + +#MAX CORES IS 8 with the fals sharing method +nb_cores = 8 +cpus = [ MemTest() for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), + funcbus = NoncoherentBus(), + physmem = SimpleMemory(), + membus = CoherentBus(width=16, snoop_filter = SnoopFilter())) +# Dummy voltage domain for all our clock domains +system.voltage_domain = VoltageDomain() +system.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', + voltage_domain = system.voltage_domain) + +system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16, + snoop_filter = SnoopFilter()) +system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.master + +# connect l2c to membus +system.l2c.mem_side = system.membus.slave + +# add L1 caches +for cpu in cpus: + # All cpus are associated with cpu_clk_domain + cpu.clk_domain = system.cpu_clk_domain + cpu.l1c = L1Cache(size = '32kB', assoc = 4) + cpu.l1c.cpu_side = cpu.test + cpu.l1c.mem_side = system.toL2Bus.slave + system.funcbus.slave = cpu.functional + +system.system_port = system.membus.slave + +# connect reference memory to funcbus +system.funcmem.port = system.funcbus.master + +# connect memory to membus +system.physmem.port = system.membus.master + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( full_system = False, system = system ) +root.system.mem_mode = 'timing' +#root.trace.flags="Cache CachePort MemoryAccess" +#root.trace.cycle=1 + diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini new file mode 100644 index 000000000..b9c14dc5f --- /dev/null +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini @@ -0,0 +1,610 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem system.funcmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[0] +test=system.cpu0.l1c.cpu_side + +[system.cpu0.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.test +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu1] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[1] +test=system.cpu1.l1c.cpu_side + +[system.cpu1.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.test +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu2] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[2] +test=system.cpu2.l1c.cpu_side + +[system.cpu2.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu2.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.test +mem_side=system.toL2Bus.slave[2] + +[system.cpu2.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu3] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[3] +test=system.cpu3.l1c.cpu_side + +[system.cpu3.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu3.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.test +mem_side=system.toL2Bus.slave[3] + +[system.cpu3.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu4] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[4] +test=system.cpu4.l1c.cpu_side + +[system.cpu4.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu4.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu4.test +mem_side=system.toL2Bus.slave[4] + +[system.cpu4.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu5] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[5] +test=system.cpu5.l1c.cpu_side + +[system.cpu5.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu5.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu5.test +mem_side=system.toL2Bus.slave[5] + +[system.cpu5.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu6] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[6] +test=system.cpu6.l1c.cpu_side + +[system.cpu6.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu6.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu6.test +mem_side=system.toL2Bus.slave[6] + +[system.cpu6.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu7] +type=MemTest +children=l1c +atomic=false +clk_domain=system.cpu_clk_domain +eventq_index=0 +issue_dmas=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +suppress_func_warnings=false +sys=system +trace_addr=0 +functional=system.funcbus.slave[7] +test=system.cpu7.l1c.cpu_side + +[system.cpu7.l1c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu7.l1c.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu7.test +mem_side=system.toL2Bus.slave[7] + +[system.cpu7.l1c.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.funcbus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.funcmem.port +slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional + +[system.funcmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=false +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.funcbus.master[0] + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=65536 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=65536 + +[system.membus] +type=CoherentBus +children=snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=system.membus.snoop_filter +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.l2c.mem_side system.system_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=3 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +port=system.membus.master[0] + +[system.toL2Bus] +type=CoherentBus +children=snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=system.toL2Bus.snoop_filter +system=system +use_default_range=false +width=16 +master=system.l2c.cpu_side +slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side + +[system.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=3 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr new file mode 100755 index 000000000..70113e2a8 --- /dev/null +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr @@ -0,0 +1,74 @@ +warn: failed to generate dot output from build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/config.dot +system.cpu6: completed 10000 read, 5415 write accesses @145109000 +system.cpu2: completed 10000 read, 5349 write accesses @145417500 +system.cpu1: completed 10000 read, 5329 write accesses @146140000 +system.cpu0: completed 10000 read, 5371 write accesses @146497000 +system.cpu4: completed 10000 read, 5466 write accesses @147507000 +system.cpu3: completed 10000 read, 5586 write accesses @147982000 +system.cpu5: completed 10000 read, 5427 write accesses @148047500 +system.cpu7: completed 10000 read, 5356 write accesses @148467500 +system.cpu6: completed 20000 read, 10673 write accesses @289538000 +system.cpu2: completed 20000 read, 10526 write accesses @290832000 +system.cpu1: completed 20000 read, 10766 write accesses @292890999 +system.cpu5: completed 20000 read, 10736 write accesses @293627000 +system.cpu7: completed 20000 read, 10730 write accesses @293693000 +system.cpu0: completed 20000 read, 10671 write accesses @294206500 +system.cpu4: completed 20000 read, 10944 write accesses @296769500 +system.cpu3: completed 20000 read, 10962 write accesses @297951000 +system.cpu2: completed 30000 read, 15840 write accesses @436954000 +system.cpu1: completed 30000 read, 16134 write accesses @439432500 +system.cpu6: completed 30000 read, 16128 write accesses @439710500 +system.cpu7: completed 30000 read, 16048 write accesses @440819000 +system.cpu5: completed 30000 read, 16126 write accesses @441698000 +system.cpu3: completed 30000 read, 16409 write accesses @444974000 +system.cpu4: completed 30000 read, 16439 write accesses @445869500 +system.cpu0: completed 30000 read, 16254 write accesses @446194000 +system.cpu2: completed 40000 read, 21231 write accesses @582932500 +system.cpu6: completed 40000 read, 21466 write accesses @586141500 +system.cpu1: completed 40000 read, 21414 write accesses @588066500 +system.cpu3: completed 40000 read, 21735 write accesses @588220000 +system.cpu5: completed 40000 read, 21572 write accesses @588767000 +system.cpu7: completed 40000 read, 21513 write accesses @590091000 +system.cpu0: completed 40000 read, 21682 write accesses @592843000 +system.cpu4: completed 40000 read, 21885 write accesses @593488000 +system.cpu2: completed 50000 read, 26639 write accesses @730512000 +system.cpu3: completed 50000 read, 26953 write accesses @733051500 +system.cpu6: completed 50000 read, 26889 write accesses @736295000 +system.cpu1: completed 50000 read, 26860 write accesses @736946500 +system.cpu4: completed 50000 read, 27157 write accesses @739104500 +system.cpu5: completed 50000 read, 27043 write accesses @739175000 +system.cpu7: completed 50000 read, 27030 write accesses @739274500 +system.cpu0: completed 50000 read, 27007 write accesses @740081999 +system.cpu2: completed 60000 read, 31935 write accesses @875520000 +system.cpu3: completed 60000 read, 32327 write accesses @878608000 +system.cpu1: completed 60000 read, 32037 write accesses @880758000 +system.cpu5: completed 60000 read, 32374 write accesses @883996500 +system.cpu4: completed 60000 read, 32578 write accesses @885209000 +system.cpu6: completed 60000 read, 32302 write accesses @886481999 +system.cpu0: completed 60000 read, 32356 write accesses @886645000 +system.cpu7: completed 60000 read, 32534 write accesses @888148500 +system.cpu3: completed 70000 read, 37577 write accesses @1026143000 +system.cpu2: completed 70000 read, 37542 write accesses @1027029999 +system.cpu1: completed 70000 read, 37457 write accesses @1029024000 +system.cpu5: completed 70000 read, 37722 write accesses @1029495500 +system.cpu6: completed 70000 read, 37640 write accesses @1032918500 +system.cpu0: completed 70000 read, 37692 write accesses @1034293500 +system.cpu7: completed 70000 read, 37955 write accesses @1034390500 +system.cpu4: completed 70000 read, 38136 write accesses @1036569000 +system.cpu3: completed 80000 read, 42898 write accesses @1173212500 +system.cpu2: completed 80000 read, 42932 write accesses @1173575000 +system.cpu1: completed 80000 read, 42886 write accesses @1177639500 +system.cpu5: completed 80000 read, 43232 write accesses @1178175000 +system.cpu0: completed 80000 read, 42958 write accesses @1178771500 +system.cpu6: completed 80000 read, 42919 write accesses @1180797000 +system.cpu7: completed 80000 read, 43430 write accesses @1183823000 +system.cpu4: completed 80000 read, 43550 write accesses @1185935999 +system.cpu2: completed 90000 read, 48239 write accesses @1319473000 +system.cpu3: completed 90000 read, 48329 write accesses @1322081500 +system.cpu1: completed 90000 read, 48223 write accesses @1323240500 +system.cpu5: completed 90000 read, 48632 write accesses @1326787000 +system.cpu0: completed 90000 read, 48351 write accesses @1327807500 +system.cpu6: completed 90000 read, 48287 write accesses @1329208000 +system.cpu7: completed 90000 read, 48796 write accesses @1329462500 +system.cpu4: completed 90000 read, 48969 write accesses @1334198500 +system.cpu2: completed 100000 read, 53603 write accesses @1466014000 diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout new file mode 100755 index 000000000..c563af536 --- /dev/null +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Feb 28 2014 18:29:12 +gem5 started Feb 28 2014 18:30:27 +gem5 executing on cz310588hp +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1466014000 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt new file mode 100644 index 000000000..03cf254c4 --- /dev/null +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -0,0 +1,1747 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.001466 # Number of seconds simulated +sim_ticks 1466014000 # Number of ticks simulated +final_tick 1466014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_tick_rate 362824283 # Simulator tick rate (ticks/s) +host_mem_usage 344492 # Number of bytes of host memory used +host_seconds 4.04 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0 81024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 87271 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 81468 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83154 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 83511 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 83243 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 81362 # Number of bytes read from this memory +system.physmem.bytes_read::total 663473 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 418112 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5482 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5323 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5333 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5428 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5332 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5280 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5327 # Number of bytes written to this memory +system.physmem.bytes_written::total 460955 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11124 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10971 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11117 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88850 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6533 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5482 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5323 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5333 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5428 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5332 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5280 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5327 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49376 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 55268231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 56234115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 59529445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 55571093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 56721150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 56964667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 56781859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 55498788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 452569348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 285203279 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 3739391 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 3630934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 3641166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 3637755 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 3702557 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 3637073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 3601603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 3633662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 314427420 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 285203279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 59007622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 59865049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 63170611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 59208848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 60423707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 60601741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 60383462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 59132450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 766996768 # Total bandwidth to/from this memory (bytes/s) +system.membus.snoop_filter.tot_requests 121068 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 119020 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.throughput 766995404 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 85646 # Transaction distribution +system.membus.trans_dist::ReadResp 85644 # Transaction distribution +system.membus.trans_dist::WriteReq 42843 # Transaction distribution +system.membus.trans_dist::WriteResp 42842 # Transaction distribution +system.membus.trans_dist::Writeback 6533 # Transaction distribution +system.membus.trans_dist::UpgradeReq 57248 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46699 # Transaction distribution +system.membus.trans_dist::ReadExReq 48957 # Transaction distribution +system.membus.trans_dist::ReadExResp 3204 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 419616 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1124426 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1124426 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1124426 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.snoops_through_bus 56301 # Total snoops (count) +system.membus.snoop_fanout::samples 121068 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 121068 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 121068 # Request fanout histogram +system.membus.reqLayer0.occupancy 476149500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 32.5 # Layer utilization (%) +system.membus.respLayer0.occupancy 322630500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 22.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 13552 # number of replacements +system.l2c.tags.tagsinuse 786.290427 # Cycle average of tags in use +system.l2c.tags.total_refs 149902 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14350 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.446132 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 730.775276 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.840177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.161871 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.892698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.763865 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.714219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.973391 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.262671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.906259 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.713648 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006994 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006605 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006557 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007092 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006744 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.767862 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 368 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1950254 # Number of tag accesses +system.l2c.tags.data_accesses 1950254 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10780 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10830 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10743 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10804 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10680 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10909 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86336 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 74514 # number of Writeback hits +system.l2c.Writeback_hits::total 74514 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 379 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 357 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 317 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2803 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1848 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1871 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1840 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1894 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14888 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12628 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12667 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12652 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12601 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12697 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12574 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12735 # number of demand (read+write) hits +system.l2c.demand_hits::total 101224 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12628 # number of overall hits +system.l2c.overall_hits::cpu1 12667 # number of overall hits +system.l2c.overall_hits::cpu2 12670 # number of overall hits +system.l2c.overall_hits::cpu3 12652 # number of overall hits +system.l2c.overall_hits::cpu4 12601 # number of overall hits +system.l2c.overall_hits::cpu5 12697 # number of overall hits +system.l2c.overall_hits::cpu6 12574 # number of overall hits +system.l2c.overall_hits::cpu7 12735 # number of overall hits +system.l2c.overall_hits::total 101224 # number of overall hits +system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 743 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 781 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 728 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 729 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 753 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 747 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 720 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5946 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1885 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1879 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1913 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1933 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1894 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15189 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4304 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4329 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4347 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4382 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4378 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4299 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4310 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34720 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5049 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5072 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5152 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5075 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5111 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5131 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5046 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses +system.l2c.demand_misses::total 40666 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5049 # number of overall misses +system.l2c.overall_misses::cpu1 5072 # number of overall misses +system.l2c.overall_misses::cpu2 5152 # number of overall misses +system.l2c.overall_misses::cpu3 5075 # number of overall misses +system.l2c.overall_misses::cpu4 5111 # number of overall misses +system.l2c.overall_misses::cpu5 5131 # number of overall misses +system.l2c.overall_misses::cpu6 5046 # number of overall misses +system.l2c.overall_misses::cpu7 5030 # number of overall misses +system.l2c.overall_misses::total 40666 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 43593500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 43998500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 45727000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 43059000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 43120000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 43827500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 44039000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 42172500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 349537000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 55121000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 55784000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 54929500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 55686500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 54924000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 54520000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 53558500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 55750500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 440274000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 230029000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 231291500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 233753500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 232262000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 233669000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 234419500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 229747500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 230546000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1855718000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 273622500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 275290000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 279480500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 275321000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 276789000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 278247000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 273786500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 272718500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2205255000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 273622500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 275290000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 279480500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 275321000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 276789000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 278247000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 273786500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 272718500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2205255000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11525 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11539 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11611 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11522 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11472 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11557 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11629 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 92282 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 74514 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 74514 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2235 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2217 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2258 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2268 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2270 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2237 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2250 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2257 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17992 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6152 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6200 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6211 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6205 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6240 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6271 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6193 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6136 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49608 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17677 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17739 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17822 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17727 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17712 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17828 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17620 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17765 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141890 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17677 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17739 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17822 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17727 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17712 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17828 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17620 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17765 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141890 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.064642 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.064390 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.067264 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.063183 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.063546 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.065155 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.065371 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.061914 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.064433 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.852349 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.850248 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.832152 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.839947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.842731 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.838176 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.859111 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.839167 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.844209 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.699610 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.698226 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.703751 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.700564 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.702244 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.698134 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.694171 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.702412 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.699887 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.285625 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.285924 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.289081 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.286286 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.288561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.287806 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.286379 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.283141 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.286602 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.285625 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.285924 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.289081 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.286286 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.288561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.287806 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.286379 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.283141 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.286602 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 58514.765101 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 59217.362046 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 58549.295775 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59146.978022 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 59149.519890 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 58203.851262 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 58954.484605 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 58572.916667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 58785.233771 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28934.908136 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29593.633952 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29233.368813 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29231.758530 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28710.925248 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29077.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 27707.449560 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29435.322070 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28986.371716 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53445.399628 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53428.389928 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53478.265843 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53430.411778 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53324.737563 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 53544.883508 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53442.079553 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53490.951276 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53448.099078 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 54193.404635 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54276.419558 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54246.991460 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54250.443350 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54155.546860 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 54228.610407 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54258.125248 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54218.389662 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54228.470959 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 54193.404635 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54276.419558 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54246.991460 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54250.443350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54155.546860 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 54228.610407 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54258.125248 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54218.389662 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54228.470959 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 6449 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 908 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.102423 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 6534 # number of writebacks +system.l2c.writebacks::total 6534 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 8 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 31 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 742 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 739 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 778 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 726 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 727 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 751 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 744 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 716 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5923 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1905 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1883 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1879 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1904 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1913 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1933 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15186 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4301 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4329 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4347 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4381 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4378 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4298 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4309 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34712 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5043 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5068 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5147 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5073 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5108 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5129 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5042 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5025 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40635 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5043 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5068 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5147 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5073 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5108 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5129 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5042 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5025 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40635 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 34436500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 34879500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 36206000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 34201000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34228500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 34696500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 34883500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 33321000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 276852500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 77532500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76774000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76435500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77640000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 77802000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76297000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78806000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77127500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 618414500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 177611500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 178666500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 180593500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 179431000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 180375000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 181189000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 177424500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 178121500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1433412500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 212048000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 213546000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 216799500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 213632000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 214603500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 215885500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 212308000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 211442500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1710265000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 212048000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 213546000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 216799500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 213632000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 214603500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 215885500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 212308000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 211442500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1710265000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408522500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 408718000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409944000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 402597000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 406388000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405037500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 409992000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 408869000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3260068000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 227084000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222076000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 221597500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 223921500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 226980000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 223544500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 219891000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 221144500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1786239000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 635606500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 630794000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 631541500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 626518500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 633368000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 628582000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 629883000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 630013500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5046307000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064044 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067005 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.063010 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063372 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064982 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.065109 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061570 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.064184 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852349 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.849346 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832152 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.839506 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.842731 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.838176 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859111 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.839167 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.844042 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.699122 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698226 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.703429 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.700564 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.702083 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698134 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.694009 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.702249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.699726 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.285286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.285698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.288800 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.286174 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.287694 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.286152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.282860 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.286384 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.285286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.285698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.288800 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.286174 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.287694 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.286152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.282860 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.286384 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46410.377358 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47198.240866 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46537.275064 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47108.815427 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 47081.843191 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46200.399467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46886.424731 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46537.709497 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46741.938207 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40699.475066 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40772.172066 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40678.818520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40777.310924 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40670.151594 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40691.733333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40768.753233 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40722.016895 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40722.672198 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41295.396419 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41272.002772 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41335.202564 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41276.972625 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41172.106825 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41386.249429 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41280.711959 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41337.085171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41294.437082 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42047.987309 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42136.148382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42121.527103 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42111.571062 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42013.214565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42091.148372 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42107.893693 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42078.109453 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42088.470530 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42047.987309 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42136.148382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42121.527103 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42111.571062 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42013.214565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42091.148372 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42107.893693 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42078.109453 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42088.470530 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.funcbus.throughput 0 # Throughput (bytes/s) +system.funcbus.data_through_bus 0 # Total data (bytes) +system.toL2Bus.snoop_filter.tot_requests 548567 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 252509 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 294010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.throughput 22759385654 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 368934 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 368931 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 42843 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 42841 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 74514 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28540 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28540 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 155707 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 155704 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119464 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119154 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118978 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 118881 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 952985 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1734762 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1749843 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1754305 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751569 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1739334 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1759819 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1742411 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1740191 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 13972234 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 13972234 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 19393344 # Total snoop data (bytes) +system.toL2Bus.snoops_through_bus 313569 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 548567 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.700997 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.184770 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 51420 9.37% 9.37% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 243442 44.38% 53.75% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 138727 25.29% 79.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 68606 12.51% 91.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30441 5.55% 97.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11622 2.12% 99.21% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3640 0.66% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 669 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 548567 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1466016000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 156116317 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 10.6 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 156768205 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 156913339 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 156965244 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 10.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 156103724 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 10.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 156986709 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 10.7 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 156696078 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 156271715 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 10.7 # Layer utilization (%) +system.cpu0.num_reads 99418 # number of read accesses completed +system.cpu0.num_writes 53245 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu0.l1c.tags.replacements 22099 # number of replacements +system.cpu0.l1c.tags.tagsinuse 397.065512 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13209 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.587380 # Average number of references to valid blocks. +system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l1c.tags.occ_blocks::cpu0 397.065512 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.775519 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.775519 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 330123 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 330123 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8700 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8700 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9742 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9742 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9742 # number of overall hits +system.cpu0.l1c.overall_hits::total 9742 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35979 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35979 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 22956 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 22956 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58935 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58935 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58935 # number of overall misses +system.cpu0.l1c.overall_misses::total 58935 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 2431275055 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 2431275055 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1798190271 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1798190271 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 4229465326 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 4229465326 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 4229465326 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 4229465326 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44679 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44679 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 23998 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 23998 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68677 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68677 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68677 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68677 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956580 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956580 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858148 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858148 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858148 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858148 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67574.836849 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 67574.836849 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78332.038291 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 78332.038291 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 71764.916026 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 71764.916026 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 71764.916026 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 71764.916026 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 2152877 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 58943 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.524727 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.l1c.fast_writes 0 # number of fast writes performed +system.cpu0.l1c.cache_copies 0 # number of cache copies performed +system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks +system.cpu0.l1c.writebacks::total 9551 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35979 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22956 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 22956 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58935 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58935 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2355407447 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2355407447 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1750135961 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1750135961 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4105543408 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 4105543408 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4105543408 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 4105543408 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1091154570 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1091154570 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4041529643 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4041529643 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5132684213 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5132684213 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956580 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956580 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858148 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858148 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65466.173240 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65466.173240 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76238.715848 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76238.715848 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.num_reads 99768 # number of read accesses completed +system.cpu1.num_writes 53422 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu1.l1c.tags.replacements 22481 # number of replacements +system.cpu1.l1c.tags.tagsinuse 398.933743 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13300 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.581472 # Average number of references to valid blocks. +system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l1c.tags.occ_blocks::cpu1 398.933743 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.779167 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.779167 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 331866 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 331866 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8705 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8705 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1116 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1116 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9821 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9821 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9821 # number of overall hits +system.cpu1.l1c.overall_hits::total 9821 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36262 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36262 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22965 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22965 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 59227 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 59227 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 59227 # number of overall misses +system.cpu1.l1c.overall_misses::total 59227 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 2445520804 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 2445520804 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1800113040 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1800113040 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 4245633844 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 4245633844 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 4245633844 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 4245633844 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44967 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44967 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24081 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24081 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69048 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69048 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69048 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69048 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806414 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.806414 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953656 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953656 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857766 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857766 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857766 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857766 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67440.317798 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 67440.317798 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78385.065970 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 78385.065970 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 71684.094146 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 71684.094146 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 71684.094146 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 71684.094146 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 2169051 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 59314 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.568955 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.l1c.fast_writes 0 # number of fast writes performed +system.cpu1.l1c.cache_copies 0 # number of cache copies performed +system.cpu1.l1c.writebacks::writebacks 9774 # number of writebacks +system.cpu1.l1c.writebacks::total 9774 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36262 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36262 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22965 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 59227 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 59227 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 59227 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 59227 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2368901584 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2368901584 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1752103572 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1752103572 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4121005156 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 4121005156 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4121005156 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 4121005156 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1095385986 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1095385986 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 3917382799 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 3917382799 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5012768785 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5012768785 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806414 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806414 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953656 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953656 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857766 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857766 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65327.383597 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65327.383597 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76294.516525 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76294.516525 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 53603 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu2.l1c.tags.replacements 22539 # number of replacements +system.cpu2.l1c.tags.tagsinuse 397.267456 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13362 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22949 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.582248 # Average number of references to valid blocks. +system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.l1c.tags.occ_blocks::cpu2 397.267456 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.775913 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.775913 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 285 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 332293 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 332293 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9823 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9823 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9823 # number of overall hits +system.cpu2.l1c.overall_hits::total 9823 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36321 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36321 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22996 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22996 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59317 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59317 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59317 # number of overall misses +system.cpu2.l1c.overall_misses::total 59317 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 2442264018 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 2442264018 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1799405026 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1799405026 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 4241669044 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 4241669044 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 4241669044 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 4241669044 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45082 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45082 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24058 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69140 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69140 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69140 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69140 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805665 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805665 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955857 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955857 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857926 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857926 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857926 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857926 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67241.100686 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 67241.100686 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78248.609584 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 78248.609584 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 71508.489033 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 71508.489033 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 71508.489033 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 71508.489033 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 2171204 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.530731 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.l1c.fast_writes 0 # number of fast writes performed +system.cpu2.l1c.cache_copies 0 # number of cache copies performed +system.cpu2.l1c.writebacks::writebacks 9704 # number of writebacks +system.cpu2.l1c.writebacks::total 9704 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36321 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36321 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22996 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22996 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59317 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59317 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59317 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59317 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2365672458 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2365672458 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1751310602 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1751310602 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4116983060 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 4116983060 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4116983060 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 4116983060 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1097675449 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1097675449 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3894001300 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3894001300 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 4991676749 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 4991676749 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805665 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805665 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955857 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955857 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857926 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857926 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65132.360287 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65132.360287 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76157.183945 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76157.183945 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.num_reads 99664 # number of read accesses completed +system.cpu3.num_writes 53618 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu3.l1c.tags.replacements 22539 # number of replacements +system.cpu3.l1c.tags.tagsinuse 397.521626 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13272 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22952 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.578250 # Average number of references to valid blocks. +system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.l1c.tags.occ_blocks::cpu3 397.521626 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.776409 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.776409 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 332331 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 332331 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8701 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8701 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1040 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1040 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9741 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9741 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9741 # number of overall hits +system.cpu3.l1c.overall_hits::total 9741 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36310 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36310 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23079 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23079 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59389 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59389 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59389 # number of overall misses +system.cpu3.l1c.overall_misses::total 59389 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 2444229866 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 2444229866 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1811981579 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1811981579 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 4256211445 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 4256211445 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 4256211445 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 4256211445 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45011 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45011 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24119 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 69130 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 69130 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 69130 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 69130 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806692 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956880 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956880 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859092 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859092 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859092 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859092 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67315.611842 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 67315.611842 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78512.135664 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 78512.135664 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 71666.662934 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 71666.662934 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 71666.662934 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 71666.662934 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 2167444 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 59346 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.522158 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.l1c.fast_writes 0 # number of fast writes performed +system.cpu3.l1c.cache_copies 0 # number of cache copies performed +system.cpu3.l1c.writebacks::writebacks 9755 # number of writebacks +system.cpu3.l1c.writebacks::total 9755 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36310 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36310 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23079 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23079 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59389 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59389 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59389 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59389 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2367603538 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2367603538 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1763687167 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1763687167 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4131290705 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 4131290705 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4131290705 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 4131290705 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1080268673 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1080268673 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 3893349735 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 3893349735 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 4973618408 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 4973618408 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806692 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956880 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956880 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859092 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859092 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65205.275076 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65205.275076 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76419.566142 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76419.566142 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu4.num_reads 99015 # number of read accesses completed +system.cpu4.num_writes 53820 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu4.l1c.tags.replacements 22084 # number of replacements +system.cpu4.l1c.tags.tagsinuse 396.195798 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13300 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.591427 # Average number of references to valid blocks. +system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu4.l1c.tags.occ_blocks::cpu4 396.195798 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.773820 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.773820 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 330427 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 330427 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8669 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8669 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1045 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1045 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9714 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9714 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9714 # number of overall hits +system.cpu4.l1c.overall_hits::total 9714 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35948 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35948 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23093 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23093 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59041 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59041 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59041 # number of overall misses +system.cpu4.l1c.overall_misses::total 59041 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 2417278257 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 2417278257 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1822150466 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1822150466 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 4239428723 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 4239428723 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 4239428723 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 4239428723 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44617 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44617 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24138 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24138 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68755 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68755 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68755 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68755 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805702 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805702 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956707 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956707 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858716 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858716 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858716 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858716 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67243.748108 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 67243.748108 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78904.883125 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 78904.883125 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 71804.825850 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 71804.825850 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 71804.825850 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 71804.825850 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 2163506 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 58921 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.718759 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu4.l1c.fast_writes 0 # number of fast writes performed +system.cpu4.l1c.cache_copies 0 # number of cache copies performed +system.cpu4.l1c.writebacks::writebacks 9586 # number of writebacks +system.cpu4.l1c.writebacks::total 9586 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35948 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35948 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23093 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23093 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59041 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59041 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59041 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59041 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2341432849 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2341432849 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1773798174 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1773798174 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4115231023 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 4115231023 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4115231023 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 4115231023 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1089200967 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1089200967 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 3986639198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 3986639198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5075840165 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5075840165 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805702 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805702 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956707 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956707 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858716 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858716 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858716 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858716 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65133.883637 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65133.883637 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 76811.075824 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 76811.075824 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu5.num_reads 99463 # number of read accesses completed +system.cpu5.num_writes 53761 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu5.l1c.tags.replacements 22236 # number of replacements +system.cpu5.l1c.tags.tagsinuse 396.818591 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13326 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.588526 # Average number of references to valid blocks. +system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu5.l1c.tags.occ_blocks::cpu5 396.818591 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.775036 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.775036 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 332464 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 332464 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8698 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8698 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1095 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1095 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9793 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9793 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9793 # number of overall hits +system.cpu5.l1c.overall_hits::total 9793 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36190 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36190 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23188 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23188 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59378 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59378 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59378 # number of overall misses +system.cpu5.l1c.overall_misses::total 59378 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 2440787473 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 2440787473 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1818333892 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1818333892 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 4259121365 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 4259121365 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 4259121365 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 4259121365 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44888 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44888 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24283 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24283 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69171 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69171 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69171 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69171 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806229 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806229 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954907 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954907 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858423 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858423 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858423 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858423 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 67443.699171 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 67443.699171 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78417.021390 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 78417.021390 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 71728.946159 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 71728.946159 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 71728.946159 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 71728.946159 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 2173855 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 59485 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.544591 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu5.l1c.fast_writes 0 # number of fast writes performed +system.cpu5.l1c.cache_copies 0 # number of cache copies performed +system.cpu5.l1c.writebacks::writebacks 9794 # number of writebacks +system.cpu5.l1c.writebacks::total 9794 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36190 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23188 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23188 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59378 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59378 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2364411063 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2364411063 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1769767596 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1769767596 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4134178659 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 4134178659 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4134178659 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 4134178659 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1083354468 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1083354468 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3885222198 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 3885222198 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 4968576666 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 4968576666 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806229 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806229 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954907 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954907 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858423 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858423 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858423 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 65333.270600 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 65333.270600 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76322.563222 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76322.563222 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 69624.754269 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 69624.754269 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu6.num_reads 99150 # number of read accesses completed +system.cpu6.num_writes 53258 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu6.l1c.tags.replacements 22399 # number of replacements +system.cpu6.l1c.tags.tagsinuse 397.638402 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13152 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.577374 # Average number of references to valid blocks. +system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu6.l1c.tags.occ_blocks::cpu6 397.638402 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.776638 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.776638 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 330920 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 330920 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8542 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8542 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1117 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1117 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9659 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9659 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9659 # number of overall hits +system.cpu6.l1c.overall_hits::total 9659 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36110 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36110 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23056 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23056 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59166 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59166 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59166 # number of overall misses +system.cpu6.l1c.overall_misses::total 59166 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 2440095733 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 2440095733 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1804973992 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1804973992 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 4245069725 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 4245069725 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 4245069725 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 4245069725 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44652 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44652 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24173 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24173 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68825 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68825 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68825 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68825 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808698 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808698 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953791 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953791 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859659 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859659 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859659 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859659 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67573.961036 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 67573.961036 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78286.519431 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 78286.519431 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 71748.465757 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 71748.465757 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 71748.465757 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 71748.465757 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 2172077 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.545419 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu6.l1c.fast_writes 0 # number of fast writes performed +system.cpu6.l1c.cache_copies 0 # number of cache copies performed +system.cpu6.l1c.writebacks::writebacks 9755 # number of writebacks +system.cpu6.l1c.writebacks::total 9755 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36110 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36110 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23056 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23056 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59166 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59166 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59166 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59166 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2363759609 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2363759609 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1756697682 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1756697682 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4120457291 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 4120457291 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4120457291 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 4120457291 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1098306924 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1098306924 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 3880453768 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 3880453768 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 4978760692 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 4978760692 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808698 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808698 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953791 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953791 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859659 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859659 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859659 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859659 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65459.972556 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65459.972556 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76192.647554 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76192.647554 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69642.316381 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69642.316381 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu7.num_reads 99292 # number of read accesses completed +system.cpu7.num_writes 53734 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed +system.cpu7.l1c.tags.replacements 22176 # number of replacements +system.cpu7.l1c.tags.tagsinuse 397.484138 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13353 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.591783 # Average number of references to valid blocks. +system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu7.l1c.tags.occ_blocks::cpu7 397.484138 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.776336 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.776336 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 330932 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 330932 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8693 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8693 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1154 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1154 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9847 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9847 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9847 # number of overall hits +system.cpu7.l1c.overall_hits::total 9847 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36097 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36097 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22922 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22922 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59019 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59019 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59019 # number of overall misses +system.cpu7.l1c.overall_misses::total 59019 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 2444006416 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 2444006416 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1801319117 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1801319117 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 4245325533 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 4245325533 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 4245325533 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 4245325533 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44790 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44790 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24076 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24076 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68866 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68866 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68866 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68866 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805916 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805916 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952068 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.952068 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857012 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857012 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857012 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857012 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 67706.635344 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 67706.635344 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78584.727205 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 78584.727205 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 71931.505668 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 71931.505668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 71931.505668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 71931.505668 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 2180293 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 59208 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.824297 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu7.l1c.fast_writes 0 # number of fast writes performed +system.cpu7.l1c.cache_copies 0 # number of cache copies performed +system.cpu7.l1c.writebacks::writebacks 9569 # number of writebacks +system.cpu7.l1c.writebacks::total 9569 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36097 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36097 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22922 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22922 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59019 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59019 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59019 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59019 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2367752098 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2367752098 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1753332745 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1753332745 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4121084843 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 4121084843 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4121084843 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 4121084843 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1099641500 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1099641500 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 3936158285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 3936158285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5035799785 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5035799785 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805916 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805916 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952068 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952068 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857012 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857012 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 65594.151813 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 65594.151813 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76491.263633 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76491.263633 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |