diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/configs/memtest-filter.py | 12 | ||||
| -rw-r--r-- | tests/configs/memtest-ruby.py | 16 | ||||
| -rw-r--r-- | tests/configs/memtest.py | 11 |
3 files changed, 9 insertions, 30 deletions
diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py index 35d64a793..42dd05639 100644 --- a/tests/configs/memtest-filter.py +++ b/tests/configs/memtest-filter.py @@ -36,8 +36,7 @@ nb_cores = 8 cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated -system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentXBar(), +system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentXBar(width=16, snoop_filter = SnoopFilter())) # Dummy voltage domain for all our clock domains @@ -63,15 +62,11 @@ for cpu in cpus: # All cpus are associated with cpu_clk_domain cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) - cpu.l1c.cpu_side = cpu.test + cpu.l1c.cpu_side = cpu.port cpu.l1c.mem_side = system.toL2Bus.slave - system.funcbus.slave = cpu.functional system.system_port = system.membus.slave -# connect reference memory to funcbus -system.funcmem.port = system.funcbus.master - # connect memory to membus system.physmem.port = system.membus.master @@ -82,6 +77,3 @@ system.physmem.port = system.membus.master root = Root( full_system = False, system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="Cache CachePort MemoryAccess" -#root.trace.cycle=1 - diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index f71370c5e..cbe41301c 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -70,7 +70,7 @@ options.ports=32 nb_cores = 8 # ruby does not support atomic, functional, or uncacheable accesses -cpus = [ MemTest(atomic=False, percent_functional=50, +cpus = [ MemTest(percent_functional=50, percent_uncacheable=0, suppress_func_warnings=True) \ for i in xrange(nb_cores) ] @@ -78,9 +78,7 @@ cpus = [ MemTest(atomic=False, percent_functional=50, options.num_cpus = nb_cores # system simulated -system = System(cpu = cpus, - funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentXBar()) +system = System(cpu = cpus) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock = '1GHz', @@ -107,21 +105,17 @@ assert(len(cpus) == len(system.ruby._cpu_ports)) for (i, ruby_port) in enumerate(system.ruby._cpu_ports): # - # Tie the cpu test and functional ports to the ruby cpu ports and + # Tie the cpu port to the ruby cpu ports and # physmem, respectively # - cpus[i].test = ruby_port.slave - cpus[i].functional = system.funcbus.slave - + cpus[i].port = ruby_port.slave + # # Since the memtester is incredibly bursty, increase the deadlock # threshold to 1 million cycles # ruby_port.deadlock_threshold = 1000000 -# connect reference memory to funcbus -system.funcmem.port = system.funcbus.master - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index e1bdc64fa..42f50ce3b 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -36,8 +36,7 @@ nb_cores = 8 cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated -system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentXBar(), +system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentXBar(width=16)) # Dummy voltage domain for all our clock domains @@ -62,15 +61,11 @@ for cpu in cpus: # All cpus are associated with cpu_clk_domain cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) - cpu.l1c.cpu_side = cpu.test + cpu.l1c.cpu_side = cpu.port cpu.l1c.mem_side = system.toL2Bus.slave - system.funcbus.slave = cpu.functional system.system_port = system.membus.slave -# connect reference memory to funcbus -system.funcmem.port = system.funcbus.master - # connect memory to membus system.physmem.port = system.membus.master @@ -81,6 +76,4 @@ system.physmem.port = system.membus.master root = Root( full_system = False, system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="Cache CachePort MemoryAccess" -#root.trace.cycle=1 |