diff options
Diffstat (limited to 'tests')
-rw-r--r-- | tests/configs/inorder-timing.py | 2 | ||||
-rw-r--r-- | tests/configs/o3-timing-checker.py | 2 | ||||
-rw-r--r-- | tests/configs/o3-timing-mp.py | 2 | ||||
-rw-r--r-- | tests/configs/o3-timing.py | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py index 5f2156ff9..edec312d0 100644 --- a/tests/configs/inorder-timing.py +++ b/tests/configs/inorder-timing.py @@ -50,7 +50,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), cpu.clock = '2GHz' system = System(cpu = cpu, - physmem = SimpleMemory(), + physmem = SimpleDRAM(), membus = CoherentBus()) system.system_port = system.membus.slave system.physmem.port = system.membus.master diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py index a54c9b7ca..4ff3f0187 100644 --- a/tests/configs/o3-timing-checker.py +++ b/tests/configs/o3-timing-checker.py @@ -63,7 +63,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), cpu.clock = '2GHz' system = System(cpu = cpu, - physmem = SimpleMemory(), + physmem = SimpleDRAM(), membus = CoherentBus()) system.system_port = system.membus.slave system.physmem.port = system.membus.master diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index b02b43d03..2b611fb9d 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -35,7 +35,7 @@ nb_cores = 4 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] # system simulated -system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) +system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus()) # l2cache & bus system.toL2Bus = CoherentBus(clock = '2GHz') diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index f87e0e355..b9bc40bc2 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), cpu.clock = '2GHz' system = System(cpu = cpu, - physmem = SimpleMemory(), + physmem = SimpleDRAM(), membus = CoherentBus()) system.system_port = system.membus.slave system.physmem.port = system.membus.master |