diff options
Diffstat (limited to 'tests')
24 files changed, 0 insertions, 9178 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/EMPTY b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/EMPTY diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini deleted file mode 100644 index 8ba8fdf37..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini +++ /dev/null @@ -1,902 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dtb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 opClasses2 opClasses3 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] -type=MinorOpClass -eventq_index=0 -opClass=FloatMemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] -type=MinorOpClass -eventq_index=0 -opClass=FloatMemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=RiscvInterrupts -eventq_index=0 - -[system.cpu.isa] -type=RiscvISA -eventq_index=0 - -[system.cpu.itb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=insttest -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json deleted file mode 100644 index 5ab2c4281..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json +++ /dev/null @@ -1,1211 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "membus": { - "point_of_coherency": true, - "system": "system", - "response_latency": 2, - "cxx_class": "CoherentXBar", - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "width": 16, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.physmem.port" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 3, - "slave": { - "peer": [ - "system.system_port", - "system.cpu.l2cache.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.membus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 1 - }, - "power_model": null, - "path": "system.membus", - "snoop_response_latency": 4, - "name": "membus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "symbolfile": "", - "readfile": "", - "thermal_model": null, - "cxx_class": "System", - "work_begin_cpu_id_exit": -1, - "load_offset": 0, - "work_begin_exit_count": 0, - "p_state_clk_gate_min": 1000, - "memories": [ - "system.physmem" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [], - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "System", - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.voltage_domain", - "type": "VoltageDomain" - }, - "cache_line_size": 64, - "boot_osflags": "a", - "system_port": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "physmem": { - "static_frontend_latency": 10000, - "tRFC": 260000, - "activation_limit": 4, - "in_addr_map": true, - "IDD3N2": "0.0", - "tWTR": 7500, - "IDD52": "0.0", - "clk_domain": "system.clk_domain", - "channels": 1, - "write_buffer_size": 64, - "device_bus_width": 8, - "VDD": "1.5", - "write_high_thresh_perc": 85, - "cxx_class": "DRAMCtrl", - "bank_groups_per_rank": 0, - "IDD2N2": "0.0", - "port": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "tCCD_L": 0, - "IDD2N": "0.032", - "p_state_clk_gate_min": 1000, - "null": false, - "IDD2P1": "0.032", - "eventq_index": 0, - "tRRD": 6000, - "tRTW": 2500, - "IDD4R": "0.157", - "burst_length": 8, - "tRTP": 7500, - "IDD4W": "0.125", - "tWR": 15000, - "banks_per_rank": 8, - "devices_per_rank": 8, - "IDD2P02": "0.0", - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "IDD6": "0.02", - "IDD5": "0.235", - "tRCD": 13750, - "type": "DRAMCtrl", - "IDD3P02": "0.0", - "tRRD_L": 0, - "IDD0": "0.055", - "IDD62": "0.0", - "min_writes_per_switch": 16, - "mem_sched_policy": "frfcfs", - "IDD02": "0.0", - "IDD2P0": "0.0", - "ranks_per_channel": 2, - "page_policy": "open_adaptive", - "IDD4W2": "0.0", - "tCS": 2500, - "power_model": null, - "tCL": 13750, - "read_buffer_size": 32, - "conf_table_reported": true, - "tCK": 1250, - "tRAS": 35000, - "tRP": 13750, - "tBURST": 5000, - "path": "system.physmem", - "tXP": 6000, - "tXS": 270000, - "addr_mapping": "RoRaBaCoCh", - "IDD3P0": "0.0", - "IDD3P1": "0.038", - "IDD3N": "0.038", - "name": "physmem", - "tXSDLL": 0, - "device_size": 536870912, - "kvm_map": true, - "dll": true, - "tXAW": 30000, - "write_low_thresh_perc": 50, - "range": "0:134217727:0:0:0:0", - "VDD2": "0.0", - "IDD2P12": "0.0", - "p_state_clk_gate_bins": 20, - "tXPDLL": 0, - "IDD4R2": "0.0", - "device_rowbuffer_size": 1024, - "static_backend_latency": 10000, - "max_accesses_per_row": 16, - "IDD3P12": "0.0", - "tREFI": 7800000 - }, - "power_model": null, - "work_cpus_ckpt_count": 0, - "thermal_components": [], - "path": "system", - "cpu_clk_domain": { - "name": "cpu_clk_domain", - "clock": [ - 500 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu_clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "work_end_ckpt_count": 0, - "mem_mode": "timing", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "load_addr_mask": 1099511627775, - "cpu": [ - { - "max_insts_any_thread": 0, - "do_statistics_insts": true, - "numThreads": 1, - "fetch1LineSnapWidth": 0, - "fetch1ToFetch2BackwardDelay": 1, - "fetch1FetchLimit": 1, - "executeIssueLimit": 2, - "system": "system", - "executeLSQMaxStoreBufferStoresPerCycle": 2, - "icache": { - "cpu_side": { - "peer": "system.cpu.icache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 2, - "cxx_class": "Cache", - "size": 131072, - "type": "Cache", - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[0]", - "role": "MASTER" - }, - "mshrs": 4, - "writeback_clean": true, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 131072, - "tag_latency": 2, - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 2, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.icache.tags", - "block_size": 64, - "type": "LRU", - "data_latency": 2 - }, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": true, - "prefetch_on_access": false, - "path": "system.cpu.icache", - "data_latency": 2, - "tag_latency": 2, - "name": "icache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 2 - }, - "function_trace": false, - "do_checkpoint_insts": true, - "decodeInputWidth": 2, - "cxx_class": "MinorCPU", - "max_loads_all_threads": 0, - "executeMemoryIssueLimit": 1, - "decodeCycleInput": true, - "max_loads_any_thread": 0, - "executeLSQTransfersQueueSize": 2, - "p_state_clk_gate_max": 1000000000000, - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "checker": null, - "eventq_index": 0, - "executeMemoryWidth": 0, - "default_p_state": "UNDEFINED", - "executeBranchDelay": 1, - "executeMemoryCommitLimit": 1, - "l2cache": { - "cpu_side": { - "peer": "system.cpu.toL2Bus.master[0]", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 20, - "cxx_class": "Cache", - "size": 2097152, - "type": "Cache", - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "mshrs": 20, - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 2097152, - "tag_latency": 20, - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 8, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.l2cache.tags", - "block_size": 64, - "type": "LRU", - "data_latency": 20 - }, - "tgts_per_mshr": 12, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.l2cache", - "data_latency": 20, - "tag_latency": 20, - "name": "l2cache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 8 - }, - "do_quiesce": true, - "type": "MinorCPU", - "executeCycleInput": true, - "executeAllowEarlyMemoryIssue": true, - "executeInputBufferSize": 7, - "icache_port": { - "peer": "system.cpu.icache.cpu_side", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "socket_id": 0, - "progress_interval": 0, - "p_state_clk_gate_min": 1000, - "toL2Bus": { - "point_of_coherency": false, - "system": "system", - "response_latency": 1, - "cxx_class": "CoherentXBar", - "forward_latency": 0, - "clk_domain": "system.cpu_clk_domain", - "width": 32, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.cpu.l2cache.cpu_side" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 1, - "slave": { - "peer": [ - "system.cpu.icache.mem_side", - "system.cpu.dcache.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.cpu.toL2Bus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 0 - }, - "power_model": null, - "path": "system.cpu.toL2Bus", - "snoop_response_latency": 1, - "name": "toL2Bus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "isa": [ - { - "eventq_index": 0, - "path": "system.cpu.isa", - "type": "RiscvISA", - "name": "isa", - "cxx_class": "RiscvISA::ISA" - } - ], - "itb": { - "name": "itb", - "eventq_index": 0, - "cxx_class": "RiscvISA::TLB", - "path": "system.cpu.itb", - "type": "RiscvTLB", - "size": 64 - }, - "interrupts": [ - { - "eventq_index": 0, - "path": "system.cpu.interrupts", - "type": "RiscvInterrupts", - "name": "interrupts", - "cxx_class": "RiscvISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.cpu.dcache.cpu_side", - "role": "MASTER" - }, - "executeFuncUnits": { - "name": "executeFuncUnits", - "eventq_index": 0, - "cxx_class": "MinorFUPool", - "path": "system.cpu.executeFuncUnits", - "funcUnits": [ - { - "issueLat": 1, - "opLat": 3, - "name": "funcUnits0", - "cantForwardFromFUIndices": [], - "opClasses": { - "name": "opClasses", - "opClasses": [ - { - "opClass": "IntAlu", - "name": "opClasses", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", - "type": "MinorOpClass" - } - ], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", - "type": "MinorOpClassSet" - }, - "eventq_index": 0, - "timings": [ - { - "extraAssumedLat": 0, - "description": "Int", - "srcRegsRelativeLats": [ - 2 - ], - "suppress": false, - "mask": 0, - "extraCommitLat": 0, - "eventq_index": 0, - "opClasses": { - "name": "opClasses", - "opClasses": [], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", - "type": "MinorOpClassSet" - }, - "cxx_class": "MinorFUTiming", - "path": "system.cpu.executeFuncUnits.funcUnits0.timings", - "extraCommitLatExpr": null, - "type": "MinorFUTiming", - "match": 0, - "name": "timings" - } - ], - "cxx_class": "MinorFU", - "path": "system.cpu.executeFuncUnits.funcUnits0", - "type": "MinorFU" - }, - { - "issueLat": 1, - "opLat": 3, - "name": "funcUnits1", - "cantForwardFromFUIndices": [], - "opClasses": { - "name": "opClasses", - "opClasses": [ - { - "opClass": "IntAlu", - "name": "opClasses", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", - "type": "MinorOpClass" - } - ], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", - "type": "MinorOpClassSet" - }, - "eventq_index": 0, - "timings": [ - { - "extraAssumedLat": 0, - "description": "Int", - "srcRegsRelativeLats": [ - 2 - ], - "suppress": false, - "mask": 0, - "extraCommitLat": 0, - "eventq_index": 0, - "opClasses": { - "name": "opClasses", - "opClasses": [], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", - "type": "MinorOpClassSet" - }, - "cxx_class": "MinorFUTiming", - "path": "system.cpu.executeFuncUnits.funcUnits1.timings", - "extraCommitLatExpr": null, - "type": "MinorFUTiming", - "match": 0, - "name": "timings" - } - ], - "cxx_class": "MinorFU", - "path": "system.cpu.executeFuncUnits.funcUnits1", - "type": "MinorFU" - }, - { - "issueLat": 1, - "opLat": 3, - "name": "funcUnits2", - "cantForwardFromFUIndices": [], - "opClasses": { - "name": "opClasses", - "opClasses": [ - { - "opClass": "IntMult", - "name": "opClasses", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", - "type": "MinorOpClass" - } - ], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", - "type": "MinorOpClassSet" - }, - "eventq_index": 0, - "timings": [ - { - "extraAssumedLat": 0, - "description": "Mul", - "srcRegsRelativeLats": [ - 0 - ], - "suppress": false, - "mask": 0, - "extraCommitLat": 0, - "eventq_index": 0, - "opClasses": { - "name": "opClasses", - "opClasses": [], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", - "type": "MinorOpClassSet" - }, - "cxx_class": "MinorFUTiming", - "path": "system.cpu.executeFuncUnits.funcUnits2.timings", - "extraCommitLatExpr": null, - "type": "MinorFUTiming", - "match": 0, - "name": "timings" - } - ], - "cxx_class": "MinorFU", - "path": "system.cpu.executeFuncUnits.funcUnits2", - "type": "MinorFU" - }, - { - "issueLat": 9, - "opLat": 9, - "name": "funcUnits3", - "cantForwardFromFUIndices": [], - "opClasses": { - "name": "opClasses", - "opClasses": [ - { - "opClass": "IntDiv", - "name": "opClasses", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", - "type": "MinorOpClass" - } - ], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", - "type": "MinorOpClassSet" - }, - "eventq_index": 0, - "timings": [], - "cxx_class": "MinorFU", - "path": "system.cpu.executeFuncUnits.funcUnits3", - "type": "MinorFU" - }, - { - "issueLat": 1, - "opLat": 6, - "name": "funcUnits4", - "cantForwardFromFUIndices": [], - "opClasses": { - "name": "opClasses", - "opClasses": [ - { - "opClass": "FloatAdd", - "name": "opClasses00", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", - "type": "MinorOpClass" - }, - { - "opClass": "FloatCmp", - "name": "opClasses01", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", - "type": "MinorOpClass" - }, - { - "opClass": "FloatCvt", - "name": "opClasses02", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", - "type": "MinorOpClass" - }, - { - "opClass": "FloatMisc", - "name": "opClasses03", - "eventq_index": 0, - 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"size": 262144, - "type": "Cache", - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[1]", - "role": "MASTER" - }, - "mshrs": 4, - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 262144, - "tag_latency": 2, - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 2, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dcache.tags", - "block_size": 64, - "type": "LRU", - "data_latency": 2 - }, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.dcache", - "data_latency": 2, - "tag_latency": 2, - "name": "dcache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 2 - }, - "path": "system.cpu", - "fetch1ToFetch2ForwardDelay": 1, - "decodeInputBufferSize": 3 - } - ], - "multi_thread": false, - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr deleted file mode 100755 index 85a6a33ad..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr +++ /dev/null @@ -1,4 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout deleted file mode 100755 index 5f73fd76b..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout +++ /dev/null @@ -1,121 +0,0 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:43 -gem5 executing on zizzer, pid 34087 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -lui: PASS -lui, negative: PASS -auipc: 0x157E0 -auipc: PASS -jal: PASS -jalr: PASS -beq, equal: PASS -beq, not equal: PASS -bne, equal: PASS -bne, not equal: PASS -blt, less: PASS -blt, equal: PASS -blt, greater: PASS -bge, less: PASS -bge, equal: PASS -bge, greater: PASS -bltu, greater: PASS -bltu, equal: PASS -bltu, less: PASS -bgeu, greater: PASS -bgeu, equal: PASS -bgeu, less: PASS -lb, positive: PASS -lb, negative: PASS -lh, positive: PASS -lh, negative: PASS -lw, positive: PASS -lw, negative: PASS -lbu: PASS -lhu: PASS -sb: PASS -sh: PASS -sw: PASS -addi: PASS -addi, overflow: PASS -slti, true: PASS -slti, false: PASS -sltiu, false: PASS -sltiu, true: PASS -xori (1): PASS -xori (0): PASS -ori (1): PASS -ori (A): PASS -andi (0): PASS -andi (1): PASS -slli, general: PASS -slli, erase: PASS -srli, general: PASS -srli, erase: PASS -srli, negative: PASS -srai, general: PASS -srai, erase: PASS -srai, negative: PASS -add: PASS -add, overflow: PASS -sub: PASS -sub, "overflow": PASS -sll, general: PASS -sll, erase: PASS -slt, true: PASS -slt, false: PASS -sltu, false: PASS -sltu, true: PASS -xor (1): PASS -xor (0): PASS -srl, general: PASS -srl, erase: PASS -srl, negative: PASS -sra, general: PASS -sra, erase: PASS -sra, negative: PASS -or (1): PASS -or (A): PASS -and (0): PASS -and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -fstat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -open, stat: PASS -Bytes read: 1 -String read: -open, read, unlink: [1;31mFAIL[0m (expected 1; found 0) -Exiting @ tick 257396500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt deleted file mode 100644 index b9db11c0c..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt +++ /dev/null @@ -1,761 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000257 # Number of seconds simulated -sim_ticks 257396500 # Number of ticks simulated -final_tick 257396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23064 # Simulator instruction rate (inst/s) -host_op_rate 23064 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29446323 # Simulator tick rate (ticks/s) -host_mem_usage 244684 # Number of bytes of host memory used -host_seconds 8.74 # Real time elapsed on the host -sim_insts 201609 # Number of instructions simulated -sim_ops 201609 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 70720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18880 # Number of bytes read from this memory -system.physmem.bytes_read::total 89600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 70720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 70720 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 274751211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 73349871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 348101081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 274751211 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 274751211 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 274751211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 73349871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 348101081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1400 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1400 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 89600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 89600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 195 # Per bank write bursts -system.physmem.perBankRdBursts::1 221 # Per bank write bursts -system.physmem.perBankRdBursts::2 35 # Per bank write bursts -system.physmem.perBankRdBursts::3 87 # Per bank write bursts -system.physmem.perBankRdBursts::4 141 # Per bank write bursts -system.physmem.perBankRdBursts::5 86 # Per bank write bursts -system.physmem.perBankRdBursts::6 5 # Per bank write bursts -system.physmem.perBankRdBursts::7 106 # Per bank write bursts -system.physmem.perBankRdBursts::8 78 # Per bank write bursts -system.physmem.perBankRdBursts::9 96 # Per bank write bursts -system.physmem.perBankRdBursts::10 80 # Per bank write bursts -system.physmem.perBankRdBursts::11 128 # Per bank write bursts -system.physmem.perBankRdBursts::12 40 # Per bank write bursts -system.physmem.perBankRdBursts::13 27 # Per bank write bursts -system.physmem.perBankRdBursts::14 51 # Per bank write bursts -system.physmem.perBankRdBursts::15 24 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 257156500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1400 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.270073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.910663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.246990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 71 25.91% 25.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 59 21.53% 47.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52 18.98% 66.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26 9.49% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14 5.11% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 23 8.39% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8 2.92% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.09% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 18 6.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 274 # Bytes accessed per row activation -system.physmem.totQLat 19864500 # Total ticks spent queuing -system.physmem.totMemAccLat 46114500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14188.93 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32938.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 348.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 348.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.72 # Data bus utilization in percentage -system.physmem.busUtilRead 2.72 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1124 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 183683.21 # Average gap between requests -system.physmem.pageHitRate 80.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1299480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 690690 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6254640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14953950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 477120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 94483770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6205440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 144648210 # Total energy per rank (pJ) -system.physmem_0.averagePower 561.964316 # Core power per rank (mW) -system.physmem_0.totalIdleTime 223185500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states -system.physmem_0.memoryStateTime::REF 8580000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16154500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25250500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 207201500 # Time in different power states -system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 349140 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3741360 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14751360.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9433500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3408960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 53834790 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 13144800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18682440 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 118017510 # Total energy per rank (pJ) -system.physmem_1.averagePower 458.502938 # Core power per rank (mW) -system.physmem_1.totalIdleTime 227632750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 6246000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 75541750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 34227000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15120250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 118067250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 58095 # Number of BP lookups -system.cpu.branchPred.condPredicted 37339 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4808 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47628 # Number of BTB lookups -system.cpu.branchPred.BTBHits 25748 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.060637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9498 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5462 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 4036 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2282 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 130 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 257396500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 514793 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 201609 # Number of instructions committed -system.cpu.committedOps 201609 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12686 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.553423 # CPI: cycles per instruction -system.cpu.ipc 0.391631 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 132 0.07% 0.07% # Class of committed instruction -system.cpu.op_class_0::IntAlu 120936 59.99% 60.05% # Class of committed instruction -system.cpu.op_class_0::IntMult 297 0.15% 60.20% # Class of committed instruction -system.cpu.op_class_0::IntDiv 166 0.08% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::MemRead 46389 23.01% 83.29% # Class of committed instruction -system.cpu.op_class_0::MemWrite 33689 16.71% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 201609 # Class of committed instruction -system.cpu.tickCycles 299839 # Number of cycles that the object actually ticked -system.cpu.idleCycles 214954 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 237.251323 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 81600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 275.675676 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 237.251323 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.057923 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.057923 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 164496 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 164496 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 48321 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48321 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 33279 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 33279 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 81600 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 81600 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 81600 # number of overall hits -system.cpu.dcache.overall_hits::total 81600 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32769500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32769500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41612500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41612500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41612500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41612500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82100 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82100 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82100 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82100 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001880 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001880 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012141 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012141 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006090 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006090 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006090 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006090 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 97175.824176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 97175.824176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80121.026895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80121.026895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83225 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83225 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 198 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 198 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 204 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 204 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 85 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 85 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 211 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 211 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25093000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25093000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003605 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003605 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96011.764706 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96011.764706 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80246.445498 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80246.445498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 581.971054 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 86953 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1105 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 78.690498 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 581.971054 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.284166 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.284166 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1061 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.518066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 177221 # Number of tag accesses -system.cpu.icache.tags.data_accesses 177221 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 86953 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 86953 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 86953 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 86953 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 86953 # number of overall hits -system.cpu.icache.overall_hits::total 86953 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1105 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1105 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1105 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1105 # number of overall misses -system.cpu.icache.overall_misses::total 1105 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 95598500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 95598500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 95598500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 95598500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 95598500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 95598500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 88058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 88058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 88058 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 88058 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 88058 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 88058 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.012549 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.012549 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.012549 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.012549 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.012549 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.012549 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 86514.479638 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 86514.479638 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 86514.479638 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 86514.479638 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 44 # number of writebacks -system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1105 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1105 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1105 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1105 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 94493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 94493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 94493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 94493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 94493500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 94493500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.012549 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.012549 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.012549 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85514.479638 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85514.479638 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 828.582477 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 45 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1400 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.032143 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 591.965303 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 236.617175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018065 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.025286 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12960 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12960 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 44 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 44 # number of WritebackClean hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1105 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1105 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 84 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 295 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1400 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1105 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 295 # number of overall misses -system.cpu.l2cache.overall_misses::total 1400 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16615500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16615500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 92835500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 92835500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8021000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8021000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92835500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24636500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 117472000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92835500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24636500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 117472000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 44 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 44 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1105 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1105 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 85 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 85 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1105 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1401 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1105 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1401 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.988235 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.988235 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.996622 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.999286 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.996622 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.999286 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78746.445498 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78746.445498 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84014.027149 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84014.027149 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95488.095238 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 95488.095238 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83908.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83908.571429 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1105 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1105 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 84 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 295 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1400 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 295 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1400 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14505500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14505500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81785500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81785500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7181000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7181000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81785500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21686500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 103472000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81785500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21686500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 103472000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.988235 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.988235 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.999286 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.999286 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68746.445498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68746.445498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74014.027149 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74014.027149 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 85488.095238 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85488.095238 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1445 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2254 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2846 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 92480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1401 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000714 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.026717 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1400 99.93% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1401 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 766500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1657500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1400 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1189 # Transaction distribution -system.membus.trans_dist::ReadExReq 211 # Transaction distribution -system.membus.trans_dist::ReadExResp 211 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2800 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 89600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 89600 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1400 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1400 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1400 # Request fanout histogram -system.membus.reqLayer0.occupancy 1611500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 7433000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/EMPTY b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/EMPTY diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini deleted file mode 100644 index d8016ae2d..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini +++ /dev/null @@ -1,211 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=RiscvInterrupts -eventq_index=0 - -[system.cpu.isa] -type=RiscvISA -eventq_index=0 - -[system.cpu.itb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=insttest -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json deleted file mode 100644 index e72d8a19b..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json +++ /dev/null @@ -1,289 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "membus": { - "point_of_coherency": true, - "system": "system", - "response_latency": 2, - "cxx_class": "CoherentXBar", - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "width": 16, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.physmem.port" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 3, - "slave": { - "peer": [ - "system.system_port", - "system.cpu.icache_port", - "system.cpu.dcache_port" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.membus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 1 - }, - "power_model": null, - "path": "system.membus", - "snoop_response_latency": 4, - "name": "membus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "symbolfile": "", - "readfile": "", - "thermal_model": null, - "cxx_class": "System", - "work_begin_cpu_id_exit": -1, - "load_offset": 0, - "work_begin_exit_count": 0, - "p_state_clk_gate_min": 1000, - "memories": [ - "system.physmem" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [], - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "System", - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.voltage_domain", - "type": "VoltageDomain" - }, - "cache_line_size": 64, - "boot_osflags": "a", - "system_port": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "physmem": { - "range": "0:134217727:0:0:0:0", - "latency": 30000, - "name": "physmem", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "kvm_map": true, - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.physmem", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "in_addr_map": true - }, - "power_model": null, - "work_cpus_ckpt_count": 0, - "thermal_components": [], - "path": "system", - "cpu_clk_domain": { - "name": "cpu_clk_domain", - "clock": [ - 500 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu_clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "work_end_ckpt_count": 0, - "mem_mode": "atomic", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "load_addr_mask": 1099511627775, - "cpu": [ - { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "eventq_index": 0, - "cxx_class": "RiscvISA::TLB", - "path": "system.cpu.itb", - "type": "RiscvTLB", - "size": 64 - }, - "simulate_data_stalls": false, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "AtomicSimpleCPU", - "max_loads_all_threads": 0, - "system": "system", - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "width": 1, - "checker": null, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "do_quiesce": true, - "type": "AtomicSimpleCPU", - "fastmem": false, - "profile": 0, - "icache_port": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "p_state_clk_gate_min": 1000, - "interrupts": [ - { - "eventq_index": 0, - "path": "system.cpu.interrupts", - "type": "RiscvInterrupts", - "name": "interrupts", - "cxx_class": "RiscvISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.membus.slave[2]", - "role": "MASTER" - }, - "socket_id": 0, - "power_model": null, - "max_insts_all_threads": 0, - "path": "system.cpu", - "max_loads_any_thread": 0, - "switched_out": false, - "workload": [ - { - "uid": 100, - "pid": 100, - "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", - "drivers": [], - "system": "system", - "gid": 100, - "eventq_index": 0, - "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", - "cwd": "", - "simpoint": 0, - "euid": 100, - "path": "system.cpu.workload", - "max_stack_size": 67108864, - "name": "workload", - "cmd": [ - "insttest" - ], - "errout": "cerr", - "useArchPT": false, - "egid": 100, - "output": "cout" - } - ], - "name": "cpu", - "dtb": { - "name": "dtb", - "eventq_index": 0, - "cxx_class": "RiscvISA::TLB", - "path": "system.cpu.dtb", - "type": "RiscvTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "simulate_inst_stalls": false, - "progress_interval": 0, - "branchPred": null, - "isa": [ - { - "eventq_index": 0, - "path": "system.cpu.isa", - "type": "RiscvISA", - "name": "isa", - "cxx_class": "RiscvISA::ISA" - } - ], - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - } - ], - "multi_thread": false, - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr deleted file mode 100755 index fd133b12b..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Unknown operating system; assuming Linux. -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout deleted file mode 100755 index 97d9d4fd2..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout +++ /dev/null @@ -1,171 +0,0 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:43 -gem5 executing on zizzer, pid 34088 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -lui: PASS -lui, negative: PASS -auipc: 0x157E0 -auipc: PASS -jal: PASS -jalr: PASS -beq, equal: PASS -beq, not equal: PASS -bne, equal: PASS -bne, not equal: PASS -blt, less: PASS -blt, equal: PASS -blt, greater: PASS -bge, less: PASS -bge, equal: PASS -bge, greater: PASS -bltu, greater: PASS -bltu, equal: PASS -bltu, less: PASS -bgeu, greater: PASS -bgeu, equal: PASS -bgeu, less: PASS -lb, positive: PASS -lb, negative: PASS -lh, positive: PASS -lh, negative: PASS -lw, positive: PASS -lw, negative: PASS -lbu: PASS -lhu: PASS -sb: PASS -sh: PASS -sw: PASS -addi: PASS -addi, overflow: PASS -slti, true: PASS -slti, false: PASS -sltiu, false: PASS -sltiu, true: PASS -xori (1): PASS -xori (0): PASS -ori (1): PASS -ori (A): PASS -andi (0): PASS -andi (1): PASS -slli, general: PASS -slli, erase: PASS -srli, general: PASS -srli, erase: PASS -srli, negative: PASS -srai, general: PASS -srai, erase: PASS -srai, negative: PASS -add: PASS -add, overflow: PASS -sub: PASS -sub, "overflow": PASS -sll, general: PASS -sll, erase: PASS -slt, true: PASS -slt, false: PASS -sltu, false: PASS -sltu, true: PASS -xor (1): PASS -xor (0): PASS -srl, general: PASS -srl, erase: PASS -srl, negative: PASS -sra, general: PASS -sra, erase: PASS -sra, negative: PASS -or (1): PASS -or (A): PASS -and (0): PASS -and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540729 -fstat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -open, stat: PASS -Bytes read: 15 -String read: this is a test -open, read, unlink: PASS -times: - tms_utime = 0 - tms_stime = 0 - tms_cutime = 0 - tms_cstime = 0 -times: PASS -timeval: - tv_sec = 1000000000 - tv_usec = 102 -gettimeofday: PASS -Cycles: 210287 -rdcycle: PASS -Time: 1480540732 -rdtime: PASS -Instructions Retired: 215205 -rdinstret: PASS -lwu: PASS -ld: PASS -sd: PASS -addiw: PASS -addiw, overflow: PASS -addiw, truncate: PASS -slliw, general: PASS -slliw, erase: PASS -slliw, truncate: PASS -srliw, general: PASS -srliw, erase: PASS -srliw, negative: PASS -srliw, truncate: PASS -sraiw, general: PASS -sraiw, erase: PASS -sraiw, negative: PASS -sraiw, truncate: PASS -addw: PASS -addw, overflow: PASS -addw, truncate: PASS -subw: PASS -subw, "overflow": PASS -subw, truncate: PASS -sllw, general: PASS -sllw, erase: PASS -sllw, truncate: PASS -srlw, general: PASS -srlw, erase: PASS -srlw, negative: PASS -srlw, truncate: PASS -sraw, general: PASS -sraw, erase: PASS -sraw, negative: PASS -sraw, truncate: PASS -Exiting @ tick 133105500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt deleted file mode 100644 index 774499b09..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt +++ /dev/null @@ -1,153 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000133 # Number of seconds simulated -sim_ticks 133105500 # Number of ticks simulated -final_tick 133105500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24056 # Simulator instruction rate (inst/s) -host_op_rate 24056 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12036090 # Simulator tick rate (ticks/s) -host_mem_usage 234212 # Number of bytes of host memory used -host_seconds 11.06 # Real time elapsed on the host -sim_insts 266028 # Number of instructions simulated -sim_ops 266028 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1064848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 412103 # Number of bytes read from this memory -system.physmem.bytes_read::total 1476951 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1064848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1064848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 270848 # Number of bytes written to this memory -system.physmem.bytes_written::total 270848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 266212 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 62869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 329081 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 43712 # Number of write requests responded to by this memory -system.physmem.num_writes::total 43712 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8000030051 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3096062897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11096092949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8000030051 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8000030051 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2034837028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2034837028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8000030051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5130899925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13130929977 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 183 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 133105500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 266212 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 266028 # Number of instructions committed -system.cpu.committedOps 266028 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 266027 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 19074 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39822 # number of instructions that are conditional controls -system.cpu.num_int_insts 266027 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 351579 # number of times the integer registers were read -system.cpu.num_int_register_writes 182492 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 106582 # number of memory refs -system.cpu.num_load_insts 62869 # Number of load instructions -system.cpu.num_store_insts 43713 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 266212 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 58896 # Number of branches fetched -system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 158769 59.64% 59.71% # Class of executed instruction -system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction -system.cpu.op_class::IntDiv 242 0.09% 59.96% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::MemRead 62869 23.62% 83.58% # Class of executed instruction -system.cpu.op_class::MemWrite 43713 16.42% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 266212 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 329081 # Transaction distribution -system.membus.trans_dist::ReadResp 329081 # Transaction distribution -system.membus.trans_dist::WriteReq 43712 # Transaction distribution -system.membus.trans_dist::WriteResp 43712 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 532424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 213162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 745586 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1064848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 682951 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1747799 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 372793 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 372793 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 372793 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/EMPTY b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/EMPTY diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini deleted file mode 100644 index f98935352..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini +++ /dev/null @@ -1,1265 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=RiscvInterrupts -eventq_index=0 - -[system.cpu.isa] -type=RiscvISA -eventq_index=0 - -[system.cpu.itb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=insttest -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=12 -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer -buffer_size=0 -cacheMemory=system.ruby.l1_cntrl0.cacheMemory -cache_response_latency=12 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -version=0 - -[system.ruby.l1_cntrl0.cacheMemory] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.cacheMemory -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.cacheMemory -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 -power_model=Null -router_id=0 -virt_nets=5 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 -power_model=Null -router_id=1 -virt_nets=5 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 -power_model=Null -router_id=2 -virt_nets=5 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json deleted file mode 100644 index 0c28bed70..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json +++ /dev/null @@ -1,1734 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "symbolfile": "", - "readfile": "", - "thermal_model": null, - "cxx_class": "System", - "work_begin_cpu_id_exit": -1, - "load_offset": 0, - "work_begin_exit_count": 0, - "p_state_clk_gate_min": 1, - "memories": [ - "system.mem_ctrls" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [ - "0:268435455:0:0:0:0" - ], - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "System", - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.voltage_domain", - "type": "VoltageDomain" - }, - "cache_line_size": 64, - "boot_osflags": "a", - "system_port": { - "peer": "system.sys_port_proxy.slave[0]", - "role": "MASTER" - }, - "sys_port_proxy": { - "system": "system", - "support_inst_reqs": true, - "slave": { - "peer": [ - "system.system_port" - ], - "role": "SLAVE" - }, - "name": "sys_port_proxy", - "p_state_clk_gate_min": 1, - "no_retry_on_stall": false, - "p_state_clk_gate_bins": 20, - "support_data_reqs": true, - "cxx_class": "RubyPortProxy", - "clk_domain": "system.clk_domain", - "power_model": null, - "is_cpu_sequencer": true, - "version": 0, - "eventq_index": 0, - "using_ruby_tester": false, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "path": "system.sys_port_proxy", - "type": "RubyPortProxy", - "ruby_system": "system.ruby" - }, - "power_model": null, - "work_cpus_ckpt_count": 0, - "thermal_components": [], - "path": "system", - "ruby": { - "all_instructions": false, - "memory_size_bits": 48, - "cxx_class": "RubySystem", - "l1_cntrl0": { - "requestFromCache": { - "ordered": true, - "name": "requestFromCache", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "master": { - "peer": "system.ruby.network.slave[0]", - "role": "MASTER" - }, - "buffer_size": 0, - "path": "system.ruby.l1_cntrl0.requestFromCache", - "type": "MessageBuffer" - }, - "cxx_class": "L1Cache_Controller", - "forwardToCache": { - "ordered": true, - "name": "forwardToCache", - "cxx_class": "MessageBuffer", - "slave": { - "peer": "system.ruby.network.master[0]", - "role": "SLAVE" - }, - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.l1_cntrl0.forwardToCache", - "type": "MessageBuffer" - }, - "system": "system", - "cluster_id": 0, - "sequencer": { - "no_retry_on_stall": false, - "deadlock_threshold": 500000, - "using_ruby_tester": false, - "system": "system", - "dcache": "system.ruby.l1_cntrl0.cacheMemory", - "cxx_class": "Sequencer", - "garnet_standalone": false, - "clk_domain": "system.cpu.clk_domain", - "icache_hit_latency": 1, - "version": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "type": "RubySequencer", - "icache": "system.ruby.l1_cntrl0.cacheMemory", - "slave": { - "peer": [ - "system.cpu.icache_port", - "system.cpu.dcache_port" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1, - "power_model": null, - "coreid": 99, - "path": "system.ruby.l1_cntrl0.sequencer", - "ruby_system": "system.ruby", - "support_inst_reqs": true, - "name": "sequencer", - "max_outstanding_requests": 16, - "p_state_clk_gate_bins": 20, - "dcache_hit_latency": 1, - "support_data_reqs": true, - "is_cpu_sequencer": true - }, - "type": "L1Cache_Controller", - "issue_latency": 2, - "recycle_latency": 10, - "clk_domain": "system.cpu.clk_domain", - "version": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "number_of_TBEs": 256, - "p_state_clk_gate_min": 1, - "responseToCache": { - "ordered": true, - "name": "responseToCache", - "cxx_class": "MessageBuffer", - "slave": { - "peer": "system.ruby.network.master[1]", - "role": "SLAVE" - }, - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.l1_cntrl0.responseToCache", - "type": "MessageBuffer" - }, - "transitions_per_cycle": 4, - "responseFromCache": { - "ordered": true, - "name": "responseFromCache", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "master": { - "peer": "system.ruby.network.slave[1]", - "role": "MASTER" - }, - "buffer_size": 0, - "path": "system.ruby.l1_cntrl0.responseFromCache", - "type": "MessageBuffer" - }, - "power_model": null, - "cache_response_latency": 12, - "buffer_size": 0, - "send_evictions": false, - "cacheMemory": { - "size": 256, - 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"type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers07", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers07", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers08", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers08", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers09", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers09", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers10", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers10", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers11", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers11", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers12", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers12", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers13", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers13", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers14", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers14", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers15", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers15", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers16", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers16", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers17", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers17", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers18", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers18", - "type": "MessageBuffer" - }, - { - "ordered": true, - "name": "port_buffers19", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.network.routers2.port_buffers19", - "type": "MessageBuffer" - } - ] - } - ], - "power_model": null, - "netifs": [], - "control_msg_size": 8, - "buffer_size": 0, - "endpoint_bandwidth": 1000, - "ruby_system": "system.ruby", - "name": "network", - "p_state_clk_gate_bins": 20, - "ext_links": [ - { - "latency": 1, - "name": "ext_links0", - "weight": 1, - "ext_node": "system.ruby.l1_cntrl0", - "link_id": 0, - "eventq_index": 0, - "cxx_class": "SimpleExtLink", - "path": "system.ruby.network.ext_links0", - "int_node": "system.ruby.network.routers0", - "type": "SimpleExtLink", - "bandwidth_factor": 16 - }, - { - "latency": 1, - "name": "ext_links1", - "weight": 1, - "ext_node": "system.ruby.dir_cntrl0", - "link_id": 1, - "eventq_index": 0, - "cxx_class": "SimpleExtLink", - "path": "system.ruby.network.ext_links1", - "int_node": "system.ruby.network.routers1", - "type": "SimpleExtLink", - "bandwidth_factor": 16 - } - ], - "number_of_virtual_networks": 5, - "path": "system.ruby.network" - }, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.ruby.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "randomization": false, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "phys_mem": null, - "type": "RubySystem", - "p_state_clk_gate_min": 1, - "hot_lines": false, - "power_model": null, - "path": "system.ruby", - "memctrl_clk_domain": { - "name": "memctrl_clk_domain", - "clk_domain": "system.ruby.clk_domain", - "eventq_index": 0, - "cxx_class": "DerivedClockDomain", - "path": "system.ruby.memctrl_clk_domain", - "type": "DerivedClockDomain", - "clk_divider": 3 - }, - "name": "ruby", - "p_state_clk_gate_bins": 20, - "block_size_bytes": 64, - "access_backing_store": false, - "number_of_virtual_networks": 5, - "num_of_sequencers": 1, - "dir_cntrl0": { - "system": "system", - "cluster_id": 0, - "responseFromMemory": { - "ordered": false, - "name": "responseFromMemory", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.dir_cntrl0.responseFromMemory", - "type": "MessageBuffer" - }, - "cxx_class": "Directory_Controller", - "forwardFromDir": { - "ordered": false, - "name": "forwardFromDir", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "master": { - "peer": "system.ruby.network.slave[4]", - "role": "MASTER" - }, - "buffer_size": 0, - "path": "system.ruby.dir_cntrl0.forwardFromDir", - "type": "MessageBuffer" - }, - "dmaRequestToDir": { - "ordered": true, - "name": "dmaRequestToDir", - "cxx_class": "MessageBuffer", - "slave": { - "peer": "system.ruby.network.master[3]", - "role": "SLAVE" - }, - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.dir_cntrl0.dmaRequestToDir", - "type": "MessageBuffer" - }, - "type": "Directory_Controller", - "recycle_latency": 10, - "clk_domain": "system.ruby.clk_domain", - "version": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "directory_latency": 12, - "number_of_TBEs": 256, - "to_memory_controller_latency": 1, - "p_state_clk_gate_min": 1, - "responseFromDir": { - "ordered": false, - "name": "responseFromDir", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "master": { - "peer": "system.ruby.network.slave[2]", - "role": "MASTER" - }, - "buffer_size": 0, - "path": "system.ruby.dir_cntrl0.responseFromDir", - "type": "MessageBuffer" - }, - "transitions_per_cycle": 4, - "memory": { - "peer": "system.mem_ctrls.port", - "role": "MASTER" - }, - "power_model": null, - "buffer_size": 0, - "ruby_system": "system.ruby", - "requestToDir": { - "ordered": true, - "name": "requestToDir", - "cxx_class": "MessageBuffer", - "slave": { - "peer": "system.ruby.network.master[2]", - "role": "SLAVE" - }, - "randomization": false, - "eventq_index": 0, - "buffer_size": 0, - "path": "system.ruby.dir_cntrl0.requestToDir", - "type": "MessageBuffer" - }, - "dmaResponseFromDir": { - "ordered": true, - "name": "dmaResponseFromDir", - "cxx_class": "MessageBuffer", - "randomization": false, - "eventq_index": 0, - "master": { - "peer": "system.ruby.network.slave[3]", - "role": "MASTER" - }, - "buffer_size": 0, - "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", - "type": "MessageBuffer" - }, - "name": "dir_cntrl0", - "p_state_clk_gate_bins": 20, - "directory": { - "name": "directory", - "version": 0, - "eventq_index": 0, - "cxx_class": "DirectoryMemory", - "path": "system.ruby.dir_cntrl0.directory", - "type": "RubyDirectoryMemory", - "numa_high_bit": 5, - "size": 268435456 - }, - "path": "system.ruby.dir_cntrl0" - } - }, - "work_end_ckpt_count": 0, - "mem_mode": "timing", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "load_addr_mask": 1099511627775, - "cpu": { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "eventq_index": 0, - "cxx_class": "RiscvISA::TLB", - "path": "system.cpu.itb", - "type": "RiscvTLB", - "size": 64 - }, - "system": "system", - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "function_trace_start": 0, - "cpu_id": 0, - "checker": null, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "p_state_clk_gate_min": 1, - "interrupts": [ - { - "eventq_index": 0, - "path": "system.cpu.interrupts", - "type": "RiscvInterrupts", - "name": "interrupts", - "cxx_class": "RiscvISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", - "role": "MASTER" - }, - "socket_id": 0, - "power_model": null, - "max_insts_all_threads": 0, - "path": "system.cpu", - "max_loads_any_thread": 0, - "switched_out": false, - "workload": [ - { - "uid": 100, - "pid": 100, - "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", - "drivers": [], - "system": "system", - "gid": 100, - "eventq_index": 0, - "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", - "cwd": "", - "simpoint": 0, - "euid": 100, - "path": "system.cpu.workload", - "max_stack_size": 67108864, - "name": "workload", - "cmd": [ - "insttest" - ], - "errout": "cerr", - "useArchPT": false, - "egid": 100, - "output": "cout" - } - ], - "name": "cpu", - "dtb": { - "name": "dtb", - "eventq_index": 0, - "cxx_class": "RiscvISA::TLB", - "path": "system.cpu.dtb", - "type": "RiscvTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "progress_interval": 0, - "branchPred": null, - "isa": [ - { - "eventq_index": 0, - "path": "system.cpu.isa", - "type": "RiscvISA", - "name": "isa", - "cxx_class": "RiscvISA::ISA" - } - ], - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - }, - "multi_thread": false, - "mem_ctrls": [ - { - "static_frontend_latency": 10, - "tRFC": 260, - "activation_limit": 4, - "in_addr_map": true, - "IDD3N2": "0.0", - "tWTR": 8, - "IDD52": "0.0", - "clk_domain": "system.clk_domain", - "channels": 1, - "write_buffer_size": 64, - "device_bus_width": 8, - "VDD": "1.5", - "write_high_thresh_perc": 85, - "cxx_class": "DRAMCtrl", - "bank_groups_per_rank": 0, - "IDD2N2": "0.0", - "port": { - "peer": "system.ruby.dir_cntrl0.memory", - "role": "SLAVE" - }, - "tCCD_L": 0, - "IDD2N": "0.032", - "p_state_clk_gate_min": 1, - "null": false, - "IDD2P1": "0.032", - "eventq_index": 0, - "tRRD": 6, - "tRTW": 3, - "IDD4R": "0.157", - "burst_length": 8, - "tRTP": 8, - "IDD4W": "0.125", - "tWR": 15, - "banks_per_rank": 8, - "devices_per_rank": 8, - "IDD2P02": "0.0", - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000, - "IDD6": "0.02", - "IDD5": "0.235", - "tRCD": 14, - "type": "DRAMCtrl", - "IDD3P02": "0.0", - "tRRD_L": 0, - "IDD0": "0.055", - "IDD62": "0.0", - "min_writes_per_switch": 16, - "mem_sched_policy": "frfcfs", - "IDD02": "0.0", - "IDD2P0": "0.0", - "ranks_per_channel": 2, - "page_policy": "open_adaptive", - "IDD4W2": "0.0", - "tCS": 3, - "power_model": null, - "tCL": 14, - "read_buffer_size": 32, - "conf_table_reported": true, - "tCK": 1, - "tRAS": 35, - "tRP": 14, - "tBURST": 5, - "path": "system.mem_ctrls", - "tXP": 6, - "tXS": 270, - "addr_mapping": "RoRaBaCoCh", - "IDD3P0": "0.0", - "IDD3P1": "0.038", - "IDD3N": "0.038", - "name": "mem_ctrls", - "tXSDLL": 0, - "device_size": 536870912, - "kvm_map": true, - "dll": true, - "tXAW": 30, - "write_low_thresh_perc": 50, - "range": "0:268435455:5:19:0:0", - "VDD2": "0.0", - "IDD2P12": "0.0", - "p_state_clk_gate_bins": 20, - "tXPDLL": 0, - "IDD4R2": "0.0", - "device_rowbuffer_size": 1024, - "static_backend_latency": 10, - "max_accesses_per_row": 16, - "IDD3P12": "0.0", - "tREFI": 7800 - } - ], - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr deleted file mode 100755 index 63b14556f..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr +++ /dev/null @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Unknown operating system; assuming Linux. -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout deleted file mode 100755 index ea970ac1c..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout +++ /dev/null @@ -1,171 +0,0 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:44 -gem5 executing on zizzer, pid 34093 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -lui: PASS -lui, negative: PASS -auipc: 0x157E0 -auipc: PASS -jal: PASS -jalr: PASS -beq, equal: PASS -beq, not equal: PASS -bne, equal: PASS -bne, not equal: PASS -blt, less: PASS -blt, equal: PASS -blt, greater: PASS -bge, less: PASS -bge, equal: PASS -bge, greater: PASS -bltu, greater: PASS -bltu, equal: PASS -bltu, less: PASS -bgeu, greater: PASS -bgeu, equal: PASS -bgeu, less: PASS -lb, positive: PASS -lb, negative: PASS -lh, positive: PASS -lh, negative: PASS -lw, positive: PASS -lw, negative: PASS -lbu: PASS -lhu: PASS -sb: PASS -sh: PASS -sw: PASS -addi: PASS -addi, overflow: PASS -slti, true: PASS -slti, false: PASS -sltiu, false: PASS -sltiu, true: PASS -xori (1): PASS -xori (0): PASS -ori (1): PASS -ori (A): PASS -andi (0): PASS -andi (1): PASS -slli, general: PASS -slli, erase: PASS -srli, general: PASS -srli, erase: PASS -srli, negative: PASS -srai, general: PASS -srai, erase: PASS -srai, negative: PASS -add: PASS -add, overflow: PASS -sub: PASS -sub, "overflow": PASS -sll, general: PASS -sll, erase: PASS -slt, true: PASS -slt, false: PASS -sltu, false: PASS -sltu, true: PASS -xor (1): PASS -xor (0): PASS -srl, general: PASS -srl, erase: PASS -srl, negative: PASS -sra, general: PASS -sra, erase: PASS -sra, negative: PASS -or (1): PASS -or (A): PASS -and (0): PASS -and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540733 -fstat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540733 -open, stat: PASS -Bytes read: 15 -String read: this is a test -open, read, unlink: PASS -times: - tms_utime = 0 - tms_stime = 0 - tms_cutime = 0 - tms_cstime = 0 -times: PASS -timeval: - tv_sec = 1000000000 - tv_usec = 3935 -gettimeofday: PASS -Cycles: 4032706 -rdcycle: PASS -Time: 1480540736 -rdtime: PASS -Instructions Retired: 215243 -rdinstret: PASS -lwu: PASS -ld: PASS -sd: PASS -addiw: PASS -addiw, overflow: PASS -addiw, truncate: PASS -slliw, general: PASS -slliw, erase: PASS -slliw, truncate: PASS -srliw, general: PASS -srliw, erase: PASS -srliw, negative: PASS -srliw, truncate: PASS -sraiw, general: PASS -sraiw, erase: PASS -sraiw, negative: PASS -sraiw, truncate: PASS -addw: PASS -addw, overflow: PASS -addw, truncate: PASS -subw: PASS -subw, "overflow": PASS -subw, truncate: PASS -sllw, general: PASS -sllw, erase: PASS -sllw, truncate: PASS -srlw, general: PASS -srlw, erase: PASS -srlw, negative: PASS -srlw, truncate: PASS -sraw, general: PASS -sraw, erase: PASS -sraw, negative: PASS -sraw, truncate: PASS -Exiting @ tick 5246466 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt deleted file mode 100644 index 70b5b9855..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt +++ /dev/null @@ -1,644 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.005246 # Number of seconds simulated -sim_ticks 5246466 # Number of ticks simulated -final_tick 5246466 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18477 # Simulator instruction rate (inst/s) -host_op_rate 18477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 364337 # Simulator tick rate (ticks/s) -host_mem_usage 412052 # Number of bytes of host memory used -host_seconds 14.40 # Real time elapsed on the host -sim_insts 266066 # Number of instructions simulated -sim_ops 266066 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 5073344 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 5073344 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5073088 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 5073088 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 79271 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 79271 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 79267 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 79267 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 967002169 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 967002169 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 966953374 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 966953374 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1933955543 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1933955543 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 79271 # Number of read requests accepted -system.mem_ctrls.writeReqs 79267 # Number of write requests accepted -system.mem_ctrls.readBursts 79271 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 79267 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 2666176 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 2407168 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 2784128 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 5073344 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 5073088 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 37612 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 35741 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 4161 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 6493 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 322 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11183 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 1470 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 254 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 44 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 830 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 271 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 850 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 2251 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 11315 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 562 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 405 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 342 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 906 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 4421 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 6791 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 332 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 11984 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 1476 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 255 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 877 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 282 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 852 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 2350 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 11612 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 563 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 405 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 350 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 908 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5246394 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 79271 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 79267 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 41659 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 330 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 402 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2224 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2668 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2708 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2791 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2963 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2810 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2680 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2663 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2661 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2661 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2660 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 15795 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 344.923330 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 229.090130 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 305.803840 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 3621 22.92% 22.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 4154 26.30% 49.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 2325 14.72% 63.94% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 1784 11.29% 75.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 865 5.48% 80.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 706 4.47% 85.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 510 3.23% 88.41% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 328 2.08% 90.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 1502 9.51% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 15795 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 2658 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.670429 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.605623 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 1.463558 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 110 4.14% 4.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 1181 44.43% 48.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 1114 41.91% 90.48% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 223 8.39% 98.87% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 29 1.09% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 2658 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 2658 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.366441 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.340186 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.970216 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 2300 86.53% 86.53% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 19 0.71% 87.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 111 4.18% 91.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 179 6.73% 98.16% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 49 1.84% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 2658 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 835288 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 1626809 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 208295 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 20.05 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 39.05 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 508.19 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 530.67 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 967.00 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 966.95 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.15 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.01 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 29472 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 39888 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 70.75 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.64 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.09 # Average gap between requests -system.mem_ctrls.pageHitRate 81.42 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 79710960 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 43126104 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 282823968 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 218655360 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 414882000.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 659598072 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10126848 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 1616957760 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 62452224 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 21677280 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 3410010576 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 649.963342 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 3773570 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 6170 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 175566 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 65011 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 162636 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 1291123 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 3545960 # Time in different power states -system.mem_ctrls_1.actEnergy 33108180 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 17905776 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 193088448 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 144673344 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 397057440.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 650520024 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 12185088 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 1517506896 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 81936768 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 62020080 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 3110002044 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 592.780368 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 3787958 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 12732 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 167990 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 246912 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 213377 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 1277589 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 3327866 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 183 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5246466 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5246466 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 266066 # Number of instructions committed -system.cpu.committedOps 266066 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 266065 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 19074 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39832 # number of instructions that are conditional controls -system.cpu.num_int_insts 266065 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 351637 # number of times the integer registers were read -system.cpu.num_int_register_writes 182516 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 106592 # number of memory refs -system.cpu.num_load_insts 62875 # Number of load instructions -system.cpu.num_store_insts 43717 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246466 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 58906 # Number of branches fetched -system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 158793 59.64% 59.71% # Class of executed instruction -system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction -system.cpu.op_class::IntDiv 246 0.09% 59.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::MemRead 62875 23.62% 83.58% # Class of executed instruction -system.cpu.op_class::MemWrite 43717 16.42% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 266250 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 158538 # delay histogram for all message -system.ruby.delayHist | 158538 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 158538 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 372842 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 372842 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 372842 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 372841 -system.ruby.latency_hist_seqr::mean 13.071591 -system.ruby.latency_hist_seqr::gmean 2.303358 -system.ruby.latency_hist_seqr::stdev 28.899910 -system.ruby.latency_hist_seqr | 332521 89.19% 89.19% | 37494 10.06% 99.24% | 1855 0.50% 99.74% | 376 0.10% 99.84% | 322 0.09% 99.93% | 238 0.06% 99.99% | 17 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 13 0.00% 100.00% -system.ruby.latency_hist_seqr::total 372841 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 293570 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 293570 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 293570 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 79271 -system.ruby.miss_latency_hist_seqr::mean 57.777182 -system.ruby.miss_latency_hist_seqr::gmean 50.619805 -system.ruby.miss_latency_hist_seqr::stdev 37.283085 -system.ruby.miss_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% -system.ruby.miss_latency_hist_seqr::total 79271 -system.ruby.Directory.incomplete_times_seqr 79270 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 293570 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 79271 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 372841 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.554514 -system.ruby.network.routers0.msg_count.Control::2 79271 -system.ruby.network.routers0.msg_count.Data::2 79267 -system.ruby.network.routers0.msg_count.Response_Data::4 79271 -system.ruby.network.routers0.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers0.msg_bytes.Control::2 634168 -system.ruby.network.routers0.msg_bytes.Data::2 5707224 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.554514 -system.ruby.network.routers1.msg_count.Control::2 79271 -system.ruby.network.routers1.msg_count.Data::2 79267 -system.ruby.network.routers1.msg_count.Response_Data::4 79271 -system.ruby.network.routers1.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers1.msg_bytes.Control::2 634168 -system.ruby.network.routers1.msg_bytes.Data::2 5707224 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.554514 -system.ruby.network.routers2.msg_count.Control::2 79271 -system.ruby.network.routers2.msg_count.Data::2 79267 -system.ruby.network.routers2.msg_count.Response_Data::4 79271 -system.ruby.network.routers2.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers2.msg_bytes.Control::2 634168 -system.ruby.network.routers2.msg_bytes.Data::2 5707224 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 237813 -system.ruby.network.msg_count.Data 237801 -system.ruby.network.msg_count.Response_Data 237813 -system.ruby.network.msg_count.Writeback_Control 237801 -system.ruby.network.msg_byte.Control 1902504 -system.ruby.network.msg_byte.Data 17121672 -system.ruby.network.msg_byte.Response_Data 17122536 -system.ruby.network.msg_byte.Writeback_Control 1902408 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.554666 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 79271 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers0.throttle1.link_utilization 7.554361 -system.ruby.network.routers0.throttle1.msg_count.Control::2 79271 -system.ruby.network.routers0.throttle1.msg_count.Data::2 79267 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 634168 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5707224 -system.ruby.network.routers1.throttle0.link_utilization 7.554361 -system.ruby.network.routers1.throttle0.msg_count.Control::2 79271 -system.ruby.network.routers1.throttle0.msg_count.Data::2 79267 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 634168 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5707224 -system.ruby.network.routers1.throttle1.link_utilization 7.554666 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 79271 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers2.throttle0.link_utilization 7.554666 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 79271 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers2.throttle1.link_utilization 7.554361 -system.ruby.network.routers2.throttle1.msg_count.Control::2 79271 -system.ruby.network.routers2.throttle1.msg_count.Data::2 79267 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 634168 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5707224 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 79271 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 79271 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 79271 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 79267 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 79267 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 79267 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 62875 -system.ruby.LD.latency_hist_seqr::mean 27.680191 -system.ruby.LD.latency_hist_seqr::gmean 7.180276 -system.ruby.LD.latency_hist_seqr::stdev 35.811045 -system.ruby.LD.latency_hist_seqr | 50013 79.54% 79.54% | 11930 18.97% 98.52% | 656 1.04% 99.56% | 86 0.14% 99.70% | 110 0.17% 99.87% | 69 0.11% 99.98% | 11 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 62875 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 30585 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 30585 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 30585 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 32290 -system.ruby.LD.miss_latency_hist_seqr::mean 52.951595 -system.ruby.LD.miss_latency_hist_seqr::gmean 46.459624 -system.ruby.LD.miss_latency_hist_seqr::stdev 34.412980 -system.ruby.LD.miss_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 32290 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 -system.ruby.ST.latency_hist_seqr::samples 43716 -system.ruby.ST.latency_hist_seqr::mean 11.968158 -system.ruby.ST.latency_hist_seqr::gmean 2.425644 -system.ruby.ST.latency_hist_seqr::stdev 26.441690 -system.ruby.ST.latency_hist_seqr | 40932 93.63% 93.63% | 2520 5.76% 99.40% | 167 0.38% 99.78% | 45 0.10% 99.88% | 22 0.05% 99.93% | 18 0.04% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 2 0.00% 99.98% | 10 0.02% 100.00% -system.ruby.ST.latency_hist_seqr::total 43716 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 33299 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33299 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 33299 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 -system.ruby.ST.miss_latency_hist_seqr::samples 10417 -system.ruby.ST.miss_latency_hist_seqr::mean 47.028991 -system.ruby.ST.miss_latency_hist_seqr::gmean 41.206543 -system.ruby.ST.miss_latency_hist_seqr::stdev 36.336668 -system.ruby.ST.miss_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 10417 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 266250 -system.ruby.IFETCH.latency_hist_seqr::mean 9.802941 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.746090 -system.ruby.IFETCH.latency_hist_seqr::stdev 26.280316 -system.ruby.IFETCH.latency_hist_seqr | 241576 90.73% 90.73% | 23044 8.66% 99.39% | 1032 0.39% 99.78% | 245 0.09% 99.87% | 190 0.07% 99.94% | 151 0.06% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 266250 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 229686 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 229686 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 229686 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 36564 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.100837 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 57.898658 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.529976 -system.ruby.IFETCH.miss_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 36564 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 79271 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.777182 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.619805 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.283085 -system.ruby.Directory.miss_mach_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 79271 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 32290 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.951595 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.459624 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.412980 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 32290 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 10417 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.028991 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.206543 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 36.336668 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 10417 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 36564 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.100837 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 57.898658 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.529976 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 36564 -system.ruby.Directory_Controller.GETX 79271 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 79267 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 79271 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 79267 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 79271 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 79267 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 79271 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 62875 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 266250 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 43716 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 79271 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 32290 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 36564 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 10417 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 30585 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 229686 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 33299 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 68854 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 10417 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/EMPTY b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/EMPTY diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini deleted file mode 100644 index eb052bbd2..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini +++ /dev/null @@ -1,380 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dtb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=RiscvInterrupts -eventq_index=0 - -[system.cpu.isa] -type=RiscvISA -eventq_index=0 - -[system.cpu.itb] -type=RiscvTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=insttest -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json deleted file mode 100644 index e14de7091..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json +++ /dev/null @@ -1,508 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "membus": { - "point_of_coherency": true, - "system": "system", - "response_latency": 2, - "cxx_class": "CoherentXBar", - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "width": 16, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.physmem.port" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 3, - "slave": { - "peer": [ - "system.system_port", - "system.cpu.l2cache.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.membus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 1 - }, - "power_model": null, - "path": "system.membus", - "snoop_response_latency": 4, - "name": "membus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "symbolfile": "", - "readfile": "", - "thermal_model": null, - "cxx_class": "System", - "work_begin_cpu_id_exit": -1, - "load_offset": 0, - "work_begin_exit_count": 0, - "p_state_clk_gate_min": 1000, - "memories": [ - "system.physmem" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [], - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "System", - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.voltage_domain", - "type": "VoltageDomain" - }, - "cache_line_size": 64, - "boot_osflags": "a", - "system_port": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "physmem": { - "range": "0:134217727:0:0:0:0", - "latency": 30000, - "name": "physmem", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "kvm_map": true, - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.physmem", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "in_addr_map": true - }, - "power_model": null, - "work_cpus_ckpt_count": 0, - "thermal_components": [], - "path": "system", - "cpu_clk_domain": { - "name": "cpu_clk_domain", - "clock": [ - 500 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu_clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "work_end_ckpt_count": 0, - "mem_mode": "timing", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "load_addr_mask": 1099511627775, - "cpu": [ - { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "eventq_index": 0, - "cxx_class": "RiscvISA::TLB", - "path": "system.cpu.itb", - "type": "RiscvTLB", - "size": 64 - }, - "system": "system", - "icache": { - "cpu_side": { - "peer": "system.cpu.icache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 2, - "cxx_class": "Cache", - "size": 131072, - "type": "Cache", - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[0]", - "role": "MASTER" - }, - "mshrs": 4, - "writeback_clean": true, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 131072, - "tag_latency": 2, - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 2, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.icache.tags", - "block_size": 64, - "type": "LRU", - "data_latency": 2 - }, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": true, - "prefetch_on_access": false, - "path": "system.cpu.icache", - "data_latency": 2, - "tag_latency": 2, - "name": "icache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 2 - }, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "checker": null, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "toL2Bus": { - "point_of_coherency": false, - "system": "system", - "response_latency": 1, - "cxx_class": "CoherentXBar", - "forward_latency": 0, - "clk_domain": "system.cpu_clk_domain", - "width": 32, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.cpu.l2cache.cpu_side" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 1, - "slave": { - "peer": [ - "system.cpu.icache.mem_side", - "system.cpu.dcache.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.cpu.toL2Bus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 0 - }, - "power_model": null, - "path": "system.cpu.toL2Bus", - "snoop_response_latency": 1, - "name": "toL2Bus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.cpu.icache.cpu_side", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "p_state_clk_gate_min": 1000, - "interrupts": [ - { - "eventq_index": 0, - "path": "system.cpu.interrupts", - "type": "RiscvInterrupts", - "name": "interrupts", - "cxx_class": "RiscvISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.cpu.dcache.cpu_side", - "role": "MASTER" - }, - "socket_id": 0, - "power_model": null, - "max_insts_all_threads": 0, - "l2cache": { - "cpu_side": { - "peer": "system.cpu.toL2Bus.master[0]", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 20, - "cxx_class": "Cache", - "size": 2097152, - "type": "Cache", - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "mshrs": 20, - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 2097152, - "tag_latency": 20, - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 8, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.l2cache.tags", - "block_size": 64, - "type": "LRU", - "data_latency": 20 - }, - "tgts_per_mshr": 12, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.l2cache", - "data_latency": 20, - "tag_latency": 20, - "name": "l2cache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 8 - }, - "path": "system.cpu", - "max_loads_any_thread": 0, - "switched_out": false, - "workload": [ - { - "uid": 100, - "pid": 100, - "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", - "drivers": [], - "system": "system", - "gid": 100, - "eventq_index": 0, - "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", - "cwd": "", - "simpoint": 0, - "euid": 100, - "path": "system.cpu.workload", - "max_stack_size": 67108864, - "name": "workload", - "cmd": [ - "insttest" - ], - "errout": "cerr", - "useArchPT": false, - "egid": 100, - "output": "cout" - } - ], - "name": "cpu", - "dtb": { - "name": "dtb", - "eventq_index": 0, - "cxx_class": "RiscvISA::TLB", - "path": "system.cpu.dtb", - "type": "RiscvTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "progress_interval": 0, - "branchPred": null, - "dcache": { - "cpu_side": { - "peer": "system.cpu.dcache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 2, - "cxx_class": "Cache", - "size": 262144, - "type": "Cache", - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[1]", - "role": "MASTER" - }, - "mshrs": 4, - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 262144, - "tag_latency": 2, - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 2, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dcache.tags", - "block_size": 64, - "type": "LRU", - "data_latency": 2 - }, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.dcache", - "data_latency": 2, - "tag_latency": 2, - "name": "dcache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 2 - }, - "isa": [ - { - "eventq_index": 0, - "path": "system.cpu.isa", - "type": "RiscvISA", - "name": "isa", - "cxx_class": "RiscvISA::ISA" - } - ], - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - } - ], - "multi_thread": false, - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr deleted file mode 100755 index fd133b12b..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Unknown operating system; assuming Linux. -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout deleted file mode 100755 index ac54effb0..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout +++ /dev/null @@ -1,121 +0,0 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:43 -gem5 executing on zizzer, pid 34089 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -lui: PASS -lui, negative: PASS -auipc: 0x157E0 -auipc: PASS -jal: PASS -jalr: PASS -beq, equal: PASS -beq, not equal: PASS -bne, equal: PASS -bne, not equal: PASS -blt, less: PASS -blt, equal: PASS -blt, greater: PASS -bge, less: PASS -bge, equal: PASS -bge, greater: PASS -bltu, greater: PASS -bltu, equal: PASS -bltu, less: PASS -bgeu, greater: PASS -bgeu, equal: PASS -bgeu, less: PASS -lb, positive: PASS -lb, negative: PASS -lh, positive: PASS -lh, negative: PASS -lw, positive: PASS -lw, negative: PASS -lbu: PASS -lhu: PASS -sb: PASS -sh: PASS -sw: PASS -addi: PASS -addi, overflow: PASS -slti, true: PASS -slti, false: PASS -sltiu, false: PASS -sltiu, true: PASS -xori (1): PASS -xori (0): PASS -ori (1): PASS -ori (A): PASS -andi (0): PASS -andi (1): PASS -slli, general: PASS -slli, erase: PASS -srli, general: PASS -srli, erase: PASS -srli, negative: PASS -srai, general: PASS -srai, erase: PASS -srai, negative: PASS -add: PASS -add, overflow: PASS -sub: PASS -sub, "overflow": PASS -sll, general: PASS -sll, erase: PASS -slt, true: PASS -slt, false: PASS -sltu, false: PASS -sltu, true: PASS -xor (1): PASS -xor (0): PASS -srl, general: PASS -srl, erase: PASS -srl, negative: PASS -sra, general: PASS -sra, erase: PASS -sra, negative: PASS -or (1): PASS -or (A): PASS -and (0): PASS -and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -fstat: - st_dev = 2054 - st_ino = 58196126 - st_mode = 33277 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540723 -open, stat: PASS -Bytes read: 9 -String read: Ð -open, read, unlink: [1;31mFAIL[0m (expected 1; found 0) -Exiting @ tick 352925500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt deleted file mode 100644 index 32254e280..000000000 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt +++ /dev/null @@ -1,515 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000353 # Number of seconds simulated -sim_ticks 352925500 # Number of ticks simulated -final_tick 352925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23308 # Simulator instruction rate (inst/s) -host_op_rate 23308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40827277 # Simulator tick rate (ticks/s) -host_mem_usage 243536 # Number of bytes of host memory used -host_seconds 8.64 # Real time elapsed on the host -sim_insts 201478 # Number of instructions simulated -sim_ops 201478 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 55168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18368 # Number of bytes read from this memory -system.physmem.bytes_read::total 73536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 55168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 55168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1149 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 156316276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52044978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 208361255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 156316276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156316276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 156316276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52044978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 208361255 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 130 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 352925500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 705851 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 201478 # Number of instructions committed -system.cpu.committedOps 201478 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 201477 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 14627 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 30164 # number of instructions that are conditional controls -system.cpu.num_int_insts 201477 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 266871 # number of times the integer registers were read -system.cpu.num_int_register_writes 137624 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 80078 # number of memory refs -system.cpu.num_load_insts 46389 # Number of load instructions -system.cpu.num_store_insts 33689 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 705851 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44791 # Number of branches fetched -system.cpu.op_class::No_OpClass 132 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 120936 59.99% 60.05% # Class of executed instruction -system.cpu.op_class::IntMult 297 0.15% 60.20% # Class of executed instruction -system.cpu.op_class::IntDiv 166 0.08% 60.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::MemRead 46389 23.01% 83.29% # Class of executed instruction -system.cpu.op_class::MemWrite 33689 16.71% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 201609 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 237.806291 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 79790 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 287 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 278.013937 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 237.806291 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.058058 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.058058 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 287 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.070068 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 160441 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 160441 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 46314 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46314 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 33476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 33476 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 79790 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 79790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 79790 # number of overall hits -system.cpu.dcache.overall_hits::total 79790 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 212 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 287 # number of overall misses -system.cpu.dcache.overall_misses::total 287 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4725000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4725000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13356000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13356000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18081000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18081000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18081000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18081000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46389 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46389 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 80077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 80077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 80077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 80077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001617 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001617 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006293 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006293 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003584 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003584 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 75 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 75 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 212 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 212 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17794000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17794000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17794000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17794000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006293 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006293 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16 # number of replacements -system.cpu.icache.tags.tagsinuse 467.242122 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200748 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 862 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 232.886311 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 467.242122 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.228146 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.228146 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 846 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 632 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.413086 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 404082 # Number of tag accesses -system.cpu.icache.tags.data_accesses 404082 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 200748 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200748 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200748 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200748 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200748 # number of overall hits -system.cpu.icache.overall_hits::total 200748 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 862 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 862 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 862 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 862 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 862 # number of overall misses -system.cpu.icache.overall_misses::total 862 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54307500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54307500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54307500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54307500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54307500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54307500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 201610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 201610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 201610 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 201610 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 201610 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 201610 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004276 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.004276 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.004276 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.004276 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.004276 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.004276 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63001.740139 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63001.740139 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63001.740139 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63001.740139 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16 # number of writebacks -system.cpu.icache.writebacks::total 16 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 862 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 862 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 862 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 862 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53445500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53445500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53445500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53445500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53445500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53445500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004276 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.004276 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.004276 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62001.740139 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62001.740139 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 708.129693 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1149 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.013925 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 470.314864 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 237.814829 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014353 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007258 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.021610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.035065 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 10469 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 10469 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 212 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 212 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 862 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 862 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 75 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 862 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 287 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1149 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 862 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 287 # number of overall misses -system.cpu.l2cache.overall_misses::total 1149 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12826000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12826000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52152000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 52152000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4537500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4537500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52152000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17363500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 69515500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52152000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17363500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 69515500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 212 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 212 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 862 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 862 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 75 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 75 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 862 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 287 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1149 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 862 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 287 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1149 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.160093 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.160093 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.870322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.870322 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 212 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 212 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 862 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 862 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 75 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 75 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1149 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1149 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10706000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10706000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43532000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43532000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3787500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3787500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43532000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14493500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 58025500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43532000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14493500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 58025500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.160093 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.160093 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 16 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 862 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 75 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 574 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2314 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 74560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1149 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1149 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 598500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1293000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 430500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1149 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 937 # Transaction distribution -system.membus.trans_dist::ReadExReq 212 # Transaction distribution -system.membus.trans_dist::ReadExResp 212 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 937 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2298 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2298 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 73536 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1149 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1149 # Request fanout histogram -system.membus.reqLayer0.occupancy 1150000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 5745000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |