diff options
Diffstat (limited to 'tests')
91 files changed, 5900 insertions, 5921 deletions
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 35811282c..9f7c89c7b 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -38,7 +38,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index d4a69d94a..fec21c177 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -39,6 +39,7 @@ class MyCache(BaseCache): class MyL1Cache(MyCache): is_top_level = True + tgts_per_mshr = 20 cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index a4489f192..c697e97a9 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -42,7 +42,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py index 1718a76e8..489b5c5b6 100644 --- a/tests/configs/realview-o3-dual.py +++ b/tests/configs/realview-o3-dual.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 89f320c04..61e7591e6 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 125e228a7..786452a09 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index 13212d5d9..8a003dad8 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index e2efd077d..158bcba97 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index ffc55a28a..c90a30371 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 12:28:18 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 16:59:04 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -40,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 177134936000 because target called exit() +Exiting @ tick 177098873000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index be7b06491..7a98c6c82 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.177135 # Number of seconds simulated -sim_ticks 177134936000 # Number of ticks simulated +sim_seconds 0.177099 # Number of seconds simulated +sim_ticks 177098873000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142557 # Simulator instruction rate (inst/s) -host_tick_rate 41921641 # Simulator tick rate (ticks/s) -host_mem_usage 216920 # Number of bytes of host memory used -host_seconds 4225.38 # Real time elapsed on the host -sim_insts 602359810 # Number of instructions simulated +host_inst_rate 166594 # Simulator instruction rate (inst/s) +host_tick_rate 48979898 # Simulator tick rate (ticks/s) +host_mem_usage 214636 # Number of bytes of host memory used +host_seconds 3615.75 # Real time elapsed on the host +sim_insts 602359805 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,141 +51,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 354269873 # number of cpu cycles simulated +system.cpu.numCycles 354197747 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91159436 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 84245505 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4004866 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 86334569 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80046410 # Number of BTB hits +system.cpu.BPredUnit.lookups 91137531 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 84224367 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4001637 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 86284566 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80014553 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1704802 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1819 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 76808344 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 703901675 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91159436 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81751212 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 159188980 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 18469359 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 103024732 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1704311 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1605 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 76786839 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 703787736 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91137531 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81718864 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 159146597 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 18455506 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 103039518 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 658 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 74435954 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1343690 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 353410599 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.128136 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 620 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 74412736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1337820 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 353350911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.128080 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.980798 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194221784 54.96% 54.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25626631 7.25% 62.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19263980 5.45% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24389254 6.90% 74.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11789340 3.34% 77.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13441910 3.80% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4603453 1.30% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7798173 2.21% 85.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52276074 14.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 194204457 54.96% 54.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25620928 7.25% 62.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 19248235 5.45% 67.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24404617 6.91% 74.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11778472 3.33% 77.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13409998 3.80% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4602257 1.30% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7805373 2.21% 85.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52276574 14.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 353410599 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257316 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.986908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 98916904 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83485006 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 137131028 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19492362 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14385299 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6301332 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2598 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 740264204 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7138 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14385299 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 111881934 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9577242 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 106466 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 143552765 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73906893 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 727334722 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 296 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59781135 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10308783 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 341 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 753003460 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3381092272 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3381092144 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 353350911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257307 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.986991 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 98877750 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83515155 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 137076269 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19506954 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14374783 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6301291 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2551 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 740114896 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7230 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14374783 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 111843103 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9537973 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 119731 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 143514381 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73960940 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 727174418 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 286 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59845789 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10289393 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 752889395 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3380302991 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3380302863 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 125586053 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6434 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6436 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 132024310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 179771780 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 82868403 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 19149565 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24496609 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 702530034 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7346 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 663102893 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 740706 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 99626728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 237214631 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1047 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 353410599 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876296 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734600 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 125472001 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 13297 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 13294 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 132095966 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 179744866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 82855502 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 19180586 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24795671 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 702443112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 663038146 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 743101 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 99536301 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 237037166 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3158 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 353350911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.876430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.733239 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 85472706 24.19% 24.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90623075 25.64% 49.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75986397 21.50% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 42524156 12.03% 83.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 25503318 7.22% 90.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 18123112 5.13% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7244001 2.05% 97.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6628954 1.88% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1304880 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 85428360 24.18% 24.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90441308 25.60% 49.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76153703 21.55% 71.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 42544702 12.04% 83.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 25577763 7.24% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18033700 5.10% 95.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7283699 2.06% 97.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6627828 1.88% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1259848 0.36% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 353410599 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 353350911 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 202122 4.87% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2984901 71.87% 76.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 966402 23.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202982 4.88% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2990868 71.85% 76.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 968637 23.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412611240 62.22% 62.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6564 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412586864 62.23% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued @@ -213,137 +213,137 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 172508534 26.02% 88.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 77976552 11.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 172485012 26.01% 88.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 77959702 11.76% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 663102893 # Type of FU issued -system.cpu.iq.rate 1.871745 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4153425 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006264 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1684510480 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 802175669 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 650244511 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 663038146 # Type of FU issued +system.cpu.iq.rate 1.871943 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4162487 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006278 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1684332755 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 802000478 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 650204091 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 667256298 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 667200613 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29664426 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29662170 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30819183 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 223952 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11801 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12647388 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30792271 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 224606 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11800 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12634488 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13674 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12619 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 13695 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12640 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14385299 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 811787 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 58163 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 702606824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1856146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 179771780 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 82868403 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6016 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13064 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5095 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11801 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4163103 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495424 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4658527 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 656117429 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169139334 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6985464 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 14374783 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 826341 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 58736 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 702522112 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1853549 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 179744866 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 82855502 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 8175 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13020 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5275 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11800 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4156328 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 497844 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4654172 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 656067860 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169121282 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6970286 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69444 # number of nop insts executed -system.cpu.iew.exec_refs 245837823 # number of memory reference insts executed -system.cpu.iew.exec_branches 76466943 # Number of branches executed -system.cpu.iew.exec_stores 76698489 # Number of stores executed -system.cpu.iew.exec_rate 1.852027 # Inst execution rate -system.cpu.iew.wb_sent 652257551 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 650244527 # cumulative count of insts written-back -system.cpu.iew.wb_producers 423314128 # num instructions producing a value -system.cpu.iew.wb_consumers 657393243 # num instructions consuming a value +system.cpu.iew.exec_nop 69496 # number of nop insts executed +system.cpu.iew.exec_refs 245806937 # number of memory reference insts executed +system.cpu.iew.exec_branches 76463124 # Number of branches executed +system.cpu.iew.exec_stores 76685655 # Number of stores executed +system.cpu.iew.exec_rate 1.852264 # Inst execution rate +system.cpu.iew.wb_sent 652210228 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 650204107 # cumulative count of insts written-back +system.cpu.iew.wb_producers 423315850 # num instructions producing a value +system.cpu.iew.wb_consumers 657380921 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835450 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643928 # average fanout of values written-back +system.cpu.iew.wb_rate 1.835709 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643943 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 100255909 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6299 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4064207 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 339025301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.776740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.152545 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 100172226 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6346 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4060978 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 338976129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.776998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.152747 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 108189269 31.91% 31.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 106528342 31.42% 63.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49314404 14.55% 77.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9858111 2.91% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23334525 6.88% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14310366 4.22% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7925881 2.34% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1332062 0.39% 94.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18232341 5.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108154848 31.91% 31.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 106518775 31.42% 63.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49308103 14.55% 77.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9862304 2.91% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23329668 6.88% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14306268 4.22% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7919036 2.34% 94.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1343281 0.40% 94.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18233846 5.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 339025301 # Number of insts commited each cycle -system.cpu.commit.count 602359861 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 338976129 # Number of insts commited each cycle +system.cpu.commit.count 602359856 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173611 # Number of memory references committed -system.cpu.commit.loads 148952596 # Number of loads committed +system.cpu.commit.refs 219173609 # Number of memory references committed +system.cpu.commit.loads 148952595 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828603 # Number of branches committed +system.cpu.commit.branches 70828602 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522647 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522643 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18232341 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18233846 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1023408118 # The number of ROB reads -system.cpu.rob.rob_writes 1419658807 # The number of ROB writes -system.cpu.timesIdled 37049 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 859274 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359810 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated -system.cpu.cpi 0.588137 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.588137 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700285 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700285 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3276148182 # number of integer regfile reads -system.cpu.int_regfile_writes 676030301 # number of integer regfile writes +system.cpu.rob.rob_reads 1023273753 # The number of ROB reads +system.cpu.rob.rob_writes 1419480895 # The number of ROB writes +system.cpu.timesIdled 37084 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 846836 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359805 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated +system.cpu.cpi 0.588017 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588017 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700631 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700631 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3275893571 # number of integer regfile reads +system.cpu.int_regfile_writes 675997918 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 943785902 # number of misc regfile reads -system.cpu.misc_regfile_writes 2660 # number of misc regfile writes -system.cpu.icache.replacements 38 # number of replacements -system.cpu.icache.tagsinuse 657.730766 # Cycle average of tags in use -system.cpu.icache.total_refs 74434959 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 97812.035480 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 943643021 # number of misc regfile reads +system.cpu.misc_regfile_writes 2658 # number of misc regfile writes +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 657.503073 # Cycle average of tags in use +system.cpu.icache.total_refs 74411745 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 766 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 97143.270235 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 657.730766 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.321158 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 74434959 # number of ReadReq hits -system.cpu.icache.demand_hits 74434959 # number of demand (read+write) hits -system.cpu.icache.overall_hits 74434959 # number of overall hits -system.cpu.icache.ReadReq_misses 995 # number of ReadReq misses -system.cpu.icache.demand_misses 995 # number of demand (read+write) misses -system.cpu.icache.overall_misses 995 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34724500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34724500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34724500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 74435954 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 74435954 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 74435954 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 657.503073 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.321046 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 74411745 # number of ReadReq hits +system.cpu.icache.demand_hits 74411745 # number of demand (read+write) hits +system.cpu.icache.overall_hits 74411745 # number of overall hits +system.cpu.icache.ReadReq_misses 991 # number of ReadReq misses +system.cpu.icache.demand_misses 991 # number of demand (read+write) misses +system.cpu.icache.overall_misses 991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 34848500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 34848500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 34848500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 74412736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 74412736 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 74412736 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34898.994975 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34898.994975 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34898.994975 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35164.984864 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35164.984864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35164.984864 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 234 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 234 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 234 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 761 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 761 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 766 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 766 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 766 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26233500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34132.720105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34247.389034 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 441231 # number of replacements -system.cpu.dcache.tagsinuse 4094.754255 # Cycle average of tags in use -system.cpu.dcache.total_refs 205797010 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445327 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 462.125607 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.754255 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999696 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 137942409 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67851936 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1336 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 205794345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 205794345 # number of overall hits -system.cpu.dcache.ReadReq_misses 249307 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1565595 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1814902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1814902 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3284045500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27041000027 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 163000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 30325045527 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30325045527 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 138191716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 441233 # number of replacements +system.cpu.dcache.tagsinuse 4094.750739 # Cycle average of tags in use +system.cpu.dcache.total_refs 205781738 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445329 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 462.089237 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87973000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.750739 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 137926945 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67852137 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1328 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 205779082 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 205779082 # number of overall hits +system.cpu.dcache.ReadReq_misses 249074 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1565394 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 11 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1814468 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1814468 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3282849000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 27038418025 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 203000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30321267025 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30321267025 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 138176019 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 207609247 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 207609247 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001804 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.022553 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.005952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008742 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008742 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13172.696715 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17272.027585 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 20375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16708.916254 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16708.916254 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 1339 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 207593550 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 207593550 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001803 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.022550 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.008215 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008740 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008740 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13180.215518 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17272.595925 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 18454.545455 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 16710.830406 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 16710.830406 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -422,70 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395260 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51378 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1318197 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1369575 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1369575 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197929 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247398 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445327 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445327 # number of overall MSHR misses +system.cpu.dcache.writebacks 395275 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51126 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1318013 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 11 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1369139 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1369139 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197948 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247381 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445329 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445329 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1625138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2544850527 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4169988527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4169988527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1625134500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2544872027 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4170006527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4170006527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001433 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8210.711922 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10286.463621 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8209.906137 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10287.257417 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72978 # number of replacements -system.cpu.l2cache.tagsinuse 17806.299437 # Cycle average of tags in use -system.cpu.l2cache.total_refs 422221 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88511 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.770266 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72960 # number of replacements +system.cpu.l2cache.tagsinuse 17805.724339 # Cycle average of tags in use +system.cpu.l2cache.total_refs 422235 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88493 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.771394 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1880.880475 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15925.418963 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057400 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486005 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165873 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395260 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 189038 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354911 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354911 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32814 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91177 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126440500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2003739500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3130180000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3130180000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198687 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395260 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247401 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 446088 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 446088 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165154 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235904 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204392 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204392 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34328.045956 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34332.359543 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34330.807111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34330.807111 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1879.670498 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15926.053841 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057363 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486025 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165899 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395275 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 189031 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354930 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354930 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32812 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58353 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91165 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91165 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126662000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2003366500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3130028500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3130028500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198711 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395275 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247384 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 446095 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 446095 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165124 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235880 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204362 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204362 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34336.888943 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.850976 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34333.664235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34333.664235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -494,28 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58123 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32806 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91169 # number of overall MSHR misses +system.cpu.l2cache.writebacks 58128 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32801 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58353 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91154 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91154 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1019567500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822366000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2841933500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2841933500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1019608000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822407000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2842015000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2842015000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165114 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235904 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204374 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204374 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31078.689874 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31224.680020 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165069 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235880 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204338 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204338 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31084.662053 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31230.733638 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 80ace0dc5..f1874f64f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -495,7 +495,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index cea2acb5a..df0fa130a 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:07:22 -gem5 started Aug 20 2011 13:07:33 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 58e0bfc8f..8c5bfcb3c 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.408816 # Number of seconds simulated sim_ticks 408816360000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166907 # Simulator instruction rate (inst/s) -host_tick_rate 48544601 # Simulator tick rate (ticks/s) -host_mem_usage 212296 # Number of bytes of host memory used -host_seconds 8421.46 # Real time elapsed on the host +host_inst_rate 252046 # Simulator instruction rate (inst/s) +host_tick_rate 73306837 # Simulator tick rate (ticks/s) +host_mem_usage 206388 # Number of bytes of host memory used +host_seconds 5576.78 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 817632721 # number of cpu cycles simulated @@ -273,7 +273,7 @@ system.cpu.int_regfile_writes 1303867666 # nu system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads system.cpu.fp_regfile_writes 10452290 # number of floating regfile writes system.cpu.misc_regfile_reads 605383822 # number of misc regfile reads -system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes +system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes system.cpu.icache.replacements 166 # number of replacements system.cpu.icache.tagsinuse 1031.400456 # Cycle average of tags in use system.cpu.icache.total_refs 170772098 # Total number of references to valid blocks. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 215751210..864c2771b 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,7 +62,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index 98d918157..3eb09159b 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:15:22 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 920d55128..ae12e23e4 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.744764 # Number of seconds simulated sim_ticks 744764119000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2563815 # Simulator instruction rate (inst/s) -host_tick_rate 1281911834 # Simulator tick rate (ticks/s) -host_mem_usage 220472 # Number of bytes of host memory used -host_seconds 580.98 # Real time elapsed on the host +host_inst_rate 4241689 # Simulator instruction rate (inst/s) +host_tick_rate 2120851440 # Simulator tick rate (ticks/s) +host_mem_usage 196528 # Number of bytes of host memory used +host_seconds 351.16 # Real time elapsed on the host sim_insts 1489523295 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 1489528239 # number of cpu cycles simulated @@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 78161763 # nu system.cpu.num_int_insts 1319481298 # number of integer instructions system.cpu.num_fp_insts 8454127 # number of float instructions system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234411208 # number of times the integer registers were written +system.cpu.num_int_register_writes 1234343158 # number of times the integer registers were written system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written system.cpu.num_mem_refs 569365767 # number of memory refs diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index f78fdda37..6dbddf888 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,7 +165,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index e85428b5b..4a77ef60d 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:19:37 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 1c38bff95..d75fccee8 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 2.064259 # Number of seconds simulated sim_ticks 2064258667000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1125008 # Simulator instruction rate (inst/s) -host_tick_rate 1559093873 # Simulator tick rate (ticks/s) -host_mem_usage 229120 # Number of bytes of host memory used -host_seconds 1324.01 # Real time elapsed on the host +host_inst_rate 2284016 # Simulator instruction rate (inst/s) +host_tick_rate 3165307188 # Simulator tick rate (ticks/s) +host_mem_usage 205232 # Number of bytes of host memory used +host_seconds 652.15 # Real time elapsed on the host sim_insts 1489523295 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 4128517334 # number of cpu cycles simulated @@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 78161763 # nu system.cpu.num_int_insts 1319481298 # number of integer instructions system.cpu.num_fp_insts 8454127 # number of float instructions system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234411207 # number of times the integer registers were written +system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written system.cpu.num_mem_refs 569365767 # number of memory refs diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 51444fd65..78fc12019 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -933,7 +933,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -953,7 +953,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1082,7 +1082,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 35487e816..cb23e1c15 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:21:47 -gem5 started Aug 20 2011 15:21:55 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:05:33 +gem5 started Nov 21 2011 19:03:16 +gem5 executing on u200540-lin command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 106949500 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d2a095e1d..65d49a60e 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -3,10 +3,10 @@ sim_seconds 1.897465 # Number of seconds simulated sim_ticks 1897465263500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131766 # Simulator instruction rate (inst/s) -host_tick_rate 4454253159 # Simulator tick rate (ticks/s) -host_mem_usage 298700 # Number of bytes of host memory used -host_seconds 425.99 # Real time elapsed on the host +host_inst_rate 138767 # Simulator instruction rate (inst/s) +host_tick_rate 4690907118 # Simulator tick rate (ticks/s) +host_mem_usage 293696 # Number of bytes of host memory used +host_seconds 404.50 # Real time elapsed on the host sim_insts 56130966 # Number of instructions simulated system.l2c.replacements 397795 # number of replacements system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use @@ -594,6 +594,7 @@ system.cpu0.rob.rob_reads 136748495 # Th system.cpu0.rob.rob_writes 124811050 # The number of ROB writes system.cpu0.timesIdled 1231942 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 33836909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3682845519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 50542242 # Number of Instructions Simulated system.cpu0.committedInsts_total 50542242 # Number of Instructions Simulated system.cpu0.cpi 2.217524 # CPI: Cycles Per Instruction @@ -1159,6 +1160,7 @@ system.cpu1.rob.rob_reads 15919184 # Th system.cpu1.rob.rob_writes 14457399 # The number of ROB writes system.cpu1.timesIdled 81947 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 698509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3784960163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 5588724 # Number of Instructions Simulated system.cpu1.committedInsts_total 5588724 # Number of Instructions Simulated system.cpu1.cpi 1.783406 # CPI: Cycles Per Instruction diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 2cd4054d5..c437d8a70 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -497,7 +497,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -517,7 +517,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -646,7 +646,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 636c32218..b8893b11f 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:21:47 -gem5 started Aug 20 2011 15:21:55 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:05:33 +gem5 started Nov 21 2011 18:56:50 +gem5 executing on u200540-lin command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1858873594500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index f8131be53..16f374a0c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -3,10 +3,10 @@ sim_seconds 1.858874 # Number of seconds simulated sim_ticks 1858873594500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131543 # Simulator instruction rate (inst/s) -host_tick_rate 4605131786 # Simulator tick rate (ticks/s) -host_mem_usage 295252 # Number of bytes of host memory used -host_seconds 403.65 # Real time elapsed on the host +host_inst_rate 141632 # Simulator instruction rate (inst/s) +host_tick_rate 4958330764 # Simulator tick rate (ticks/s) +host_mem_usage 290572 # Number of bytes of host memory used +host_seconds 374.90 # Real time elapsed on the host sim_insts 53097697 # Number of instructions simulated system.l2c.replacements 391354 # number of replacements system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use @@ -542,6 +542,7 @@ system.cpu.rob.rob_reads 143945413 # Th system.cpu.rob.rob_writes 132113260 # The number of ROB writes system.cpu.timesIdled 1256827 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 34118395 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3601447413 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 53097697 # Number of Instructions Simulated system.cpu.committedInsts_total 53097697 # Number of Instructions Simulated system.cpu.cpi 2.190177 # CPI: Cycles Per Instruction diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 3a986614c..fb7470780 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index eb8b03237..caf37a67b 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout -Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:41:18 -gem5 started Aug 20 2011 15:46:02 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:32:34 +gem5 started Nov 22 2011 02:00:14 +gem5 executing on u200540-lin command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582520130500 because m5_exit instruction encountered +Exiting @ tick 2582494395500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b36a36f09..fc137bfb1 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.582520 # Number of seconds simulated -sim_ticks 2582520130500 # Number of ticks simulated +sim_seconds 2.582494 # Number of seconds simulated +sim_ticks 2582494395500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84908 # Simulator instruction rate (inst/s) -host_tick_rate 2745493933 # Simulator tick rate (ticks/s) -host_mem_usage 385348 # Number of bytes of host memory used -host_seconds 940.64 # Real time elapsed on the host -sim_insts 79867485 # Number of instructions simulated -system.l2c.replacements 132224 # number of replacements -system.l2c.tagsinuse 27582.981749 # Cycle average of tags in use -system.l2c.total_refs 1821382 # Total number of references to valid blocks. -system.l2c.sampled_refs 162180 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.230620 # Average number of references to valid blocks. +host_inst_rate 86259 # Simulator instruction rate (inst/s) +host_tick_rate 2789337609 # Simulator tick rate (ticks/s) +host_mem_usage 380504 # Number of bytes of host memory used +host_seconds 925.85 # Real time elapsed on the host +sim_insts 79862069 # Number of instructions simulated +system.l2c.replacements 132200 # number of replacements +system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use +system.l2c.total_refs 1817822 # Total number of references to valid blocks. +system.l2c.sampled_refs 162144 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.211158 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 5000.765535 # Average occupied blocks per context -system.l2c.occ_blocks::1 7177.119061 # Average occupied blocks per context -system.l2c.occ_blocks::2 15405.097153 # Average occupied blocks per context -system.l2c.occ_percent::0 0.076306 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.109514 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.235063 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 739666 # number of ReadReq hits -system.l2c.ReadReq_hits::1 629011 # number of ReadReq hits -system.l2c.ReadReq_hits::2 183263 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1551940 # number of ReadReq hits -system.l2c.Writeback_hits::0 599118 # number of Writeback hits -system.l2c.Writeback_hits::total 599118 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1040 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 1060 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2100 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 181 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 449 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 630 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 58369 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 39072 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97441 # number of ReadExReq hits -system.l2c.demand_hits::0 798035 # number of demand (read+write) hits -system.l2c.demand_hits::1 668083 # number of demand (read+write) hits -system.l2c.demand_hits::2 183263 # number of demand (read+write) hits -system.l2c.demand_hits::total 1649381 # number of demand (read+write) hits -system.l2c.overall_hits::0 798035 # number of overall hits -system.l2c.overall_hits::1 668083 # number of overall hits -system.l2c.overall_hits::2 183263 # number of overall hits -system.l2c.overall_hits::total 1649381 # number of overall hits -system.l2c.ReadReq_misses::0 19689 # number of ReadReq misses -system.l2c.ReadReq_misses::1 20600 # number of ReadReq misses -system.l2c.ReadReq_misses::2 170 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40459 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 7392 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3836 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11228 # number of UpgradeReq misses +system.l2c.occ_blocks::0 5000.897751 # Average occupied blocks per context +system.l2c.occ_blocks::1 7176.831699 # Average occupied blocks per context +system.l2c.occ_blocks::2 15405.259775 # Average occupied blocks per context +system.l2c.occ_percent::0 0.076308 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.109510 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.235066 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 738573 # number of ReadReq hits +system.l2c.ReadReq_hits::1 628212 # number of ReadReq hits +system.l2c.ReadReq_hits::2 178875 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1545660 # number of ReadReq hits +system.l2c.Writeback_hits::0 598786 # number of Writeback hits +system.l2c.Writeback_hits::total 598786 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 1039 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 1048 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2087 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 175 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 451 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 626 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 58347 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 39083 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 97430 # number of ReadExReq hits +system.l2c.demand_hits::0 796920 # number of demand (read+write) hits +system.l2c.demand_hits::1 667295 # number of demand (read+write) hits +system.l2c.demand_hits::2 178875 # number of demand (read+write) hits +system.l2c.demand_hits::total 1643090 # number of demand (read+write) hits +system.l2c.overall_hits::0 796920 # number of overall hits +system.l2c.overall_hits::1 667295 # number of overall hits +system.l2c.overall_hits::2 178875 # number of overall hits +system.l2c.overall_hits::total 1643090 # number of overall hits +system.l2c.ReadReq_misses::0 19694 # number of ReadReq misses +system.l2c.ReadReq_misses::1 20569 # number of ReadReq misses +system.l2c.ReadReq_misses::2 168 # number of ReadReq misses +system.l2c.ReadReq_misses::total 40431 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 7390 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3840 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11230 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 864 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 461 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1325 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 98007 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 50222 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148229 # number of ReadExReq misses -system.l2c.demand_misses::0 117696 # number of demand (read+write) misses -system.l2c.demand_misses::1 70822 # number of demand (read+write) misses -system.l2c.demand_misses::2 170 # number of demand (read+write) misses -system.l2c.demand_misses::total 188688 # number of demand (read+write) misses -system.l2c.overall_misses::0 117696 # number of overall misses -system.l2c.overall_misses::1 70822 # number of overall misses -system.l2c.overall_misses::2 170 # number of overall misses -system.l2c.overall_misses::total 188688 # number of overall misses -system.l2c.ReadReq_miss_latency 2113875000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 61547500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 8091500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7780940999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9894815999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9894815999 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 759355 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 649611 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 183433 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1592399 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 599118 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 599118 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8432 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4896 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13328 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 1045 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 910 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1955 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 156376 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 89294 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245670 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 915731 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 738905 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 183433 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1838069 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 915731 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 738905 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 183433 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1838069 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025929 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.031711 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000927 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.058567 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.876660 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.783497 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.826794 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.506593 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.626739 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.562434 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.128527 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.095847 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000927 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.225301 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.128527 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.095847 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000927 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.225301 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 107363.248514 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 102615.291262 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 12434558.823529 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12644537.363306 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8326.231061 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 16044.708029 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_misses::1 454 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1318 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 97999 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 50217 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 148216 # number of ReadExReq misses +system.l2c.demand_misses::0 117693 # number of demand (read+write) misses +system.l2c.demand_misses::1 70786 # number of demand (read+write) misses +system.l2c.demand_misses::2 168 # number of demand (read+write) misses +system.l2c.demand_misses::total 188647 # number of demand (read+write) misses +system.l2c.overall_misses::0 117693 # number of overall misses +system.l2c.overall_misses::1 70786 # number of overall misses +system.l2c.overall_misses::2 168 # number of overall misses +system.l2c.overall_misses::total 188647 # number of overall misses +system.l2c.ReadReq_miss_latency 2112279500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 61500500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 8037000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7780237999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9892517499 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9892517499 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 758267 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 648781 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 179043 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1586091 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 598786 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 598786 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 8429 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4888 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13317 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1039 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 905 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1944 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 156346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 89300 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245646 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 914613 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 738081 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 179043 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1831737 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 914613 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 738081 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 179043 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1831737 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.025972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.031704 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.000938 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.058615 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.876735 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.785597 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.831569 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.501657 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.626808 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.562340 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.128681 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.095905 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.000938 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.225524 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.128681 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.095905 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.000938 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.225524 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 107254.976135 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 102692.376878 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 12573092.261905 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12783039.614917 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8322.124493 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 16015.755208 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9365.162037 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17552.060738 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 9302.083333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 17702.643172 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79391.686298 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 154930.926666 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 79390.993775 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 154932.353566 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 84070.962471 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 139713.874206 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 58204799.994118 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 58428584.830795 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 84070.962471 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 139713.874206 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 58204799.994118 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 58428584.830795 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 84053.575820 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 139752.458099 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 58884032.732143 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 59107838.766062 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 84053.575820 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 139752.458099 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 58884032.732143 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 59107838.766062 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,56 +143,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 112853 # number of writebacks -system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 94 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 40365 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 11228 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1325 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148229 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 188594 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 188594 # number of overall MSHR misses +system.l2c.writebacks 112847 # number of writebacks +system.l2c.ReadReq_mshr_hits 98 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 98 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 98 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 40333 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 11230 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1318 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 148216 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 188549 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 188549 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1617473000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 449580000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 53034500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5939516999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7556989999 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7556989999 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131965465500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32542103084 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164507568584 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.053157 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.062137 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.220053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.335347 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.331594 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.293301 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1616144000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 449664000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 52753500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5939088499 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7555232499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7555232499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131965191500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32542078084 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164507269584 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.053191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.062167 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.225270 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.340628 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.332305 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.297463 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.267943 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456044 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.268527 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456354 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.947901 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.660011 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.948000 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.659754 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.205949 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.255234 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.028136 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.489319 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.205949 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.255234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.028136 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.489319 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40071.175523 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40040.969006 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40026.037736 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40069.871611 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.206152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.255458 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.053093 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.514703 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.206152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.255458 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.053093 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.514703 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40070.017108 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40041.317898 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40025.417299 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40070.495082 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -207,27 +207,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 42414340 # DTB read hits -system.cpu0.dtb.read_misses 56223 # DTB read misses -system.cpu0.dtb.write_hits 6898086 # DTB write hits -system.cpu0.dtb.write_misses 11305 # DTB write misses +system.cpu0.dtb.read_hits 42404013 # DTB read hits +system.cpu0.dtb.read_misses 55271 # DTB read misses +system.cpu0.dtb.write_hits 6896316 # DTB write hits +system.cpu0.dtb.write_misses 11117 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2713 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 11513 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 590 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 10190 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 580 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1641 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 42470563 # DTB read accesses -system.cpu0.dtb.write_accesses 6909391 # DTB write accesses +system.cpu0.dtb.perms_faults 1489 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 42459284 # DTB read accesses +system.cpu0.dtb.write_accesses 6907433 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 49312426 # DTB hits -system.cpu0.dtb.misses 67528 # DTB misses -system.cpu0.dtb.accesses 49379954 # DTB accesses -system.cpu0.itb.inst_hits 6438737 # ITB inst hits -system.cpu0.itb.inst_misses 18334 # ITB inst misses +system.cpu0.dtb.hits 49300329 # DTB hits +system.cpu0.dtb.misses 66388 # DTB misses +system.cpu0.dtb.accesses 49366717 # DTB accesses +system.cpu0.itb.inst_hits 6430047 # ITB inst hits +system.cpu0.itb.inst_misses 17344 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -236,122 +236,122 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1587 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1577 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 6092 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 5810 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6457071 # ITB inst accesses -system.cpu0.itb.hits 6438737 # DTB hits -system.cpu0.itb.misses 18334 # DTB misses -system.cpu0.itb.accesses 6457071 # DTB accesses -system.cpu0.numCycles 352502516 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6447391 # ITB inst accesses +system.cpu0.itb.hits 6430047 # DTB hits +system.cpu0.itb.misses 17344 # DTB misses +system.cpu0.itb.accesses 6447391 # DTB accesses +system.cpu0.numCycles 352464224 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 8652992 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 6404778 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 637693 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 7363134 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5053345 # Number of BTB hits +system.cpu0.BPredUnit.lookups 8639262 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 6396113 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 634960 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7354016 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5046946 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 807352 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 136692 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16884109 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45966993 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8652992 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5860697 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11522341 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2668103 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 112168 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 79167270 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 2014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 119305 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 115037 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6432455 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 291981 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 9711 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109779148 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.541337 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.795461 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 806008 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 135144 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 16864575 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45911459 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8639262 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5852954 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11507352 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2656909 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 105092 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 79183942 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 2005 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 114543 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 115021 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6424056 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 290090 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 8736 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 109741052 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.540842 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.794710 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98275003 89.52% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1141137 1.04% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1489424 1.36% 91.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1304085 1.19% 93.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1112037 1.01% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 879763 0.80% 94.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 783842 0.71% 95.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 505631 0.46% 96.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4288226 3.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98251365 89.53% 89.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 1141553 1.04% 90.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1483062 1.35% 91.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1305311 1.19% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1111109 1.01% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 877492 0.80% 94.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 783730 0.71% 95.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 504789 0.46% 96.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4282641 3.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109779148 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.024547 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.130402 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18050945 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78849390 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10366657 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 743574 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1768582 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1352275 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89418 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56923097 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 298418 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1768582 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 19113011 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33326039 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41047359 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10060323 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4463834 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54560689 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1472 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 580904 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3150021 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 227 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54846534 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 247844774 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 247794895 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 49879 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 41443860 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13402673 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 827250 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 762254 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8494444 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 11787351 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7696820 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1444181 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1562010 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51022975 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1296408 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 80307756 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 139273 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9946263 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22977035 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 252908 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109779148 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.731539 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.440195 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109741052 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.024511 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.130258 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18015904 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78867966 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10351735 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 744902 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1760545 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1349765 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89024 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56859019 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 296865 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1760545 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19077781 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 33324855 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 41068350 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10047301 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4462220 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54490886 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1483 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 580883 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 3149232 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 205 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54779836 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 247536349 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 247487579 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48770 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 41441157 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13338678 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 828868 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 763855 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8500592 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 11770384 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7686805 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1443183 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1570137 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50961906 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1297751 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 80276175 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 137636 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9888896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22816025 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 253323 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109741052 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.731505 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.440076 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 80155628 73.02% 73.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10112206 9.21% 82.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4137187 3.77% 86.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3171994 2.89% 88.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9961890 9.07% 97.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1265964 1.15% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 671041 0.61% 99.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224336 0.20% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 78902 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 80125799 73.01% 73.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10111373 9.21% 82.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4133530 3.77% 85.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3177611 2.90% 88.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 9954077 9.07% 97.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1265280 1.15% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 670333 0.61% 99.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224189 0.20% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 78860 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109779148 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109741052 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 37945 0.47% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 630 0.01% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 37808 0.47% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available @@ -379,373 +379,374 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7705227 95.96% 96.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285473 3.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 7704393 95.96% 96.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 285533 3.56% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29747563 37.04% 37.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 62367 0.08% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 4 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1707 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29731482 37.04% 37.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 62351 0.08% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1694 0.00% 37.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 37.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 43146000 53.73% 90.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7261641 9.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 43135014 53.73% 90.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 7257159 9.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 80307756 # Type of FU issued -system.cpu0.iq.rate 0.227822 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8029275 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.099981 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 278618763 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62278383 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 46688761 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11606 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7153 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5243 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 88242529 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6041 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 399833 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 80276175 # Type of FU issued +system.cpu0.iq.rate 0.227757 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8028360 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.100009 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 278513866 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62161443 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 46668616 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11568 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6980 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5172 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 88210043 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6031 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 399886 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2542386 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5153 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20600 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1003035 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2526229 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5188 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20554 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 993550 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 32220164 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13264 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 32220160 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 13300 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1768582 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25955516 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 355771 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 52493661 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 246498 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 11787351 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7696820 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 864266 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62537 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20600 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 509776 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 136927 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 646703 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 79579333 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 42855337 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 728423 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1760545 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 25952608 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 355602 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 52433539 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 243567 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 11770384 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7686805 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 865739 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62160 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5553 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20554 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 507509 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 136100 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 643609 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 79551296 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 42843907 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 724879 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 174278 # number of nop insts executed -system.cpu0.iew.exec_refs 50025973 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6436853 # Number of branches executed -system.cpu0.iew.exec_stores 7170636 # Number of stores executed -system.cpu0.iew.exec_rate 0.225755 # Inst execution rate -system.cpu0.iew.wb_sent 79157088 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 46694004 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24804627 # num instructions producing a value -system.cpu0.iew.wb_consumers 46107956 # num instructions consuming a value +system.cpu0.iew.exec_nop 173882 # number of nop insts executed +system.cpu0.iew.exec_refs 50011427 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6433542 # Number of branches executed +system.cpu0.iew.exec_stores 7167520 # Number of stores executed +system.cpu0.iew.exec_rate 0.225700 # Inst execution rate +system.cpu0.iew.wb_sent 79133798 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 46673788 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24793926 # num instructions producing a value +system.cpu0.iew.wb_consumers 46078393 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.132464 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.537968 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.132421 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.538081 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 41930270 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 10408005 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1043500 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 570177 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 108054182 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.388049 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.248702 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 41927345 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 10365163 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1044428 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 567784 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 108024119 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.388129 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.248779 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 91026362 84.24% 84.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 9315133 8.62% 92.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2453841 2.27% 95.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1345650 1.25% 96.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1029771 0.95% 97.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 653477 0.60% 97.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 658529 0.61% 98.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 238490 0.22% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1332929 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 90994296 84.24% 84.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 9318293 8.63% 92.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2453548 2.27% 95.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1344047 1.24% 96.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1036100 0.96% 97.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 648919 0.60% 97.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 654404 0.61% 98.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 241700 0.22% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1332812 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 108054182 # Number of insts commited each cycle -system.cpu0.commit.count 41930270 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 108024119 # Number of insts commited each cycle +system.cpu0.commit.count 41927345 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 15938750 # Number of memory references committed -system.cpu0.commit.loads 9244965 # Number of loads committed -system.cpu0.commit.membars 288660 # Number of memory barriers committed -system.cpu0.commit.branches 5543054 # Number of branches committed -system.cpu0.commit.fp_insts 4980 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37176133 # Number of committed integer instructions. -system.cpu0.commit.function_calls 620334 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1332929 # number cycles where commit BW limit reached +system.cpu0.commit.refs 15937410 # Number of memory references committed +system.cpu0.commit.loads 9244155 # Number of loads committed +system.cpu0.commit.membars 288635 # Number of memory barriers committed +system.cpu0.commit.branches 5542672 # Number of branches committed +system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 37173454 # Number of committed integer instructions. +system.cpu0.commit.function_calls 620264 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1332812 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 157975997 # The number of ROB reads -system.cpu0.rob.rob_writes 106454954 # The number of ROB writes -system.cpu0.timesIdled 1454281 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 242723368 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 41804443 # Number of Instructions Simulated -system.cpu0.committedInsts_total 41804443 # Number of Instructions Simulated -system.cpu0.cpi 8.432178 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.432178 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.118593 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.118593 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 354304839 # number of integer regfile reads -system.cpu0.int_regfile_writes 46156049 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4230 # number of floating regfile reads -system.cpu0.fp_regfile_writes 1342 # number of floating regfile writes -system.cpu0.misc_regfile_reads 65708495 # number of misc regfile reads -system.cpu0.misc_regfile_writes 636034 # number of misc regfile writes -system.cpu0.icache.replacements 540132 # number of replacements -system.cpu0.icache.tagsinuse 511.623908 # Cycle average of tags in use -system.cpu0.icache.total_refs 5846805 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 540644 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.814519 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 157900366 # The number of ROB reads +system.cpu0.rob.rob_writes 106355397 # The number of ROB writes +system.cpu0.timesIdled 1453890 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 242723172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 4812468828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41801518 # Number of Instructions Simulated +system.cpu0.committedInsts_total 41801518 # Number of Instructions Simulated +system.cpu0.cpi 8.431852 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.431852 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.118598 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.118598 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 354175082 # number of integer regfile reads +system.cpu0.int_regfile_writes 46137252 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4205 # number of floating regfile reads +system.cpu0.fp_regfile_writes 1348 # number of floating regfile writes +system.cpu0.misc_regfile_reads 65629786 # number of misc regfile reads +system.cpu0.misc_regfile_writes 635954 # number of misc regfile writes +system.cpu0.icache.replacements 539173 # number of replacements +system.cpu0.icache.tagsinuse 511.623608 # Cycle average of tags in use +system.cpu0.icache.total_refs 5839899 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 539685 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.820940 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 16020223000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.623908 # Average occupied blocks per context +system.cpu0.icache.occ_blocks::0 511.623608 # Average occupied blocks per context system.cpu0.icache.occ_percent::0 0.999265 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 5846805 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5846805 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 5846805 # number of demand (read+write) hits +system.cpu0.icache.ReadReq_hits::0 5839899 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5839899 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5839899 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5846805 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 5846805 # number of overall hits +system.cpu0.icache.demand_hits::total 5839899 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5839899 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5846805 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 585522 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 585522 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 585522 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 5839899 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 584029 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 584029 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 584029 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 585522 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 585522 # number of overall misses +system.cpu0.icache.demand_misses::total 584029 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 584029 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 585522 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 8762208993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 8762208993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 8762208993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 6432327 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6432327 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 6432327 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 584029 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 8742056490 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 8742056490 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 8742056490 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 6423928 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6423928 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 6423928 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6432327 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 6432327 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 6423928 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 6423928 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6432327 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.091028 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.091028 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 6423928 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.090915 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.090915 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.091028 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.090915 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14964.781841 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14968.531511 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14964.781841 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14968.531511 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14964.781841 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14968.531511 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1480495 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1586493 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 196 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 210 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7553.545918 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7554.728571 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 29912 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 44859 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 44859 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 44859 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 540663 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 540663 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 540663 # number of overall MSHR misses +system.cpu0.icache.writebacks 29902 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 44323 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 44323 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 44323 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 539706 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 539706 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 539706 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 6562850995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 6562850995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 6562850995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 6552393493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 6552393493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 6552393493 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084054 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084015 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.084054 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.084015 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.084054 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.084015 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.524358 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12140.671945 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 372646 # number of replacements -system.cpu0.dcache.tagsinuse 487.071508 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12784845 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 373158 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.261211 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 372215 # number of replacements +system.cpu0.dcache.tagsinuse 487.071305 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12774859 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 372727 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.274037 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 487.071508 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.951312 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7969031 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7969031 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 4348200 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4348200 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 221332 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 221332 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 199760 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199760 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12317231 # number of demand (read+write) hits +system.cpu0.dcache.occ_blocks::0 487.071305 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.951311 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::0 7959466 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7959466 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 4347928 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4347928 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 221270 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 221270 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 199751 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199751 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 12307394 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12317231 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12317231 # number of overall hits +system.cpu0.dcache.demand_hits::total 12307394 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 12307394 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 12317231 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 463423 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 463423 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1863605 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1863605 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9962 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9962 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7780 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 2327028 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 12307394 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 462880 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 462880 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1863380 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1863380 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 9956 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9956 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 7770 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7770 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 2326260 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2327028 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 2327028 # number of overall misses +system.cpu0.dcache.demand_misses::total 2326260 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 2326260 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2327028 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 6461559500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 70508741836 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 120808500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 88519000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 76970301336 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 76970301336 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8432454 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8432454 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6211805 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6211805 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 231294 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 231294 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 207540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 207540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14644259 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 2326260 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 6451753000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 70471171342 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 120838000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 88450500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 76922924342 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 76922924342 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8422346 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8422346 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 6211308 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6211308 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 231226 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 231226 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 207521 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 207521 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14633654 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14644259 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14644259 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14633654 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14633654 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14644259 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.054957 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.300010 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043071 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037487 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.158904 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14633654 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.054959 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.299998 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043057 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037442 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.158966 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.158904 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.158966 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 13943.113527 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 13938.284221 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37834.595763 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 37819.001675 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12126.932343 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12137.203696 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11377.763496 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11383.590734 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 33076.654572 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 33067.208456 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 33076.654572 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 33067.208456 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6713488 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1808000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 859 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 6759989 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1802000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 868 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 123 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7815.469150 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 14699.186992 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7788.005760 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 14650.406504 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 327128 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 223214 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1685177 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 329 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1908391 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1908391 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 240209 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 178428 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7778 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 418637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 418637 # number of overall MSHR misses +system.cpu0.dcache.writebacks 326934 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 223096 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1684995 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1908091 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1908091 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 239784 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 178385 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9630 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 7769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 418169 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 418169 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2943893000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6377983487 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86869500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9321876487 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9321876487 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959490000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038770484 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 139998260484 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028486 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 2937322500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6377417488 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86877000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65112500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 9314739988 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 9314739988 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959379000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038732984 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 139998111984 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028719 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041648 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037477 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037437 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028587 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.028576 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028587 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.028576 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12255.548293 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35745.418247 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9017.907194 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8376.832091 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12249.868632 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35750.861833 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9021.495327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8381.065774 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -754,27 +755,27 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10576986 # DTB read hits -system.cpu1.dtb.read_misses 41991 # DTB read misses -system.cpu1.dtb.write_hits 5532460 # DTB write hits -system.cpu1.dtb.write_misses 15559 # DTB write misses +system.cpu1.dtb.read_hits 10573739 # DTB read hits +system.cpu1.dtb.read_misses 42015 # DTB read misses +system.cpu1.dtb.write_hits 5529871 # DTB write hits +system.cpu1.dtb.write_misses 15191 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 5132 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1927 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3403 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 787 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10618977 # DTB read accesses -system.cpu1.dtb.write_accesses 5548019 # DTB write accesses +system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10615754 # DTB read accesses +system.cpu1.dtb.write_accesses 5545062 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16109446 # DTB hits -system.cpu1.dtb.misses 57550 # DTB misses -system.cpu1.dtb.accesses 16166996 # DTB accesses -system.cpu1.itb.inst_hits 8208666 # ITB inst hits -system.cpu1.itb.inst_misses 3757 # ITB inst misses +system.cpu1.dtb.hits 16103610 # DTB hits +system.cpu1.dtb.misses 57206 # DTB misses +system.cpu1.dtb.accesses 16160816 # DTB accesses +system.cpu1.itb.inst_hits 8206065 # ITB inst hits +system.cpu1.itb.inst_misses 3031 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -783,122 +784,122 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1367 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2255 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2156 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8212423 # ITB inst accesses -system.cpu1.itb.hits 8208666 # DTB hits -system.cpu1.itb.misses 3757 # DTB misses -system.cpu1.itb.accesses 8212423 # DTB accesses -system.cpu1.numCycles 69081256 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8209096 # ITB inst accesses +system.cpu1.itb.hits 8206065 # DTB hits +system.cpu1.itb.misses 3031 # DTB misses +system.cpu1.itb.accesses 8209096 # DTB accesses +system.cpu1.numCycles 69056369 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 8330796 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6738871 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 503522 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7267639 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5704343 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8325282 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 6737041 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 502555 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7261407 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5699060 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 683793 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 107847 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 17620797 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62561411 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8330796 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6388136 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13917594 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4639299 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 49548 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 15790396 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 3022 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 34407 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 125274 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 237 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8206050 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 760093 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2394 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 50674659 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.494403 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.744832 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 682916 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 107380 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 17608500 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 62544782 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8325282 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6381976 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13909998 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4633998 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 45331 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 15806576 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 3075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 32937 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 125179 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8203545 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 759342 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1683 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 50660963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.494360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.745003 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 36764920 72.55% 72.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 704096 1.39% 73.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1222881 2.41% 76.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2516311 4.97% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1142608 2.25% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 651052 1.28% 84.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1887369 3.72% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 403735 0.80% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5381687 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 36758800 72.56% 72.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 702781 1.39% 73.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1220162 2.41% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2515175 4.96% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1141377 2.25% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 650709 1.28% 84.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1886656 3.72% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 404310 0.80% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5380993 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 50674659 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.120594 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.905621 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18672830 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16053118 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12511393 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 382905 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3054413 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1082178 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 80433 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69756936 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 260341 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3054413 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19817710 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3624621 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 10850261 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11740016 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1587638 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63840108 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3002 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 319994 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 862075 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 38212 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 68266339 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 296265404 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 296212618 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52786 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39108942 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29157397 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 433648 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 381432 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4194062 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11085935 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7020391 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 635108 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 890373 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 56044948 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 651331 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 50360925 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 120514 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18223761 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52593424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 131996 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 50674659 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.993809 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.617399 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 50660963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.120558 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.905706 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18651451 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16071797 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12503703 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 383683 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3050329 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1080503 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 80301 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69737045 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 259727 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3050329 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 19796555 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3624603 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 10867059 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11733074 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1589343 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 63809564 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2981 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 320281 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 864112 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 38202 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 68239803 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 296124940 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 296072200 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52740 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39106608 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29133195 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 434621 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 382462 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4203927 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11080202 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7013216 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 634211 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 885799 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 56015216 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 652114 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 50333331 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 120412 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18201885 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52559759 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 132486 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 50660963 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.993533 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.617126 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 32153473 63.45% 63.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5526378 10.91% 74.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3775422 7.45% 81.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3611274 7.13% 88.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2989508 5.90% 94.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1557590 3.07% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 784960 1.55% 99.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 214293 0.42% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61761 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 32144545 63.45% 63.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5530112 10.92% 74.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3775848 7.45% 81.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3605586 7.12% 88.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2986827 5.90% 94.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1557942 3.08% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 784538 1.55% 99.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 214001 0.42% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61564 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 50674659 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 50660963 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 15522 1.51% 1.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1191 0.12% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 15475 1.52% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1190 0.12% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available @@ -926,373 +927,374 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 749386 73.14% 74.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 258502 25.23% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 748820 73.38% 75.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 254917 24.98% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32758484 65.05% 65.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 50347 0.10% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 759 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32741822 65.05% 65.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 50334 0.10% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.19% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.19% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 65.19% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11614499 23.06% 88.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5918207 11.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11609954 23.07% 88.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5911828 11.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 50360925 # Type of FU issued -system.cpu1.iq.rate 0.729010 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1024601 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020345 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 152586143 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 74924785 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 44270347 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12757 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7087 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5824 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 51360226 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6678 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 266055 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 50333331 # Type of FU issued +system.cpu1.iq.rate 0.728873 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1020402 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020273 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 152512648 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 74873900 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 44249478 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12744 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7082 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5800 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 51328452 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6659 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 264599 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3973405 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7375 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 12287 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1481060 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3968304 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7379 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 12210 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1474293 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1850150 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1139659 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 1850149 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1139663 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3054413 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2505400 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 71046 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56747555 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 255776 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11085935 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7020391 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 408110 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28416 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3434 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 12287 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 384769 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 125659 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 510428 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 47569274 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10848117 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2791651 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3050329 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2505738 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 70750 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 56718238 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 255272 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 11080202 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7013216 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 408861 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28043 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3317 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 12210 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 383709 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 125709 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 509418 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 47546383 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10844490 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2786948 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 51276 # number of nop insts executed -system.cpu1.iew.exec_refs 16673626 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5809146 # Number of branches executed -system.cpu1.iew.exec_stores 5825509 # Number of stores executed -system.cpu1.iew.exec_rate 0.688599 # Inst execution rate -system.cpu1.iew.wb_sent 46311223 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 44276171 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24275566 # num instructions producing a value -system.cpu1.iew.wb_consumers 44463888 # num instructions consuming a value +system.cpu1.iew.exec_nop 50908 # number of nop insts executed +system.cpu1.iew.exec_refs 16665607 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5805305 # Number of branches executed +system.cpu1.iew.exec_stores 5821117 # Number of stores executed +system.cpu1.iew.exec_rate 0.688516 # Inst execution rate +system.cpu1.iew.wb_sent 46287732 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 44255278 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24264943 # num instructions producing a value +system.cpu1.iew.wb_consumers 44435618 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.640929 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545961 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.640857 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.546070 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38087596 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18562736 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 519335 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 450588 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 47661477 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.799127 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.835707 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38085105 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18540440 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 519628 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 449695 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 47651856 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.799237 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835547 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 34693281 72.79% 72.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6099066 12.80% 85.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1834262 3.85% 89.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 962147 2.02% 91.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 825706 1.73% 93.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 739217 1.55% 94.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 588574 1.23% 95.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 450580 0.95% 96.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1468644 3.08% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 34686600 72.79% 72.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6094128 12.79% 85.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1835097 3.85% 89.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 960943 2.02% 91.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 825753 1.73% 93.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 740854 1.55% 94.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 593786 1.25% 95.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 449604 0.94% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1465091 3.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 47661477 # Number of insts commited each cycle -system.cpu1.commit.count 38087596 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 47651856 # Number of insts commited each cycle +system.cpu1.commit.count 38085105 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 12651861 # Number of memory references committed -system.cpu1.commit.loads 7112530 # Number of loads committed -system.cpu1.commit.membars 148745 # Number of memory barriers committed -system.cpu1.commit.branches 4804762 # Number of branches committed +system.cpu1.commit.refs 12650821 # Number of memory references committed +system.cpu1.commit.loads 7111898 # Number of loads committed +system.cpu1.commit.membars 148710 # Number of memory barriers committed +system.cpu1.commit.branches 4804442 # Number of branches committed system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34029989 # Number of committed integer instructions. -system.cpu1.commit.function_calls 433336 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1468644 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 34027730 # Number of committed integer instructions. +system.cpu1.commit.function_calls 433273 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1465091 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 102084600 # The number of ROB reads -system.cpu1.rob.rob_writes 116474424 # The number of ROB writes -system.cpu1.timesIdled 450576 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18406597 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 38063042 # Number of Instructions Simulated -system.cpu1.committedInsts_total 38063042 # Number of Instructions Simulated -system.cpu1.cpi 1.814917 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.814917 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550989 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550989 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 222881114 # number of integer regfile reads -system.cpu1.int_regfile_writes 47167594 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4241 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1808 # number of floating regfile writes -system.cpu1.misc_regfile_reads 77248425 # number of misc regfile reads -system.cpu1.misc_regfile_writes 323332 # number of misc regfile writes -system.cpu1.icache.replacements 486491 # number of replacements -system.cpu1.icache.tagsinuse 498.789046 # Cycle average of tags in use -system.cpu1.icache.total_refs 7677673 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 487003 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 15.765145 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 102053926 # The number of ROB reads +system.cpu1.rob.rob_writes 116420763 # The number of ROB writes +system.cpu1.timesIdled 449905 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18395406 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5095165422 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38060551 # Number of Instructions Simulated +system.cpu1.committedInsts_total 38060551 # Number of Instructions Simulated +system.cpu1.cpi 1.814382 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.814382 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551152 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551152 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 222777169 # number of integer regfile reads +system.cpu1.int_regfile_writes 47147395 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4225 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1812 # number of floating regfile writes +system.cpu1.misc_regfile_reads 77230796 # number of misc regfile reads +system.cpu1.misc_regfile_writes 323252 # number of misc regfile writes +system.cpu1.icache.replacements 485904 # number of replacements +system.cpu1.icache.tagsinuse 498.788757 # Cycle average of tags in use +system.cpu1.icache.total_refs 7675789 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 486416 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 15.780297 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74237229000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.789046 # Average occupied blocks per context +system.cpu1.icache.occ_blocks::0 498.788757 # Average occupied blocks per context system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7677673 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7677673 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7677673 # number of demand (read+write) hits +system.cpu1.icache.ReadReq_hits::0 7675789 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7675789 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 7675789 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7677673 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7677673 # number of overall hits +system.cpu1.icache.demand_hits::total 7675789 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 7675789 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 7677673 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 528325 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 528325 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 528325 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 7675789 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 527703 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 527703 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 527703 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 528325 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 528325 # number of overall misses +system.cpu1.icache.demand_misses::total 527703 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 527703 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 528325 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7771273996 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7771273996 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7771273996 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 8205998 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8205998 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 8205998 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 527703 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7760328997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7760328997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7760328997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 8203492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8203492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 8203492 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8205998 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 8205998 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 8203492 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 8203492 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8205998 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.064383 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.064383 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 8203492 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.064327 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.064327 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.064383 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.064327 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14709.267962 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 14705.864846 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14709.267962 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14705.864846 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14709.267962 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14705.864846 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1184497 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 1243497 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 157 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7544.566879 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7446.089820 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 18578 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 41295 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 41295 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 41295 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 487030 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 487030 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 487030 # number of overall MSHR misses +system.cpu1.icache.writebacks 18536 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 41257 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 41257 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 41257 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 486446 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 486446 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 486446 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5811540497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5811540497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5811540497 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5802515997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5802515997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5802515997 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059350 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059297 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.059350 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.059297 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.059350 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.059297 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11932.612975 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11928.386701 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 272380 # number of replacements -system.cpu1.dcache.tagsinuse 444.916025 # Cycle average of tags in use -system.cpu1.dcache.total_refs 10412119 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 272723 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 38.178368 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 272184 # number of replacements +system.cpu1.dcache.tagsinuse 444.922817 # Cycle average of tags in use +system.cpu1.dcache.total_refs 10410516 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 272526 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 38.200084 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 66749899000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 444.916025 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.868977 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 7081898 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7081898 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3139500 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3139500 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 75302 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75302 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 72598 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72598 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 10221398 # number of demand (read+write) hits +system.cpu1.dcache.occ_blocks::0 444.922817 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.868990 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 7080702 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7080702 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 3139041 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3139041 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 75297 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 75297 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 72589 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72589 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 10219743 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10221398 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 10221398 # number of overall hits +system.cpu1.dcache.demand_hits::total 10219743 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 10219743 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 10221398 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 324241 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 324241 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 1274343 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1274343 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 12700 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12700 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 11096 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 11096 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 1598584 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 10219743 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 323641 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 323641 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 1274421 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1274421 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 12692 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 12692 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 11088 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 11088 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 1598062 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1598584 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 1598584 # number of overall misses +system.cpu1.dcache.demand_misses::total 1598062 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 1598062 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1598584 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 5065302500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 46249656862 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 148116500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 88362500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 51314959362 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 51314959362 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 7406139 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7406139 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 4413843 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4413843 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 88002 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 88002 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 83694 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83694 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11819982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 1598062 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 5056918000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 46262292366 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 147873000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 87994000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 51319210366 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 51319210366 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 7404343 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7404343 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 4413462 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4413462 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 87989 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87989 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 83677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 11817805 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11819982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11819982 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11817805 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 11817805 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11819982 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.043780 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.288715 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144315 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132578 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.135244 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 11817805 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.043710 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.288758 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144245 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132510 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.135225 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.135244 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.135225 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15622.029601 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15625.084584 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36292.942216 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 36300.635635 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11662.716535 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11650.882446 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7963.455299 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7935.966811 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32100.258330 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 32113.403839 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32100.258330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 32113.403839 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 13378551 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5449500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3082 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4340.866645 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34710.191083 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 13353050 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5461500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3087 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4325.574992 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34134.375000 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 223500 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 134561 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1158019 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 988 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1292580 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1292580 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 189680 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 116324 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11712 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 11095 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 306004 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 306004 # number of overall MSHR misses +system.cpu1.dcache.writebacks 223414 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 134188 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 1158095 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 989 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 1292283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 1292283 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 189453 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 116326 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 11703 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 11087 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 305779 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 305779 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2497244500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3447430551 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 55002000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5944675051 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5944675051 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455396000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503639517 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49959035517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025611 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2493574500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 3446976050 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 98971000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54655500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 5940550550 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 5940550550 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455171000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503599517 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 49958770517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025587 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026357 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133088 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133005 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132566 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132498 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.025889 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.025874 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.025889 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.025874 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13165.565690 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29636.451214 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8468.280396 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4957.368184 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13161.968932 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29632.034541 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8456.891395 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4929.692433 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1353,8 +1355,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308164389827 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308164389827 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1308164258694 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1308164258694 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -1369,8 +1371,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 55750 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 55740 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 41971 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 41953 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 79ce98ed4..b9ffca20c 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index b45c8117b..61a472c55 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout -Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:41:18 -gem5 started Aug 20 2011 15:46:02 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:32:34 +gem5 started Nov 22 2011 02:00:08 +gem5 executing on u200540-lin command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503587516500 because m5_exit instruction encountered +Exiting @ tick 2503566110500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ae3ccdd2b..b782cd5c8 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503588 # Number of seconds simulated -sim_ticks 2503587516500 # Number of ticks simulated +sim_seconds 2.503566 # Number of seconds simulated +sim_ticks 2503566110500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84198 # Simulator instruction rate (inst/s) -host_tick_rate 2745069755 # Simulator tick rate (ticks/s) -host_mem_usage 385208 # Number of bytes of host memory used -host_seconds 912.03 # Real time elapsed on the host -sim_insts 76790714 # Number of instructions simulated -system.l2c.replacements 119531 # number of replacements -system.l2c.tagsinuse 25929.939584 # Cycle average of tags in use -system.l2c.total_refs 1799445 # Total number of references to valid blocks. -system.l2c.sampled_refs 150368 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.966941 # Average number of references to valid blocks. +host_inst_rate 84156 # Simulator instruction rate (inst/s) +host_tick_rate 2743719152 # Simulator tick rate (ticks/s) +host_mem_usage 380536 # Number of bytes of host memory used +host_seconds 912.47 # Real time elapsed on the host +sim_insts 76790007 # Number of instructions simulated +system.l2c.replacements 119509 # number of replacements +system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use +system.l2c.total_refs 1795434 # Total number of references to valid blocks. +system.l2c.sampled_refs 150343 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.942252 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11550.967581 # Average occupied blocks per context -system.l2c.occ_blocks::1 14378.972003 # Average occupied blocks per context -system.l2c.occ_percent::0 0.176254 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219406 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1351962 # number of ReadReq hits -system.l2c.ReadReq_hits::1 155464 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1507426 # number of ReadReq hits -system.l2c.Writeback_hits::0 630774 # number of Writeback hits -system.l2c.Writeback_hits::total 630774 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105933 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105933 # number of ReadExReq hits -system.l2c.demand_hits::0 1457895 # number of demand (read+write) hits -system.l2c.demand_hits::1 155464 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613359 # number of demand (read+write) hits -system.l2c.overall_hits::0 1457895 # number of overall hits -system.l2c.overall_hits::1 155464 # number of overall hits -system.l2c.overall_hits::total 1613359 # number of overall hits -system.l2c.ReadReq_misses::0 36117 # number of ReadReq misses -system.l2c.ReadReq_misses::1 148 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36265 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3244 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3244 # number of UpgradeReq misses +system.l2c.occ_blocks::0 11551.232252 # Average occupied blocks per context +system.l2c.occ_blocks::1 14378.665001 # Average occupied blocks per context +system.l2c.occ_percent::0 0.176258 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.219401 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1350292 # number of ReadReq hits +system.l2c.ReadReq_hits::1 153003 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1503295 # number of ReadReq hits +system.l2c.Writeback_hits::0 629881 # number of Writeback hits +system.l2c.Writeback_hits::total 629881 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 16 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 105934 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105934 # number of ReadExReq hits +system.l2c.demand_hits::0 1456226 # number of demand (read+write) hits +system.l2c.demand_hits::1 153003 # number of demand (read+write) hits +system.l2c.demand_hits::total 1609229 # number of demand (read+write) hits +system.l2c.overall_hits::0 1456226 # number of overall hits +system.l2c.overall_hits::1 153003 # number of overall hits +system.l2c.overall_hits::total 1609229 # number of overall hits +system.l2c.ReadReq_misses::0 36080 # number of ReadReq misses +system.l2c.ReadReq_misses::1 144 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36224 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3255 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3255 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140419 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140419 # number of ReadExReq misses -system.l2c.demand_misses::0 176536 # number of demand (read+write) misses -system.l2c.demand_misses::1 148 # number of demand (read+write) misses -system.l2c.demand_misses::total 176684 # number of demand (read+write) misses -system.l2c.overall_misses::0 176536 # number of overall misses -system.l2c.overall_misses::1 148 # number of overall misses -system.l2c.overall_misses::total 176684 # number of overall misses -system.l2c.ReadReq_miss_latency 1896887000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 953000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7384203500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9281090500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9281090500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1388079 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 155612 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1543691 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 630774 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 630774 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3286 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246352 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246352 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1634431 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 155612 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1790043 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1634431 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 155612 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1790043 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026019 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000951 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026970 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.987219 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.105263 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569993 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.108011 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000951 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108962 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.108011 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000951 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108962 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52520.613561 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12816804.054054 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12869324.667616 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 293.773120 # average UpgradeReq miss latency +system.l2c.ReadExReq_misses::0 140433 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140433 # number of ReadExReq misses +system.l2c.demand_misses::0 176513 # number of demand (read+write) misses +system.l2c.demand_misses::1 144 # number of demand (read+write) misses +system.l2c.demand_misses::total 176657 # number of demand (read+write) misses +system.l2c.overall_misses::0 176513 # number of overall misses +system.l2c.overall_misses::1 144 # number of overall misses +system.l2c.overall_misses::total 176657 # number of overall misses +system.l2c.ReadReq_miss_latency 1894696500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 1006500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7384268500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9278965000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9278965000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1386372 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 153147 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1539519 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 629881 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 629881 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 3293 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3293 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1632739 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 153147 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1785886 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1632739 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 153147 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1785886 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026025 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000940 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.026965 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.988460 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.111111 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.570015 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.108109 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000940 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109049 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.108109 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000940 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109049 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52513.761086 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 13157614.583333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 13210128.344420 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 309.216590 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52586.925559 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52582.145934 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52573.358975 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 62710070.945946 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 62762644.304921 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52573.358975 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 62710070.945946 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 62762644.304921 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52568.167784 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 64437256.944444 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 64489825.112228 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52568.167784 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 64437256.944444 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 64489825.112228 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,50 +107,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102665 # number of writebacks -system.l2c.ReadReq_mshr_hits 95 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 95 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 95 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36170 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3244 # number of UpgradeReq MSHR misses +system.l2c.writebacks 102655 # number of writebacks +system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 94 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 36130 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3255 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140419 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176589 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176589 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_misses 140433 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 176563 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 176563 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1451509500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 130965000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency 1449837500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 131527500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5640198500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7091708000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7091708000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131769561500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32342663570 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164112225070 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026058 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.232437 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.258495 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.987219 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_latency 5640075000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7089912500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7089912500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131769527500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32342636570 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164112164070 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.235917 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.261978 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.988460 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.105263 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.111111 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569993 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.570015 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.108043 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.134803 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.242846 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.108043 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.134803 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.242846 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40130.204589 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40371.454994 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.108139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.152899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.261038 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.108139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.152899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.261038 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40128.355937 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40407.834101 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40166.918295 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40162.034565 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -165,27 +165,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52225825 # DTB read hits -system.cpu.dtb.read_misses 89986 # DTB read misses -system.cpu.dtb.write_hits 11975736 # DTB write hits -system.cpu.dtb.write_misses 26350 # DTB write misses +system.cpu.dtb.read_hits 52217329 # DTB read hits +system.cpu.dtb.read_misses 90306 # DTB read misses +system.cpu.dtb.write_hits 11974176 # DTB write hits +system.cpu.dtb.write_misses 25588 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4338 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 8018 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 617 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5563 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 685 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2450 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52315811 # DTB read accesses -system.cpu.dtb.write_accesses 12002086 # DTB write accesses +system.cpu.dtb.perms_faults 2233 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52307635 # DTB read accesses +system.cpu.dtb.write_accesses 11999764 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64201561 # DTB hits -system.cpu.dtb.misses 116336 # DTB misses -system.cpu.dtb.accesses 64317897 # DTB accesses -system.cpu.itb.inst_hits 14135631 # ITB inst hits -system.cpu.itb.inst_misses 11185 # ITB inst misses +system.cpu.dtb.hits 64191505 # DTB hits +system.cpu.dtb.misses 115894 # DTB misses +system.cpu.dtb.accesses 64307399 # DTB accesses +system.cpu.itb.inst_hits 14124795 # ITB inst hits +system.cpu.itb.inst_misses 9853 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -194,516 +194,517 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2607 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2606 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8440 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 7868 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14146816 # ITB inst accesses -system.cpu.itb.hits 14135631 # DTB hits -system.cpu.itb.misses 11185 # DTB misses -system.cpu.itb.accesses 14146816 # DTB accesses -system.cpu.numCycles 415920995 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 14134648 # ITB inst accesses +system.cpu.itb.hits 14124795 # DTB hits +system.cpu.itb.misses 9853 # DTB misses +system.cpu.itb.accesses 14134648 # DTB accesses +system.cpu.numCycles 415912091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16219215 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12559944 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1110172 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13927920 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10224432 # Number of BTB hits +system.cpu.BPredUnit.lookups 16206323 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12554772 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1108177 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13916811 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 10226428 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1424516 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 228409 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32955891 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104818490 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16219215 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11648948 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24471055 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7079806 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 137198 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92799321 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 151217 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217200 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 351 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14126420 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1047323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6165 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155547085 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.838560 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.184344 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1423283 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 227054 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32931583 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104747250 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16206323 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11649711 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24460631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7066944 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 130925 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92852979 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 144764 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217141 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14116150 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1044696 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4826 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155542524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.838034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.183637 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131101786 84.28% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1736791 1.12% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2601051 1.67% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3653656 2.35% 89.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2169863 1.39% 90.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1434892 0.92% 91.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2627328 1.69% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 855909 0.55% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9365809 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131107701 84.29% 84.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1736645 1.12% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2606210 1.68% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3650547 2.35% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2167045 1.39% 90.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1435515 0.92% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2626627 1.69% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 854151 0.55% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9358083 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155547085 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038996 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.252015 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35186802 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92649693 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21977926 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1094000 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4638664 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2316854 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 177884 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122073457 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 575981 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4638664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37340555 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36816085 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49864787 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20912628 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5974366 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 113922984 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4414 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 914987 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3980816 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42327 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118460665 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 523781573 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 523685374 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 96199 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77493785 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40966879 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1201529 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1095575 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12285551 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 22000628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14180796 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1905529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2295702 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102943309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1872075 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126931651 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 252428 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27053062 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73124308 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 373806 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155547085 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816034 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505599 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155542524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038966 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.251849 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35137982 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92713675 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21969277 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1093477 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4628113 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2313056 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 177631 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 122001156 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 574106 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4628113 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37294552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36817406 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49929047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20901153 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5972253 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 113826701 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4400 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 118358542 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 40865823 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21982315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102860212 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1874615 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126873317 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 374922 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108904431 70.01% 70.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15118772 9.72% 79.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7542016 4.85% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6525767 4.20% 88.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12768009 8.21% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2736654 1.76% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1396269 0.90% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 422710 0.27% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132457 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108919716 70.03% 70.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12766128 8.21% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2735747 1.76% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155547085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155542524 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45562 0.51% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8415938 94.58% 95.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 436851 4.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45891 0.52% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8417784 94.58% 95.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 436630 4.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60109955 47.36% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96551 0.08% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2253 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53954328 42.51% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12662017 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60069483 47.35% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2251 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53942685 42.52% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126931651 # Type of FU issued -system.cpu.iq.rate 0.305182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8898356 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070104 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 418652883 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131886553 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87334534 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23945 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10473 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135710724 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12753 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 616189 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126873317 # Type of FU issued +system.cpu.iq.rate 0.305048 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 418533130 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87292109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 135654306 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6319666 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11234 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32604 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2401616 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6301517 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32657 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2389653 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34061863 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1153574 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34061869 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1153605 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4638664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28343669 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 418971 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 105030898 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 476967 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 22000628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14180796 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1225085 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 85041 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7449 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32604 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 851635 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 257956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109591 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123477395 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52923959 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3454256 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4628113 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28345943 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 419499 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 104949442 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1228030 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123429780 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 215514 # number of nop insts executed -system.cpu.iew.exec_refs 65415175 # number of memory reference insts executed -system.cpu.iew.exec_branches 11714146 # Number of branches executed -system.cpu.iew.exec_stores 12491216 # Number of stores executed -system.cpu.iew.exec_rate 0.296877 # Inst execution rate -system.cpu.iew.wb_sent 121817988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87345007 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47064551 # num instructions producing a value -system.cpu.iew.wb_consumers 86684992 # num instructions consuming a value +system.cpu.iew.exec_nop 214615 # number of nop insts executed +system.cpu.iew.exec_refs 65401525 # number of memory reference insts executed +system.cpu.iew.exec_branches 11705842 # Number of branches executed +system.cpu.iew.exec_stores 12487221 # Number of stores executed +system.cpu.iew.exec_rate 0.296769 # Inst execution rate +system.cpu.iew.wb_sent 121771134 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87302555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47043389 # num instructions producing a value +system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210004 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.542938 # average fanout of values written-back +system.cpu.iew.wb_rate 0.209906 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.542984 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76941095 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27854412 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1498269 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 978817 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 150990773 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.509575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459429 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 76940388 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27793277 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499693 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 977065 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150996763 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.509550 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459324 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122133629 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14849154 9.83% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4108732 2.72% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2181203 1.44% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1788420 1.18% 96.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1359682 0.90% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1260703 0.83% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 659440 0.44% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2649810 1.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122144480 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14839804 9.83% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4110999 2.72% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2181780 1.44% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1788910 1.18% 96.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1360879 0.90% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1262027 0.84% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 662023 0.44% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2645861 1.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 150990773 # Number of insts commited each cycle -system.cpu.commit.count 76941095 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 150996763 # Number of insts commited each cycle +system.cpu.commit.count 76940388 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27460142 # Number of memory references committed -system.cpu.commit.loads 15680962 # Number of loads committed +system.cpu.commit.refs 27459875 # Number of memory references committed +system.cpu.commit.loads 15680798 # Number of loads committed system.cpu.commit.membars 413062 # Number of memory barriers committed -system.cpu.commit.branches 9891108 # Number of branches committed +system.cpu.commit.branches 9891038 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68494112 # Number of committed integer instructions. +system.cpu.commit.int_insts 68493475 # Number of committed integer instructions. system.cpu.commit.function_calls 995603 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2649810 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2645861 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 251379971 # The number of ROB reads -system.cpu.rob.rob_writes 214361160 # The number of ROB writes -system.cpu.timesIdled 1877573 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260373910 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 76790714 # Number of Instructions Simulated -system.cpu.committedInsts_total 76790714 # Number of Instructions Simulated -system.cpu.cpi 5.416293 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.416293 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184628 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184628 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 559837261 # number of integer regfile reads -system.cpu.int_regfile_writes 89743570 # number of integer regfile writes -system.cpu.fp_regfile_reads 8283 # number of floating regfile reads -system.cpu.fp_regfile_writes 2809 # number of floating regfile writes -system.cpu.misc_regfile_reads 137364406 # number of misc regfile reads -system.cpu.misc_regfile_writes 912286 # number of misc regfile writes -system.cpu.icache.replacements 993006 # number of replacements -system.cpu.icache.tagsinuse 511.614815 # Cycle average of tags in use -system.cpu.icache.total_refs 13045370 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 993518 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.130482 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 251328068 # The number of ROB reads +system.cpu.rob.rob_writes 214226863 # The number of ROB writes +system.cpu.timesIdled 1877486 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260369567 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591132146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 76790007 # Number of Instructions Simulated +system.cpu.committedInsts_total 76790007 # Number of Instructions Simulated +system.cpu.cpi 5.416227 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads +system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 559625789 # number of integer regfile reads +system.cpu.int_regfile_writes 89694790 # number of integer regfile writes +system.cpu.fp_regfile_reads 8322 # number of floating regfile reads +system.cpu.fp_regfile_writes 2832 # number of floating regfile writes +system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads +system.cpu.misc_regfile_writes 912282 # number of misc regfile writes +system.cpu.icache.replacements 991618 # number of replacements +system.cpu.icache.tagsinuse 511.615309 # Cycle average of tags in use +system.cpu.icache.total_refs 13036767 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992130 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.140180 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.614815 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999248 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13045370 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13045370 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13045370 # number of demand (read+write) hits +system.cpu.icache.occ_blocks::0 511.615309 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 13036767 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13036767 # number of ReadReq hits +system.cpu.icache.demand_hits::0 13036767 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13045370 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13045370 # number of overall hits +system.cpu.icache.demand_hits::total 13036767 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 13036767 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 13045370 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1080929 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1080929 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1080929 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 13036767 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1079261 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079261 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1079261 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1080929 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1080929 # number of overall misses +system.cpu.icache.demand_misses::total 1079261 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1079261 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1080929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15935046488 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15935046488 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15935046488 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14126299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14126299 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1079261 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15910722989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15910722989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15910722989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 14116028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14116028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 14116028 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126299 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14126299 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 14116028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 14116028 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126299 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.076519 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.076519 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 14116028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.076456 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.076456 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.076519 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.076456 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14741.991831 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14742.238429 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14741.991831 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14742.238429 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14741.991831 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14742.238429 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2385493 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2475992 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 357 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 368 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6682.053221 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6728.239130 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57770 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 87373 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 87373 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 87373 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 993556 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 993556 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 993556 # number of overall MSHR misses +system.cpu.icache.writebacks 57161 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 87101 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 87101 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 87101 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 992160 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 992160 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 992160 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11874405493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11874405493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11874405493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11856676492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11856676492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11856676492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070334 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070286 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.070334 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.070286 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.070334 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.070286 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11951.420446 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11950.367372 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644346 # number of replacements +system.cpu.dcache.replacements 643915 # number of replacements system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use -system.cpu.dcache.total_refs 22273031 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644858 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.539435 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 22265831 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644427 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.551363 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14419247 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14419247 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7264920 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264920 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 299971 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 299971 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285485 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285485 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21684167 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 14412375 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14412375 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 7264610 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7264610 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 299966 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 299966 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 285484 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285484 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 21676985 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21684167 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21684167 # number of overall hits +system.cpu.dcache.demand_hits::total 21676985 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 21676985 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 21684167 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 724263 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 724263 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2966438 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966438 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13488 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13488 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3690701 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 21676985 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 724119 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 724119 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2966647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966647 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 13487 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13487 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 18 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 3690766 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3690701 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3690701 # number of overall misses +system.cpu.dcache.demand_misses::total 3690766 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3690766 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3690701 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10889184500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110353624242 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 218944000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 357000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 121242808742 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121242808742 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 15143510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 15143510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10231358 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10231358 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 313459 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 313459 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 285504 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285504 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 25374868 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 3690766 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 10885048500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110351571736 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 219032000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 343000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 121236620236 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 121236620236 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 15136494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 15136494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10231257 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231257 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 313453 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 313453 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 285502 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285502 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 25367751 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25374868 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25374868 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 25367751 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 25367751 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25374868 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047827 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043030 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.145447 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 25367751 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.047839 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.289959 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000063 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.145490 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.145447 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.145490 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15034.848529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15032.126626 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37200.718249 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 37197.405602 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16232.502966 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16240.231334 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 18789.473684 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 19055.555556 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32850.888962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 32848.633654 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32850.888962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 32848.633654 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16719933 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7529000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2957 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5654.356781 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27180.505415 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 16787932 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7490000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2999 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 273 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5597.843281 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27435.897436 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 573004 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 337704 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2716896 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1445 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3054600 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3054600 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 386559 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249542 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12043 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 636101 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 636101 # number of overall MSHR misses +system.cpu.dcache.writebacks 572720 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 338008 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2717083 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3055091 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3055091 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 386111 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249564 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 12045 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 18 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 635675 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 635675 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5253783500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8925189433 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161542500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 293500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14178972933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14178972933 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158793000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258212210 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189417005210 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025526 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 5247540500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8926098932 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161654000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 282500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14173639432 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14173639432 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158749000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258178710 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 189416927710 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025509 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024390 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038420 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038427 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000063 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025068 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025058 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025068 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025058 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13591.155555 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.281560 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13413.808852 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15447.368421 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13590.756285 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.772980 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13420.838522 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15694.444444 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -764,8 +765,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1307895610037 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1307895610037 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1307898920918 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1307898920918 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 336a6fed4..5371c92be 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -1301,7 +1301,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/projects/pd/randd/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1321,7 +1321,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index b4c2d7806..795bcf9d9 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,16 +1,13 @@ -Redirecting stdout to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 17 2011 18:36:33 -gem5 started Nov 17 2011 18:37:39 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Nov 21 2011 16:24:08 +gem5 started Nov 21 2011 23:30:30 +gem5 executing on u200540-lin command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -tests warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5145286546500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 4f78f7da1..f0652d752 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 5.145287 # Number of seconds simulated sim_ticks 5145286546500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252508 # Simulator instruction rate (inst/s) -host_tick_rate 1546872935 # Simulator tick rate (ticks/s) -host_mem_usage 390244 # Number of bytes of host memory used -host_seconds 3326.25 # Real time elapsed on the host +host_inst_rate 333179 # Simulator instruction rate (inst/s) +host_tick_rate 2041066369 # Simulator tick rate (ticks/s) +host_mem_usage 358476 # Number of bytes of host memory used +host_seconds 2520.88 # Real time elapsed on the host sim_insts 839904894 # Number of instructions simulated system.l2c.replacements 171120 # number of replacements system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use @@ -511,6 +511,7 @@ system.cpu.rob.rob_reads 1146769000 # Th system.cpu.rob.rob_writes 1747209492 # The number of ROB writes system.cpu.timesIdled 3079387 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 161976736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9841548887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 839904894 # Number of Instructions Simulated system.cpu.committedInsts_total 839904894 # Number of Instructions Simulated system.cpu.cpi 0.534610 # CPI: Cycles Per Instruction diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 9bd7bf3ba..665888efd 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 67dc34515..af9fa8a65 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 12:28:18 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 17:34:42 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 33049447500 because target called exit() +Exiting @ tick 33080569000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index acf1a3733..b76763b67 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033049 # Number of seconds simulated -sim_ticks 33049447500 # Number of ticks simulated +sim_seconds 0.033081 # Number of seconds simulated +sim_ticks 33080569000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142392 # Simulator instruction rate (inst/s) -host_tick_rate 51572715 # Simulator tick rate (ticks/s) -host_mem_usage 349636 # Number of bytes of host memory used -host_seconds 640.83 # Real time elapsed on the host -sim_insts 91249665 # Number of instructions simulated +host_inst_rate 152633 # Simulator instruction rate (inst/s) +host_tick_rate 55333677 # Simulator tick rate (ticks/s) +host_mem_usage 347340 # Number of bytes of host memory used +host_seconds 597.84 # Real time elapsed on the host +sim_insts 91249885 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,141 +51,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 66098896 # number of cpu cycles simulated +system.cpu.numCycles 66161139 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27480852 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21948199 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1405962 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 24356195 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 23358870 # Number of BTB hits +system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21975755 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1408867 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 24498145 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 23511296 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 118630 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 12953 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15359689 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 131196018 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27480852 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23477500 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 32529765 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5482056 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14124387 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14730221 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368829 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66068188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.007516 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.747063 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15373276 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131330352 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 32575580 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5466802 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14146451 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14744728 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 369535 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66131343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 33589573 50.84% 50.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6678757 10.11% 60.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5691945 8.62% 69.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4809462 7.28% 76.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2791705 4.23% 81.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1680164 2.54% 83.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1554358 2.35% 85.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2929699 4.43% 90.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6342525 9.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 33609066 50.82% 50.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6636464 10.04% 60.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4857984 7.35% 76.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2814891 4.26% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1559267 2.36% 86.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2974436 4.50% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6276067 9.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66068188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.415754 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.984844 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17938862 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12617377 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30503596 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 985227 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4023126 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444811 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 31491 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 129102519 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31918 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4023126 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19654279 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1111044 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8373205 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 29732459 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3174075 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 125001528 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 255212 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1879877 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145677643 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 544340805 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 544335582 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5223 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429087 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38248551 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 647769 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 649953 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7510284 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29313185 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5861466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1226589 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 648810 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 117406606 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 634842 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 106217024 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 74725 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26332148 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63315965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 80484 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66068188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.607688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.762772 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 66131343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17946396 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12652276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30529024 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4006999 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 129091755 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4006999 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19654600 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1107804 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 29777332 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3160117 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124853414 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1879605 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145685583 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 543523067 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 543516086 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38256144 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 662187 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 664355 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7619533 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29336350 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 117270516 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 106162042 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26211084 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 62748223 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66131343 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24256842 36.71% 36.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14242052 21.56% 58.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9853567 14.91% 73.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8048166 12.18% 85.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4234412 6.41% 91.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2296375 3.48% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2457048 3.72% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476279 0.72% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 203447 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24322507 36.78% 36.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14238727 21.53% 58.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9857796 14.91% 73.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8080873 12.22% 85.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4216462 6.38% 91.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2267133 3.43% 95.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2478028 3.75% 98.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66068188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66131343 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53590 10.28% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 193594 37.13% 47.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 274209 52.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 52363 10.31% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 192834 37.95% 48.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74732015 70.36% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10984 0.01% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74696384 70.36% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued @@ -207,144 +207,144 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 117 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 159 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 183 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 260 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26127838 24.60% 94.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5345884 5.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26155378 24.64% 95.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106217024 # Type of FU issued -system.cpu.iq.rate 1.606941 # Inst issue rate -system.cpu.iq.fu_busy_cnt 521420 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004909 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 279097712 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144373136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102515328 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 669 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1008 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106738111 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 333 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 366236 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 106162042 # Type of FU issued +system.cpu.iq.rate 1.604598 # Inst issue rate +system.cpu.iq.fu_busy_cnt 508131 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 278993219 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144129610 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102521129 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106669721 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 366276 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6737356 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42339 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 715 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1114761 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6760478 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30343 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4023126 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 183340 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 29024 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118080266 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 812187 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29313185 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5861466 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 629989 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9572 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1070 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 715 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1280450 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 209997 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1490447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104523417 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25726566 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1693607 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4006999 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 117958129 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29336350 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1050 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 731 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104530426 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1631616 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38818 # number of nop insts executed -system.cpu.iew.exec_refs 30937872 # number of memory reference insts executed -system.cpu.iew.exec_branches 21209374 # Number of branches executed -system.cpu.iew.exec_stores 5211306 # Number of stores executed -system.cpu.iew.exec_rate 1.581319 # Inst execution rate -system.cpu.iew.wb_sent 102947388 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102515637 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60320212 # num instructions producing a value -system.cpu.iew.wb_consumers 97098710 # num instructions consuming a value +system.cpu.iew.exec_nop 38806 # number of nop insts executed +system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed +system.cpu.iew.exec_branches 21214083 # Number of branches executed +system.cpu.iew.exec_stores 5202833 # Number of stores executed +system.cpu.iew.exec_rate 1.579937 # Inst execution rate +system.cpu.iew.wb_sent 102941811 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102521541 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60312663 # num instructions producing a value +system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.550943 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.621226 # average fanout of values written-back +system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262274 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26817270 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554358 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1387669 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 62045063 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.470903 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.226778 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26696986 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.469029 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.224973 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 28329843 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16548650 26.67% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5280214 8.51% 80.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3902195 6.29% 87.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2034976 3.28% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 672623 1.08% 91.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 530029 0.85% 92.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 208846 0.34% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4537687 7.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 28387912 45.70% 45.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16565318 26.66% 72.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5280655 8.50% 80.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3908699 6.29% 87.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2045216 3.29% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 660602 1.06% 91.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 536847 0.86% 92.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 207955 0.33% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4531141 7.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 62045063 # Number of insts commited each cycle -system.cpu.commit.count 91262274 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle +system.cpu.commit.count 91262494 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322533 # Number of memory references committed -system.cpu.commit.loads 22575828 # Number of loads committed +system.cpu.commit.refs 27322621 # Number of memory references committed +system.cpu.commit.loads 22575872 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722422 # Number of branches committed +system.cpu.commit.branches 18722466 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533126 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533302 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4537687 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 175581186 # The number of ROB reads -system.cpu.rob.rob_writes 240196081 # The number of ROB writes +system.cpu.rob.rob_reads 175546950 # The number of ROB reads +system.cpu.rob.rob_writes 239939834 # The number of ROB writes system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30708 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249665 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249665 # Number of Instructions Simulated -system.cpu.cpi 0.724374 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.724374 # CPI: Total CPI of All Threads -system.cpu.ipc 1.380502 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.380502 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 496839540 # number of integer regfile reads -system.cpu.int_regfile_writes 120902305 # number of integer regfile writes -system.cpu.fp_regfile_reads 158 # number of floating regfile reads -system.cpu.fp_regfile_writes 392 # number of floating regfile writes -system.cpu.misc_regfile_reads 184716876 # number of misc regfile reads -system.cpu.misc_regfile_writes 11506 # number of misc regfile writes +system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 91249885 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated +system.cpu.cpi 0.725054 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.725054 # CPI: Total CPI of All Threads +system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496902731 # number of integer regfile reads +system.cpu.int_regfile_writes 120936097 # number of integer regfile writes +system.cpu.fp_regfile_reads 197 # number of floating regfile reads +system.cpu.fp_regfile_writes 534 # number of floating regfile writes +system.cpu.misc_regfile_reads 184886725 # number of misc regfile reads +system.cpu.misc_regfile_writes 11594 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 613.066905 # Cycle average of tags in use -system.cpu.icache.total_refs 14729300 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 718 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 20514.345404 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 611.587678 # Cycle average of tags in use +system.cpu.icache.total_refs 14743812 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 20420.792244 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 613.066905 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.299349 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 14729300 # number of ReadReq hits -system.cpu.icache.demand_hits 14729300 # number of demand (read+write) hits -system.cpu.icache.overall_hits 14729300 # number of overall hits -system.cpu.icache.ReadReq_misses 921 # number of ReadReq misses -system.cpu.icache.demand_misses 921 # number of demand (read+write) misses -system.cpu.icache.overall_misses 921 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32465000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32465000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32465000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 14730221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 14730221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 14730221 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35249.728556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35249.728556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35249.728556 # average overall miss latency +system.cpu.icache.occ_blocks::0 611.587678 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 14743812 # number of ReadReq hits +system.cpu.icache.demand_hits 14743812 # number of demand (read+write) hits +system.cpu.icache.overall_hits 14743812 # number of overall hits +system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses +system.cpu.icache.demand_misses 916 # number of demand (read+write) misses +system.cpu.icache.overall_misses 916 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 14744728 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 14744728 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 14744728 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,139 +354,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 203 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 203 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 203 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 718 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 718 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 194 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 194 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24779500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 24887000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 24887000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 24887000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34511.838440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943500 # number of replacements -system.cpu.dcache.tagsinuse 3561.430485 # Cycle average of tags in use -system.cpu.dcache.total_refs 28801207 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947596 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.393973 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12279149000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3561.430485 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.869490 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24229442 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4559293 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6724 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5748 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 28788735 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 28788735 # number of overall hits -system.cpu.dcache.ReadReq_misses 990132 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 175688 # number of WriteReq misses +system.cpu.dcache.replacements 943456 # number of replacements +system.cpu.dcache.tagsinuse 3558.808717 # Cycle average of tags in use +system.cpu.dcache.total_refs 28819274 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.414451 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3558.808717 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24247443 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 28806685 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 28806685 # number of overall hits +system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1165820 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1165820 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5482674500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4505328405 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1165006 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5475542500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4498706928 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 9988002905 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9988002905 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25219574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 9974249428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9974249428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 25236710 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6731 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5748 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 29954555 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 29954555 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039260 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.037104 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001040 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.038920 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.038920 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5537.316742 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 25643.916517 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 29971691 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 29971691 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 5534.949109 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 25598.796670 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8567.362805 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8567.362805 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23285977 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency 8561.543398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 8561.543398 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8139 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2861.036614 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942954 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 87074 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 131149 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 942907 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 86240 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 131213 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 218223 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 218223 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 903058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 44539 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947597 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947597 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 217453 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 217453 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 903027 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 44526 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2256691000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1081795530 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3338486530 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3338486530 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2253075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1081062556 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3334137556 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3334137556 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035808 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031634 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031634 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2498.943589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24288.725162 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.025066 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.354894 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 742 # number of replacements -system.cpu.l2cache.tagsinuse 9256.207068 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1596737 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15558 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.631251 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 744 # number of replacements +system.cpu.l2cache.tagsinuse 9229.669539 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 391.956879 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8864.250189 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.011962 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.270515 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 901452 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942954 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 31278 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932730 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932730 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1045 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15585 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15585 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 498909000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 534709500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 534709500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 902497 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942954 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 45818 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 948315 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 948315 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.001158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.317343 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016434 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016434 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34258.851675 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.861073 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34309.239654 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34309.239654 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 392.792284 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8836.877255 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 932680 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 932680 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 14538 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 15595 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 15595 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 36209000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 498763000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 534972000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 534972000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 902470 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 942907 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 45805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 948275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 948275 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.001171 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.317389 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34304.071818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,24 +499,24 @@ system.cpu.l2cache.writebacks 32 # nu system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1035 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15575 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 15585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 32188500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451730000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 483918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 483918500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 484338000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317343 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016424 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016424 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31068.088033 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 904c0b6e2..7b0140e7c 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,7 +62,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index 697635a50..ef22c481f 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:20:15 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index b13ced2e7..a31e20e25 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.122216 # Number of seconds simulated sim_ticks 122215830000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2350642 # Simulator instruction rate (inst/s) -host_tick_rate 1178195565 # Simulator tick rate (ticks/s) -host_mem_usage 352660 # Number of bytes of host memory used -host_seconds 103.73 # Real time elapsed on the host +host_inst_rate 3705610 # Simulator instruction rate (inst/s) +host_tick_rate 1857336235 # Simulator tick rate (ticks/s) +host_mem_usage 328592 # Number of bytes of host memory used +host_seconds 65.80 # Real time elapsed on the host sim_insts 243835278 # Number of instructions simulated system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431661 # number of cpu cycles simulated @@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 18619960 # nu system.cpu.num_int_insts 194726506 # number of integer instructions system.cpu.num_fp_insts 11630 # number of float instructions system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451609 # number of times the integer registers were written +system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read system.cpu.num_fp_register_writes 90 # number of times the floating registers were written system.cpu.num_mem_refs 105711442 # number of memory refs diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index 75e17228b..f14a1754a 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,7 +165,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index b7d0f3ac1..5a81ca9dc 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:15:16 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 4bbbd4713..cec6d8979 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.362431 # Number of seconds simulated sim_ticks 362430887000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1087927 # Simulator instruction rate (inst/s) -host_tick_rate 1617068836 # Simulator tick rate (ticks/s) -host_mem_usage 361308 # Number of bytes of host memory used -host_seconds 224.13 # Real time elapsed on the host +host_inst_rate 1940887 # Simulator instruction rate (inst/s) +host_tick_rate 2884887520 # Simulator tick rate (ticks/s) +host_mem_usage 337564 # Number of bytes of host memory used +host_seconds 125.63 # Real time elapsed on the host sim_insts 243835278 # Number of instructions simulated system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 724861774 # number of cpu cycles simulated @@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 18619960 # nu system.cpu.num_int_insts 194726506 # number of integer instructions system.cpu.num_fp_insts 11630 # number of float instructions system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451608 # number of times the integer registers were written +system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read system.cpu.num_fp_register_writes 90 # number of times the floating registers were written system.cpu.num_mem_refs 105711442 # number of memory refs diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index e653f0d44..79e59f3f1 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 11517aaea..dde98e297 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 11 2011 21:12:14 -gem5 started Sep 11 2011 22:42:17 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 17:44:50 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 277977002000 because target called exit() +Exiting @ tick 274198757500 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index a35c3c833..5b64b7083 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.277977 # Number of seconds simulated -sim_ticks 277977002000 # Number of ticks simulated +sim_seconds 0.274199 # Number of seconds simulated +sim_ticks 274198757500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50801 # Simulator instruction rate (inst/s) -host_tick_rate 24630434 # Simulator tick rate (ticks/s) -host_mem_usage 268512 # Number of bytes of host memory used -host_seconds 11285.92 # Real time elapsed on the host -sim_insts 573340817 # Number of instructions simulated +host_inst_rate 124379 # Simulator instruction rate (inst/s) +host_tick_rate 59483814 # Simulator tick rate (ticks/s) +host_mem_usage 219308 # Number of bytes of host memory used +host_seconds 4609.64 # Real time elapsed on the host +sim_insts 573341162 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 555954005 # number of cpu cycles simulated +system.cpu.numCycles 548397516 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 228168556 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 182073516 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18360369 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 192570670 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 159873716 # Number of BTB hits +system.cpu.BPredUnit.lookups 225101784 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 179007547 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18307036 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 189868979 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156087931 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11766939 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2589198 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 157542477 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002347382 # Number of instructions fetch has processed -system.cpu.fetch.Branches 228168556 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 171640655 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 259558013 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 76911240 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 78784930 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75608 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 144858558 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4692724 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 552173964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.153531 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.835452 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 11743928 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2589266 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 154237973 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 996342059 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225101784 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167831859 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 251951083 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 70115496 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 88916227 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27190 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 141601056 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4591339 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 544609039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.120756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.818747 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 292628171 53.00% 53.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24182032 4.38% 57.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 41208027 7.46% 64.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40287755 7.30% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42593934 7.71% 79.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15362741 2.78% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18471004 3.35% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 15875720 2.88% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61564580 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 292670234 53.74% 53.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22602609 4.15% 57.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39324759 7.22% 65.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 38673680 7.10% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 44132407 8.10% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15219761 2.79% 83.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 18468380 3.39% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 13866800 2.55% 89.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59650409 10.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 552173964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.410409 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.802932 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 174643217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 74003655 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 241825434 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5575388 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 56126270 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33116303 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100775 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1131397141 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 219753 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 56126270 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 191113879 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6444669 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52172693 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 230777280 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15539173 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1066388511 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1227 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2971665 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 9137935 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 123 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1187101757 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4711515581 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4711512464 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3117 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672198744 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 514903008 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2758299 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2758344 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48904017 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 194788235 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 120640917 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16446877 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13823038 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 932596874 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4516730 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 763493806 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3302626 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 360793671 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1004885077 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 639153 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 552173964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.382705 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.650964 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 544609039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.410472 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.816825 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 173360184 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 84631968 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 232819510 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4407510 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 49389867 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33096702 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 88546 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1070717063 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 220828 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 49389867 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 189439670 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6246457 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 67211324 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 221002512 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11319209 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 984442373 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1013 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2966416 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5236155 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 73 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1176369692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4273292331 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4273289228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3103 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199296 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 504170396 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6164964 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6164681 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 63358237 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 196378247 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 77986326 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17967729 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12612066 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870602735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7830625 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 735457773 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1536942 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 302215535 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 751654986 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3952431 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 544609039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.350433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.595771 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 245578205 44.47% 44.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 95260536 17.25% 61.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 82729163 14.98% 76.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 61462148 11.13% 87.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 37755177 6.84% 94.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16395168 2.97% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7099577 1.29% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4357430 0.79% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1536560 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 241479375 44.34% 44.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 95418106 17.52% 61.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 86231703 15.83% 77.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59231990 10.88% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 36938301 6.78% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14710122 2.70% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6373652 1.17% 99.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3471755 0.64% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 754035 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 552173964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 544609039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 144550 1.16% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6747694 54.11% 55.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5577677 44.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133367 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6658147 68.82% 70.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2883419 29.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 512546383 67.13% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 380050 0.05% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 132 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 170906603 22.38% 89.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79660635 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 497367446 67.63% 67.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 380524 0.05% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 142 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 170820646 23.23% 90.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 66889012 9.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 763493806 # Type of FU issued -system.cpu.iq.rate 1.373304 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12469921 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016333 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2094933823 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1297974964 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 705382252 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 300 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 735457773 # Type of FU issued +system.cpu.iq.rate 1.341103 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9674933 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013155 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2026736140 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1180706061 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 693772826 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 320 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 454 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 775963575 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8509313 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 745132544 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 162 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8466293 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 68015373 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 52063 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 72908 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 63037135 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 69605317 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 50613 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 20382475 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 28343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 28472 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 334 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 56126270 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2680601 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121752 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 946450192 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12430419 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 194788235 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 120640917 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2741935 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45812 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 72908 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18589508 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6131708 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 24721216 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 732040071 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 161905826 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 31453735 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 49389867 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2700739 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 121924 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 887765924 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12225511 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 196378247 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 77986326 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6083275 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 46564 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7422 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18530018 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5460534 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 23990552 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 711163338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 161856987 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 24294435 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9336588 # number of nop insts executed -system.cpu.iew.exec_refs 233639604 # number of memory reference insts executed -system.cpu.iew.exec_branches 147368049 # Number of branches executed -system.cpu.iew.exec_stores 71733778 # Number of stores executed -system.cpu.iew.exec_rate 1.316728 # Inst execution rate -system.cpu.iew.wb_sent 720193208 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 705382268 # cumulative count of insts written-back -system.cpu.iew.wb_producers 398990171 # num instructions producing a value -system.cpu.iew.wb_consumers 706117751 # num instructions consuming a value +system.cpu.iew.exec_nop 9332564 # number of nop insts executed +system.cpu.iew.exec_refs 226770071 # number of memory reference insts executed +system.cpu.iew.exec_branches 147519559 # Number of branches executed +system.cpu.iew.exec_stores 64913084 # Number of stores executed +system.cpu.iew.exec_rate 1.296803 # Inst execution rate +system.cpu.iew.wb_sent 699318417 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 693772842 # cumulative count of insts written-back +system.cpu.iew.wb_producers 395045304 # num instructions producing a value +system.cpu.iew.wb_consumers 663504976 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.268778 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565048 # average fanout of values written-back +system.cpu.iew.wb_rate 1.265091 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.595392 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574684701 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 371780538 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3877577 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 20554122 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 496047695 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.158527 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.880172 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 574685046 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 313100037 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3878194 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 20503761 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 495219173 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.160466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.863525 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 262785164 52.98% 52.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 115198259 23.22% 76.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 44158877 8.90% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 20159823 4.06% 89.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19759049 3.98% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7211981 1.45% 94.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7550461 1.52% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3502296 0.71% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15721785 3.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 259975062 52.50% 52.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116222276 23.47% 75.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 44533135 8.99% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21295357 4.30% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19840150 4.01% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7283820 1.47% 94.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7518006 1.52% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3788243 0.76% 97.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14763124 2.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 496047695 # Number of insts commited each cycle -system.cpu.commit.count 574684701 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 495219173 # Number of insts commited each cycle +system.cpu.commit.count 574685046 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376643 # Number of memory references committed -system.cpu.commit.loads 126772861 # Number of loads committed +system.cpu.commit.refs 184376781 # Number of memory references committed +system.cpu.commit.loads 126772930 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192046 # Number of branches committed +system.cpu.commit.branches 120192115 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473700921 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701197 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15721785 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14763124 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1426784011 # The number of ROB reads -system.cpu.rob.rob_writes 1949388350 # The number of ROB writes -system.cpu.timesIdled 93530 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3780041 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573340817 # Number of Instructions Simulated -system.cpu.committedInsts_total 573340817 # Number of Instructions Simulated -system.cpu.cpi 0.969675 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.969675 # CPI: Total CPI of All Threads -system.cpu.ipc 1.031274 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.031274 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3375374322 # number of integer regfile reads -system.cpu.int_regfile_writes 818576050 # number of integer regfile writes +system.cpu.rob.rob_reads 1368233994 # The number of ROB reads +system.cpu.rob.rob_writes 1825140894 # The number of ROB writes +system.cpu.timesIdled 96084 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3788477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 573341162 # Number of Instructions Simulated +system.cpu.committedInsts_total 573341162 # Number of Instructions Simulated +system.cpu.cpi 0.956494 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.956494 # CPI: Total CPI of All Threads +system.cpu.ipc 1.045485 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.045485 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3291621496 # number of integer regfile reads +system.cpu.int_regfile_writes 815258640 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1246383424 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463694 # number of misc regfile writes -system.cpu.icache.replacements 12953 # number of replacements -system.cpu.icache.tagsinuse 1066.011172 # Cycle average of tags in use -system.cpu.icache.total_refs 144842026 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 14796 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9789.269127 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1231509968 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463832 # number of misc regfile writes +system.cpu.icache.replacements 12844 # number of replacements +system.cpu.icache.tagsinuse 1060.855578 # Cycle average of tags in use +system.cpu.icache.total_refs 141584558 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 14688 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9639.471541 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1066.011172 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.520513 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 144842026 # number of ReadReq hits -system.cpu.icache.demand_hits 144842026 # number of demand (read+write) hits -system.cpu.icache.overall_hits 144842026 # number of overall hits -system.cpu.icache.ReadReq_misses 16532 # number of ReadReq misses -system.cpu.icache.demand_misses 16532 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16532 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 236127500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 236127500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 236127500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 144858558 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 144858558 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 144858558 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 14283.057101 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 14283.057101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 14283.057101 # average overall miss latency +system.cpu.icache.occ_blocks::0 1060.855578 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.517996 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 141584561 # number of ReadReq hits +system.cpu.icache.demand_hits 141584561 # number of demand (read+write) hits +system.cpu.icache.overall_hits 141584561 # number of overall hits +system.cpu.icache.ReadReq_misses 16495 # number of ReadReq misses +system.cpu.icache.demand_misses 16495 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16495 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 235861500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 235861500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 235861500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 141601056 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 141601056 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 141601056 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000116 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000116 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000116 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 14298.969385 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 14298.969385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 14298.969385 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 3 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1595 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1595 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1595 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 14937 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 14937 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 14937 # number of overall MSHR misses +system.cpu.icache.writebacks 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1651 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1651 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1651 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 14844 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 14844 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 14844 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 154963500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 154963500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 154963500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 154845500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 154845500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 154845500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000103 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000103 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10374.472786 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10374.472786 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10374.472786 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10431.521153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1212304 # number of replacements -system.cpu.dcache.tagsinuse 4056.655033 # Cycle average of tags in use -system.cpu.dcache.total_refs 204333275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1216400 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.981976 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5992651000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4056.655033 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.990394 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 146799577 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52779397 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2522240 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2231846 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 199578974 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 199578974 # number of overall hits -system.cpu.dcache.ReadReq_misses 1241463 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1459909 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 57 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2701372 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2701372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14210039000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24949440994 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 510000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 39159479994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39159479994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 148041040 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1212341 # number of replacements +system.cpu.dcache.tagsinuse 4058.230538 # Cycle average of tags in use +system.cpu.dcache.total_refs 204314278 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1216437 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.961249 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5623770000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4058.230538 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.990779 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 146820758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 52766592 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2494784 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 2231915 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 199587350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 199587350 # number of overall hits +system.cpu.dcache.ReadReq_misses 1243424 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1472714 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 59 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2716138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2716138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14347379500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25015184497 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 557000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 39362563997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39362563997 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 148064182 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2522297 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2231846 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 202280346 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 202280346 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.008386 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.026916 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000023 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.013355 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013355 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 11446.204196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17089.723396 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 8947.368421 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14496.144920 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14496.144920 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 2494843 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 2231915 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 202303488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 202303488 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.008398 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.027152 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.013426 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013426 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 11538.605898 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 16985.772185 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 9440.677966 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 14492.107543 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 14492.107543 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 502000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 55 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7563.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7843.750000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1079589 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 365099 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1119740 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 57 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1484839 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1484839 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 876364 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 340169 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1216533 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1216533 # number of overall MSHR misses +system.cpu.dcache.writebacks 1079461 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 367349 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1132203 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 59 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1499552 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1499552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 876075 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 340511 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1216586 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1216586 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6322701500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4343796500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10666498000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10666498000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6316165000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4359865500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10676030500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10676030500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005920 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006272 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005917 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006278 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.006014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.006014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7214.697888 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12769.524854 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8767.947931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8767.947931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7209.616757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12803.890330 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218992 # number of replacements -system.cpu.l2cache.tagsinuse 21041.730576 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1568543 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 239349 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.553372 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 207293372000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7594.160868 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13447.569709 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.231755 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.410387 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 760588 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1079592 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 93 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 232455 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 993043 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 993043 # number of overall hits -system.cpu.l2cache.ReadReq_misses 130191 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 36 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 107958 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 238149 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 238149 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4453286000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 204500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3697103500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 8150389500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 8150389500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 890779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1079592 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 129 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 340413 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1231192 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1231192 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.146154 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.279070 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.317138 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.193430 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.193430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34205.789955 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5680.555556 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34245.757609 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34223.908142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34223.908142 # average overall miss latency +system.cpu.l2cache.replacements 219133 # number of replacements +system.cpu.l2cache.tagsinuse 21061.116186 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1567440 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 232507 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 992847 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 992847 # number of overall hits +system.cpu.l2cache.ReadReq_misses 130056 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 33 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 238282 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 340733 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1231129 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1231129 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.146065 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.221477 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 171216 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 130170 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 107958 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 238128 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 238128 # number of overall MSHR misses +system.cpu.l2cache.writebacks 171253 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 19 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 19 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 130037 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 108226 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4041635000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1116000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3347575000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7389210000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7389210000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146131 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.279070 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317138 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.193413 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.193413 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31048.897595 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.123530 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.412215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.412215 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index 538eb23e4..8c023b5bc 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index afdbb2fca..5bda3e9bb 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 12:28:18 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 17:59:30 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -15,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.100000 -Exiting @ tick 104473822000 because target called exit() +Exiting @ tick 104497559500 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index f346fce3e..3a7bc5069 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.104474 # Number of seconds simulated -sim_ticks 104473822000 # Number of ticks simulated +sim_seconds 0.104498 # Number of seconds simulated +sim_ticks 104497559500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153431 # Simulator instruction rate (inst/s) -host_tick_rate 45921219 # Simulator tick rate (ticks/s) -host_mem_usage 225932 # Number of bytes of host memory used -host_seconds 2275.07 # Real time elapsed on the host -sim_insts 349066014 # Number of instructions simulated +host_inst_rate 166687 # Simulator instruction rate (inst/s) +host_tick_rate 49899949 # Simulator tick rate (ticks/s) +host_mem_usage 223124 # Number of bytes of host memory used +host_seconds 2094.14 # Real time elapsed on the host +sim_insts 349066034 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,105 +51,105 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 208947645 # number of cpu cycles simulated +system.cpu.numCycles 208995120 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38329680 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21105904 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3259287 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27325340 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21186794 # Number of BTB hits +system.cpu.BPredUnit.lookups 38326507 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21101495 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3258977 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27386254 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 21276883 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7687582 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 64950 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 43658765 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 338491573 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38329680 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 28874376 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 79000452 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11006616 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 78476147 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 177 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 41256182 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 909033 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 208834894 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.121215 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193825 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7682399 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 61114 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 43645867 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 338408122 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38326507 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 28959282 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79027162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10989913 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 78526305 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 41243030 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 908340 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 208882385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.119969 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.192320 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130486470 62.48% 62.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9432998 4.52% 67.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6020581 2.88% 69.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6715952 3.22% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5392715 2.58% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4860169 2.33% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3823300 1.83% 79.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4271417 2.05% 81.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 37831292 18.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130507129 62.48% 62.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9423807 4.51% 66.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6028759 2.89% 69.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6771553 3.24% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5439017 2.60% 75.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4859666 2.33% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3802857 1.82% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4240079 2.03% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 37809518 18.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 208834894 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.183442 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.619983 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 51226737 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73595547 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 72551850 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3832247 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7628513 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7466092 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 71093 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 431841645 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 197934 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 7628513 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 58855206 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1197679 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57579508 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68948533 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14625455 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 416807689 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21628 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8007310 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 208882385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.183385 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.619215 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 51208963 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73647751 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 72596931 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3816657 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7612083 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7463930 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 71162 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 431701457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 197547 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 7612083 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 58859623 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1188483 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57604104 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68958235 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14659857 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 416634975 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8024802 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 455449785 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2447349864 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1352895692 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1094454172 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568567 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 70881213 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3981353 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4038094 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48179191 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108793088 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93182345 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3369455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2301817 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394396503 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3860146 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 379227630 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1821640 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 46525332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 143742588 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 304700 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 208834894 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.815921 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996738 # Number of insts issued each cycle +system.cpu.rename.RenamedOperands 455431964 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2446622850 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1351809132 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1094813718 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 70863365 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3987641 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4044473 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48252141 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 108792162 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93099672 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3342545 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2273908 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 394239255 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3865155 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 379120981 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1801347 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 46369193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 143590674 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 309514 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 208882385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.814997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995935 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82039971 39.28% 39.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 34743122 16.64% 55.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24446026 11.71% 67.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18532815 8.87% 76.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21777610 10.43% 86.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15334879 7.34% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8388297 4.02% 98.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2697998 1.29% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 874176 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82049002 39.28% 39.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 34801326 16.66% 55.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24478546 11.72% 67.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18529016 8.87% 76.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21712805 10.39% 86.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15357191 7.35% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8402907 4.02% 98.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2691838 1.29% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 859754 0.41% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 208834894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 208882385 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2499 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2250 0.01% 0.01% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available @@ -169,181 +169,181 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 10462 0.06% 0.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 10815 0.06% 0.10% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 2799 0.02% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 391 0.00% 0.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 2509 0.01% 0.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 64669 0.37% 0.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 64370 0.37% 0.49% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 798 0.00% 0.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 177194 1.02% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 177500 1.02% 1.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9656371 55.60% 57.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7448588 42.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9658261 55.66% 57.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7430721 42.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 129667439 34.19% 34.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147217 0.57% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 12 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6745597 1.78% 36.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8690395 2.29% 38.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3497824 0.92% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1584668 0.42% 40.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21149446 5.58% 45.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7187375 1.90% 47.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146329 1.88% 49.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103745248 27.36% 76.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 87490792 23.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 129606192 34.19% 34.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147281 0.57% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 13 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6746387 1.78% 36.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8673518 2.29% 38.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3499070 0.92% 39.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1584810 0.42% 40.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21149805 5.58% 45.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7187648 1.90% 47.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147289 1.89% 49.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103746274 27.36% 76.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 87457408 23.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 379227630 # Type of FU issued -system.cpu.iq.rate 1.814941 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17368817 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.045801 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 735557028 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 310975021 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 251585005 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 250923583 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 133814979 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118291748 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 267725333 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128871114 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7296411 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 379120981 # Type of FU issued +system.cpu.iq.rate 1.814018 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17352648 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.045771 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 735350759 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 310614656 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 251531674 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 250927583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 133866908 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118270115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 267600383 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128873246 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7282081 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14144091 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112652 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10806518 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14143162 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112354 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8279 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10723841 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 272 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7628513 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 19213 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 427 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 398303949 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2640938 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108793088 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93182345 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3848920 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 191 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3190408 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 311351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3501759 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373094213 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102121029 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6133417 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7612083 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19341 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 398151655 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2633597 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 108792162 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93099672 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3853935 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8279 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3193235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 309338 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3502573 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373031388 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102121270 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6089593 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 47300 # number of nop insts executed -system.cpu.iew.exec_refs 188086624 # number of memory reference insts executed -system.cpu.iew.exec_branches 32219112 # Number of branches executed -system.cpu.iew.exec_stores 85965595 # Number of stores executed -system.cpu.iew.exec_rate 1.785587 # Inst execution rate -system.cpu.iew.wb_sent 370884944 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 369876753 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175641589 # num instructions producing a value -system.cpu.iew.wb_consumers 345778200 # num instructions consuming a value +system.cpu.iew.exec_nop 47245 # number of nop insts executed +system.cpu.iew.exec_refs 188074720 # number of memory reference insts executed +system.cpu.iew.exec_branches 32215232 # Number of branches executed +system.cpu.iew.exec_stores 85953450 # Number of stores executed +system.cpu.iew.exec_rate 1.784881 # Inst execution rate +system.cpu.iew.wb_sent 370805637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 369801789 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175613931 # num instructions producing a value +system.cpu.iew.wb_consumers 345608979 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.770189 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.507960 # average fanout of values written-back +system.cpu.iew.wb_rate 1.769428 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.508129 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 349066626 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 49232556 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3230297 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 201206382 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734869 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.321510 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 49085191 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3229927 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 201270303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734318 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.320939 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 89873367 44.67% 44.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 39509516 19.64% 64.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17955811 8.92% 73.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13150988 6.54% 79.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14566158 7.24% 87.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7624448 3.79% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3491536 1.74% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3420028 1.70% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11614530 5.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 89873146 44.65% 44.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 39586205 19.67% 64.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17962686 8.92% 73.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13145817 6.53% 79.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14573998 7.24% 87.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7584463 3.77% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3507612 1.74% 92.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3437369 1.71% 94.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11599007 5.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 201206382 # Number of insts commited each cycle -system.cpu.commit.count 349066626 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 201270303 # Number of insts commited each cycle +system.cpu.commit.count 349066646 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024823 # Number of memory references committed -system.cpu.commit.loads 94648996 # Number of loads committed +system.cpu.commit.refs 177024831 # Number of memory references committed +system.cpu.commit.loads 94649000 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521875 # Number of branches committed +system.cpu.commit.branches 30521879 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279585913 # Number of committed integer instructions. +system.cpu.commit.int_insts 279585929 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11614530 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11599007 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 587888511 # The number of ROB reads -system.cpu.rob.rob_writes 804230779 # The number of ROB writes -system.cpu.timesIdled 2579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 112751 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 349066014 # Number of Instructions Simulated -system.cpu.committedInsts_total 349066014 # Number of Instructions Simulated -system.cpu.cpi 0.598591 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.598591 # CPI: Total CPI of All Threads -system.cpu.ipc 1.670591 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.670591 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1782159085 # number of integer regfile reads -system.cpu.int_regfile_writes 235889793 # number of integer regfile writes -system.cpu.fp_regfile_reads 188830050 # number of floating regfile reads -system.cpu.fp_regfile_writes 133876834 # number of floating regfile writes -system.cpu.misc_regfile_reads 1003607247 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422185 # number of misc regfile writes -system.cpu.icache.replacements 14102 # number of replacements -system.cpu.icache.tagsinuse 1840.385487 # Cycle average of tags in use -system.cpu.icache.total_refs 41239547 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2580.859065 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 587820610 # The number of ROB reads +system.cpu.rob.rob_writes 803918901 # The number of ROB writes +system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 112735 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 349066034 # Number of Instructions Simulated +system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated +system.cpu.cpi 0.598727 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.598727 # CPI: Total CPI of All Threads +system.cpu.ipc 1.670211 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.670211 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1781871579 # number of integer regfile reads +system.cpu.int_regfile_writes 235815438 # number of integer regfile writes +system.cpu.fp_regfile_reads 188771754 # number of floating regfile reads +system.cpu.fp_regfile_writes 133861667 # number of floating regfile writes +system.cpu.misc_regfile_reads 1003473737 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes +system.cpu.icache.replacements 14107 # number of replacements +system.cpu.icache.tagsinuse 1842.677380 # Cycle average of tags in use +system.cpu.icache.total_refs 41226387 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15987 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2578.744417 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1840.385487 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.898626 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 41239547 # number of ReadReq hits -system.cpu.icache.demand_hits 41239547 # number of demand (read+write) hits -system.cpu.icache.overall_hits 41239547 # number of overall hits -system.cpu.icache.ReadReq_misses 16635 # number of ReadReq misses -system.cpu.icache.demand_misses 16635 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16635 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 200891500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 200891500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 200891500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 41256182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 41256182 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 41256182 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000403 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000403 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000403 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12076.435227 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12076.435227 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12076.435227 # average overall miss latency +system.cpu.icache.occ_blocks::0 1842.677380 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.899745 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 41226387 # number of ReadReq hits +system.cpu.icache.demand_hits 41226387 # number of demand (read+write) hits +system.cpu.icache.overall_hits 41226387 # number of overall hits +system.cpu.icache.ReadReq_misses 16643 # number of ReadReq misses +system.cpu.icache.demand_misses 16643 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 201090500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 201090500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 201090500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 41243030 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 41243030 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 41243030 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12082.587274 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12082.587274 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12082.587274 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,142 +353,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 640 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 640 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 640 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 15995 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 15995 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 15995 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 16006 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 16006 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 16006 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 135868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 135868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 135868500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 136032000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 136032000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 136032000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8494.435761 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8494.435761 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8494.435761 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8498.812945 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1418 # number of replacements -system.cpu.dcache.tagsinuse 3101.734429 # Cycle average of tags in use -system.cpu.dcache.total_refs 176600871 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4608 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38324.841797 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1408 # number of replacements +system.cpu.dcache.tagsinuse 3101.194672 # Cycle average of tags in use +system.cpu.dcache.total_refs 176614084 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4596 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38427.781549 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3101.734429 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.757259 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94544101 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 82033265 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 12379 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11110 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 176577366 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 176577366 # number of overall hits -system.cpu.dcache.ReadReq_misses 3426 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19429 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 3101.194672 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.757128 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 94558380 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 82033210 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 11361 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 176591590 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 176591590 # number of overall hits +system.cpu.dcache.ReadReq_misses 3380 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19484 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 22855 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 22855 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 112688000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 648331000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 22864 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 22864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 111762500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 649531500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 761019000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 761019000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94547527 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 761294000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 761294000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 94561760 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 12381 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11110 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 176600221 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 176600221 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 11363 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 176614454 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 176614454 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000162 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32892.002335 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33369.241855 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33065.828402 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33336.660850 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33297.702910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33297.702910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33296.623513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33296.623513 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1659 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16572 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 1030 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16619 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 18231 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 18231 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1767 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 2857 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4624 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4624 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 18249 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 18249 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2865 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4615 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4615 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 53837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 101449500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 155286500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 155286500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 53437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 101725000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 155162000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 155162000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30468.024901 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35509.100455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33582.720588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33582.720588 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30535.428571 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35506.108202 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 59 # number of replacements -system.cpu.l2cache.tagsinuse 3910.433469 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13338 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5362 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.487505 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 57 # number of replacements +system.cpu.l2cache.tagsinuse 3897.011564 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13334 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5354 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.490474 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3528.791205 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 381.642264 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107690 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011647 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 13254 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1035 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 3518.810301 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 378.201262 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.107386 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011542 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 13251 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1030 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 13273 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 13273 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4491 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 2823 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7314 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 154072000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 97347500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 251419500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 251419500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 17745 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1035 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 2842 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 20587 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 20587 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.253085 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_hits 13270 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 13270 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4485 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 2828 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7313 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7313 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 153892500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 97502000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 251394500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 251394500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 17736 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1030 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 2847 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 20583 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 20583 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.252876 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.993315 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.355273 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.355273 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34306.835894 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34483.705278 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34375.102543 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34375.102543 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.993326 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.355293 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.355293 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34312.709030 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.369165 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34376.384521 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34376.384521 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,31 +498,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4435 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 2823 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 4430 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 2828 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses 7258 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 7258 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 138176000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 497000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88317500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 226493500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 226493500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 138008000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88479500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 226487500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 226487500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249930 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249774 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.352553 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.352553 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.806088 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31062.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31284.980517 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.048498 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.048498 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993326 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.352621 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.352621 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.047404 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31286.951909 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index d6e8feb5e..eaf32daa6 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index d1d73ccec..fc03e6958 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 11 2011 21:12:14 -gem5 started Sep 11 2011 21:52:21 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 18:31:45 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 708531477500 because target called exit() +Exiting @ tick 708403313500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 51c2df969..e47b3cac2 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708531 # Number of seconds simulated -sim_ticks 708531477500 # Number of ticks simulated +sim_seconds 0.708403 # Number of seconds simulated +sim_ticks 708403313500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73177 # Simulator instruction rate (inst/s) -host_tick_rate 27500789 # Simulator tick rate (ticks/s) -host_mem_usage 269872 # Number of bytes of host memory used -host_seconds 25764.04 # Real time elapsed on the host -sim_insts 1885333781 # Number of instructions simulated +host_inst_rate 129621 # Simulator instruction rate (inst/s) +host_tick_rate 48704258 # Simulator tick rate (ticks/s) +host_mem_usage 220728 # Number of bytes of host memory used +host_seconds 14545.00 # Real time elapsed on the host +sim_insts 1885333786 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,107 +51,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1417062956 # number of cpu cycles simulated +system.cpu.numCycles 1416806628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 503197532 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 388248962 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 32912455 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 402367124 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 282669140 # Number of BTB hits +system.cpu.BPredUnit.lookups 503033036 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 388160087 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 32894916 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 402481986 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 281923865 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59794264 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2845178 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 410598466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2543215501 # Number of instructions fetch has processed -system.cpu.fetch.Branches 503197532 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 342463404 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 683221197 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 205184289 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 105176674 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2131 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 34940 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 384286264 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12168665 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1365728364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589436 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.160278 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 59796610 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2840141 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410550003 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2542460473 # Number of instructions fetch has processed +system.cpu.fetch.Branches 503033036 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 341720475 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 682921340 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 205013758 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 105428035 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2115 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 34704 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 384233965 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12151873 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1365478165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.588855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.160415 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 682546834 49.98% 49.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48268776 3.53% 53.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108820649 7.97% 61.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 62416445 4.57% 66.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 89329433 6.54% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54222188 3.97% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35559819 2.60% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 34994936 2.56% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249569284 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 682595631 49.99% 49.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48342952 3.54% 53.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 108702790 7.96% 61.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 62379051 4.57% 66.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 89292584 6.54% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 54148565 3.97% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35470304 2.60% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 34965610 2.56% 81.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249580678 18.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1365728364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355099 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.794709 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 455451885 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84966420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 647527818 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11100617 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 166681624 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 68771353 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13534 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3425616416 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 23343 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 166681624 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 496974681 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29107016 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3577336 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 615567899 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53819808 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3299332882 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4545741 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42264080 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3261811960 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15630618087 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14995522132 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 635095955 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153591 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1268658364 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 292165 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 287873 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155635348 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1045682058 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 527865899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35886161 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 45188431 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3078949788 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 286075 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620068122 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18730048 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1193263945 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2902703474 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 76157 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1365728364 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.918440 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.900398 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1365478165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355047 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.794501 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 455361727 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 85217138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 647145530 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11223736 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 166530034 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 68649997 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12124 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3424361675 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 24057 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 166530034 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 496888956 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29110139 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3718079 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 615295356 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53935601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3298153337 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4569845 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42334817 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3261061532 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 15624755618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14989571898 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 635183720 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1267907933 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 310582 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 306325 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 155884977 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1045137132 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 527476218 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35886570 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 45267364 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3077754179 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 303954 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2619291842 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18689867 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1192085861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2899457281 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 92624 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1365478165 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.918223 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.900205 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 480776818 35.20% 35.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182697295 13.38% 48.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216773103 15.87% 64.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 179469890 13.14% 77.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 151098316 11.06% 88.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 89760948 6.57% 95.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48715298 3.57% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11568409 0.85% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4868287 0.36% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 480779837 35.21% 35.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182587607 13.37% 48.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216609244 15.86% 64.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 179766275 13.17% 77.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 150868799 11.05% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 89721779 6.57% 95.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48758870 3.57% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11536421 0.84% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4849333 0.36% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1365728364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1365478165 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2047633 2.26% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23928 0.03% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2044403 2.26% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23929 0.03% 2.28% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available @@ -179,172 +179,172 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55695213 61.39% 63.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32952568 36.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55649007 61.42% 63.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32885475 36.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1201100528 45.84% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11234357 0.43% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 6823 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876481 0.26% 46.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5505298 0.21% 46.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1200920026 45.85% 45.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11234109 0.43% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.26% 46.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5505406 0.21% 46.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24361440 0.93% 47.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24362118 0.93% 47.73% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.73% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.73% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 896104682 34.20% 81.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 473503224 18.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 895924024 34.20% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 473094394 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620068122 # Type of FU issued -system.cpu.iq.rate 1.848943 # Inst issue rate -system.cpu.iq.fu_busy_cnt 90719342 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034625 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6586805397 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4173231874 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2409969161 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128508601 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 99321062 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57077308 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2645158963 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 65628501 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72009285 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2619291842 # Type of FU issued +system.cpu.iq.rate 1.848729 # Inst issue rate +system.cpu.iq.fu_busy_cnt 90602814 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6584849993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4170838685 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2409550549 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 128504537 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 99358414 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 57073276 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2644267181 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 65627475 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 71974387 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 414293189 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1389891 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250868916 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 413748263 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264274 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1389738 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 250479234 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 166681624 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16374995 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1474320 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3079304358 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12740517 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1045682058 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 527865899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 274568 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1470984 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 216 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1389891 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34543873 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8891706 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 43435579 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2534937994 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 842579419 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 85130128 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 166530034 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16377218 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1473925 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3078126585 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12745051 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1045137132 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 527476218 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 292477 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1470662 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 212 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1389738 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 34580674 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8873578 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 43454252 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2534450261 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 842463670 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 84841581 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 68495 # number of nop insts executed -system.cpu.iew.exec_refs 1294824342 # number of memory reference insts executed -system.cpu.iew.exec_branches 344662618 # Number of branches executed -system.cpu.iew.exec_stores 452244923 # Number of stores executed -system.cpu.iew.exec_rate 1.788868 # Inst execution rate -system.cpu.iew.wb_sent 2496106713 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2467046469 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1448587293 # num instructions producing a value -system.cpu.iew.wb_consumers 2708320532 # num instructions consuming a value +system.cpu.iew.exec_nop 68452 # number of nop insts executed +system.cpu.iew.exec_refs 1294415982 # number of memory reference insts executed +system.cpu.iew.exec_branches 344601931 # Number of branches executed +system.cpu.iew.exec_stores 451952312 # Number of stores executed +system.cpu.iew.exec_rate 1.788847 # Inst execution rate +system.cpu.iew.wb_sent 2495608341 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2466623825 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1448525550 # num instructions producing a value +system.cpu.iew.wb_consumers 2707902616 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.740958 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534866 # average fanout of values written-back +system.cpu.iew.wb_rate 1.740974 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534925 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1885344797 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1193920948 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 209918 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 38436982 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1199046742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.572370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.256600 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1192782047 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 38420798 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1198948133 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.572499 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.256451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 532251438 44.39% 44.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 299124354 24.95% 69.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 106727923 8.90% 78.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 77554525 6.47% 84.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 53347084 4.45% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23351353 1.95% 91.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17117984 1.43% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9328631 0.78% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 80243450 6.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 532143962 44.38% 44.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 299077946 24.95% 69.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 106761313 8.90% 78.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 77538501 6.47% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 53400435 4.45% 89.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23357302 1.95% 91.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17130441 1.43% 92.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9348033 0.78% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 80190200 6.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1199046742 # Number of insts commited each cycle -system.cpu.commit.count 1885344797 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 1198948133 # Number of insts commited each cycle +system.cpu.commit.count 1885344802 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385851 # Number of memory references committed -system.cpu.commit.loads 631388868 # Number of loads committed +system.cpu.commit.refs 908385853 # Number of memory references committed +system.cpu.commit.loads 631388869 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350231 # Number of branches committed +system.cpu.commit.branches 291350232 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705619 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 80243450 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 80190200 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4198050692 # The number of ROB reads -system.cpu.rob.rob_writes 6325233568 # The number of ROB writes -system.cpu.timesIdled 1340861 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51334592 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1885333781 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885333781 # Number of Instructions Simulated -system.cpu.cpi 0.751624 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.751624 # CPI: Total CPI of All Threads -system.cpu.ipc 1.330452 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.330452 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12569578143 # number of integer regfile reads -system.cpu.int_regfile_writes 2360113760 # number of integer regfile writes -system.cpu.fp_regfile_reads 68800138 # number of floating regfile reads -system.cpu.fp_regfile_writes 50190994 # number of floating regfile writes -system.cpu.misc_regfile_reads 3981621400 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776274 # number of misc regfile writes -system.cpu.icache.replacements 27318 # number of replacements -system.cpu.icache.tagsinuse 1634.845440 # Cycle average of tags in use -system.cpu.icache.total_refs 384252011 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28994 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13252.811306 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4196866437 # The number of ROB reads +system.cpu.rob.rob_writes 6322804382 # The number of ROB writes +system.cpu.timesIdled 1340913 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51328463 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1885333786 # Number of Instructions Simulated +system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated +system.cpu.cpi 0.751488 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.751488 # CPI: Total CPI of All Threads +system.cpu.ipc 1.330692 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.330692 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12567203807 # number of integer regfile reads +system.cpu.int_regfile_writes 2360160094 # number of integer regfile writes +system.cpu.fp_regfile_reads 68800597 # number of floating regfile reads +system.cpu.fp_regfile_writes 50187558 # number of floating regfile writes +system.cpu.misc_regfile_reads 3980455481 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes +system.cpu.icache.replacements 27305 # number of replacements +system.cpu.icache.tagsinuse 1638.856970 # Cycle average of tags in use +system.cpu.icache.total_refs 384199729 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 28984 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13255.579941 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1634.845440 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.798264 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 384252124 # number of ReadReq hits -system.cpu.icache.demand_hits 384252124 # number of demand (read+write) hits -system.cpu.icache.overall_hits 384252124 # number of overall hits -system.cpu.icache.ReadReq_misses 34140 # number of ReadReq misses -system.cpu.icache.demand_misses 34140 # number of demand (read+write) misses -system.cpu.icache.overall_misses 34140 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 301222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 301222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 301222000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 384286264 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 384286264 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 384286264 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1638.856970 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.800223 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 384199814 # number of ReadReq hits +system.cpu.icache.demand_hits 384199814 # number of demand (read+write) hits +system.cpu.icache.overall_hits 384199814 # number of overall hits +system.cpu.icache.ReadReq_misses 34151 # number of ReadReq misses +system.cpu.icache.demand_misses 34151 # number of demand (read+write) misses +system.cpu.icache.overall_misses 34151 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 301141000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 301141000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 301141000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 384233965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 384233965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 384233965 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 8823.140012 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 8823.140012 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 8823.140012 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 8817.926269 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 8817.926269 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 8817.926269 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,143 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 774 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 774 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 774 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 33366 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 33366 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 33366 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 772 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 772 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 772 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 33379 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 33379 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 33379 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 180870500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 180870500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 180870500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 180850500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 180850500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 180850500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5420.802613 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5418.092214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1531930 # number of replacements -system.cpu.dcache.tagsinuse 4094.787279 # Cycle average of tags in use -system.cpu.dcache.total_refs 1029517706 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536026 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 670.247578 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 306646000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.787279 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999704 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 753359421 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 276118539 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 14346 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11671 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 1029477960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1029477960 # number of overall hits -system.cpu.dcache.ReadReq_misses 1938279 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 817139 # number of WriteReq misses +system.cpu.dcache.replacements 1531788 # number of replacements +system.cpu.dcache.tagsinuse 4094.791932 # Cycle average of tags in use +system.cpu.dcache.total_refs 1029449306 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1535884 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 670.265011 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 305577000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.791932 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 753290045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 276118528 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 15313 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 1029408573 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1029408573 # number of overall hits +system.cpu.dcache.ReadReq_misses 1938158 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 817150 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2755418 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2755418 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 69353392500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 28486542000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2755308 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2755308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 69348240500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28488261000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 97839934500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 97839934500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 755297700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 97836501500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 97836501500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 755228203 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 14349 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1032233378 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1032233378 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 15316 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 1032163881 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1032163881 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000209 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000196 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35780.913119 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34861.317352 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 35780.488742 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34862.951722 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35508.200389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35508.200389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35508.372022 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35508.372022 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106827 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 474953 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 740066 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 106544 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 474971 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 740057 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1215019 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1215019 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1463326 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 77073 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1540399 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1540399 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1215028 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1215028 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1463187 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 77093 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1540280 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1540280 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 50026128000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2483951500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52510079500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52510079500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 50020048000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2484862000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52504910000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52504910000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34186.591368 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32228.556044 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.683716 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32232.005500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480043 # number of replacements -system.cpu.l2cache.tagsinuse 31970.970884 # Cycle average of tags in use -system.cpu.l2cache.total_refs 85321 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512763 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.056401 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480006 # number of replacements +system.cpu.l2cache.tagsinuse 31970.917218 # Cycle average of tags in use +system.cpu.l2cache.total_refs 84924 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512726 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.056140 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 29004.040754 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2966.930131 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.885133 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.090544 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 76995 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106827 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 29008.328912 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2962.588306 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.885264 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.090411 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 76788 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 106544 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 6620 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 83615 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 83615 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1415326 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4368 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 66081 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1481407 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1481407 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48560731500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2252343000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50813074500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50813074500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1492321 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106827 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 4372 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72701 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1565022 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1565022 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.948406 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.999085 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908942 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.946573 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.946573 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34310.633381 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34084.578018 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34300.549748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34300.549748 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits 6616 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 83404 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 83404 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1415384 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4391 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 1481466 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1481466 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48555371000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2252634000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50808005000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50808005000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1492172 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 106544 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 4395 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 72698 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1564870 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1564870 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.948539 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.999090 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.908993 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.946702 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.946702 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34305.440078 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.465845 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34295.761766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34295.761766 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 25 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 25 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1415301 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4368 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66081 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1481382 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1481382 # number of overall MSHR misses +system.cpu.l2cache.writebacks 66099 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1415356 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4391 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1481438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1481438 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43971676000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 135408000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048571000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 46020247000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 46020247000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 43973863500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 136121000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 46022461000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 46022461000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948389 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999085 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908942 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.946557 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.946557 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31068.780422 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948521 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999090 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908993 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.946684 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.946684 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118653 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.907977 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 3a0a5fb16..64e40f331 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index c1184a1d5..46db9d24e 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,13 +1,11 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 12:28:18 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 18:34:35 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 31207726500 because target called exit() +Exiting @ tick 31183407000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 665110dd2..ceab52925 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.031208 # Number of seconds simulated -sim_ticks 31207726500 # Number of ticks simulated +sim_seconds 0.031183 # Number of seconds simulated +sim_ticks 31183407000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157603 # Simulator instruction rate (inst/s) -host_tick_rate 48874778 # Simulator tick rate (ticks/s) -host_mem_usage 225884 # Number of bytes of host memory used -host_seconds 638.52 # Real time elapsed on the host -sim_insts 100633520 # Number of instructions simulated +host_inst_rate 167832 # Simulator instruction rate (inst/s) +host_tick_rate 52006067 # Simulator tick rate (ticks/s) +host_mem_usage 223216 # Number of bytes of host memory used +host_seconds 599.61 # Real time elapsed on the host +sim_insts 100634165 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 62415454 # number of cpu cycles simulated +system.cpu.numCycles 62366815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17712573 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11586024 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 828480 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15104552 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9800008 # Number of BTB hits +system.cpu.BPredUnit.lookups 17631068 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11525225 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 822451 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15041021 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9743390 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1894610 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 179140 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13000723 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88894307 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17712573 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11694618 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 23068870 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2942261 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 22994151 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1125 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12237155 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 232722 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 61101347 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.028542 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.080485 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1887340 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 176888 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12968459 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88523933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17631068 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11630730 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22984896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2898005 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 23107334 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 525 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12208408 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 230644 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 61059715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.021356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.077680 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 38048418 62.27% 62.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2437383 3.99% 66.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2590379 4.24% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2495519 4.08% 74.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1726071 2.82% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1712649 2.80% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1014415 1.66% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1324144 2.17% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9752369 15.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38090584 62.38% 62.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2437224 3.99% 66.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2605062 4.27% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2470326 4.05% 74.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1717744 2.81% 77.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1704134 2.79% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1004081 1.64% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1295541 2.12% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9735019 15.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 61101347 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.283785 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.424236 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14911699 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 21729904 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21442913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1077075 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1939756 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3477546 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120762342 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 332405 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1939756 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16842041 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2003570 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15407287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20561842 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4346851 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117493872 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 61059715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.282700 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.419408 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14872380 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 21838408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21376813 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1070090 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1902024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3467429 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98061 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120316029 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 332599 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1902024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16801594 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2005674 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15516104 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20489827 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4344492 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117017437 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3565 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3003461 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 318 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 119392349 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 540581981 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 540487699 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 94282 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99143301 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20249043 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 768563 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 768716 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12082768 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29799998 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22399772 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2425661 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3419073 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112105098 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 764637 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107812126 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 316132 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12020521 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30346065 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 63680 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 61101347 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.764480 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.904021 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 3607 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2996198 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 60 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 118959985 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 538237718 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 538236225 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1493 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99144333 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 19815652 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 778147 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 778546 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12135199 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29749057 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22305499 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2463618 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3436887 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111737256 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 774255 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107616850 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 306406 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11658627 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29328565 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 71223 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 61059715 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.762485 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.902924 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22159484 36.27% 36.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11621982 19.02% 55.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8561362 14.01% 69.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7410232 12.13% 81.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4801172 7.86% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3527397 5.77% 95.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1679086 2.75% 97.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 804521 1.32% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 536111 0.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22160160 36.29% 36.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11614525 19.02% 55.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8577298 14.05% 69.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7396039 12.11% 81.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4782616 7.83% 89.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3521695 5.77% 95.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1664317 2.73% 97.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 809749 1.33% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 533316 0.87% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 61101347 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 61059715 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 88099 3.31% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1498283 56.35% 59.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1072737 40.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 88066 3.33% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1488278 56.33% 59.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1065734 40.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57136904 53.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 87447 0.08% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29022906 26.92% 80.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21564833 20.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57002654 52.97% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 87399 0.08% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 39 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28992824 26.94% 79.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21533927 20.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107812126 # Type of FU issued -system.cpu.iq.rate 1.727331 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2659119 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024664 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 279700662 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124905792 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105547410 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 188 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110471148 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1884692 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107616850 # Type of FU issued +system.cpu.iq.rate 1.725547 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2642078 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024551 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 279241693 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124185257 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105412682 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 206 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 204 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110258821 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 107 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1870348 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2491561 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3411 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16339 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1842707 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2440492 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3482 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 15956 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1748305 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 62 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1939756 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 952120 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112946418 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 627319 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29799998 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22399772 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 747490 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1210 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1207 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16339 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 688631 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 200572 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 889203 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106427513 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28649084 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1384613 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1902024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 953128 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28578 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112587966 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 618611 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29749057 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22305499 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 756996 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1135 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1192 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 15956 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 682416 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 198748 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 881164 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106274273 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28622040 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1342577 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 76683 # number of nop insts executed -system.cpu.iew.exec_refs 49896710 # number of memory reference insts executed -system.cpu.iew.exec_branches 14628801 # Number of branches executed -system.cpu.iew.exec_stores 21247626 # Number of stores executed -system.cpu.iew.exec_rate 1.705147 # Inst execution rate -system.cpu.iew.wb_sent 105874797 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105547479 # cumulative count of insts written-back -system.cpu.iew.wb_producers 52578934 # num instructions producing a value -system.cpu.iew.wb_consumers 101387160 # num instructions consuming a value +system.cpu.iew.exec_nop 76455 # number of nop insts executed +system.cpu.iew.exec_refs 49853649 # number of memory reference insts executed +system.cpu.iew.exec_branches 14601408 # Number of branches executed +system.cpu.iew.exec_stores 21231609 # Number of stores executed +system.cpu.iew.exec_rate 1.704020 # Inst execution rate +system.cpu.iew.wb_sent 105725224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105412758 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52507879 # num instructions producing a value +system.cpu.iew.wb_consumers 101154765 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.691047 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.518596 # average fanout of values written-back +system.cpu.iew.wb_rate 1.690206 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.519085 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100639072 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 12225024 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 700957 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 794036 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 59161592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.701088 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.430633 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100639717 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11948697 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 703032 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 788200 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 59157692 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.701211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.430896 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 26262806 44.39% 44.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14615219 24.70% 69.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4224786 7.14% 76.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3635680 6.15% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2285256 3.86% 86.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1889118 3.19% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 706435 1.19% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 496319 0.84% 91.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5045973 8.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 26246617 44.37% 44.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14635662 24.74% 69.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4223894 7.14% 76.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3641491 6.16% 82.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2268632 3.83% 86.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1889350 3.19% 89.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703853 1.19% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 498146 0.84% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5050047 8.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 59161592 # Number of insts commited each cycle -system.cpu.commit.count 100639072 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 59157692 # Number of insts commited each cycle +system.cpu.commit.count 100639717 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865501 # Number of memory references committed -system.cpu.commit.loads 27308436 # Number of loads committed +system.cpu.commit.refs 47865759 # Number of memory references committed +system.cpu.commit.loads 27308565 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13669955 # Number of branches committed +system.cpu.commit.branches 13670084 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91478095 # Number of committed integer instructions. +system.cpu.commit.int_insts 91478611 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5045973 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5050047 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 166954416 # The number of ROB reads -system.cpu.rob.rob_writes 227673782 # The number of ROB writes -system.cpu.timesIdled 61616 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1314107 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100633520 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633520 # Number of Instructions Simulated -system.cpu.cpi 0.620225 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.620225 # CPI: Total CPI of All Threads -system.cpu.ipc 1.612317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.612317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512325342 # number of integer regfile reads -system.cpu.int_regfile_writes 104042616 # number of integer regfile writes -system.cpu.fp_regfile_reads 124 # number of floating regfile reads -system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.misc_regfile_reads 146636710 # number of misc regfile reads -system.cpu.misc_regfile_writes 34494 # number of misc regfile writes -system.cpu.icache.replacements 26059 # number of replacements -system.cpu.icache.tagsinuse 1807.414724 # Cycle average of tags in use -system.cpu.icache.total_refs 12207911 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28088 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 434.630839 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 166670760 # The number of ROB reads +system.cpu.rob.rob_writes 227084538 # The number of ROB writes +system.cpu.timesIdled 61622 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1307100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100634165 # Number of Instructions Simulated +system.cpu.committedInsts_total 100634165 # Number of Instructions Simulated +system.cpu.cpi 0.619738 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.619738 # CPI: Total CPI of All Threads +system.cpu.ipc 1.613585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.613585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511657086 # number of integer regfile reads +system.cpu.int_regfile_writes 103892124 # number of integer regfile writes +system.cpu.fp_regfile_reads 166 # number of floating regfile reads +system.cpu.fp_regfile_writes 126 # number of floating regfile writes +system.cpu.misc_regfile_reads 146210782 # number of misc regfile reads +system.cpu.misc_regfile_writes 34752 # number of misc regfile writes +system.cpu.icache.replacements 26083 # number of replacements +system.cpu.icache.tagsinuse 1805.405384 # Cycle average of tags in use +system.cpu.icache.total_refs 12179175 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 28115 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 433.191357 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1807.414724 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.882527 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12207928 # number of ReadReq hits -system.cpu.icache.demand_hits 12207928 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12207928 # number of overall hits -system.cpu.icache.ReadReq_misses 29227 # number of ReadReq misses -system.cpu.icache.demand_misses 29227 # number of demand (read+write) misses -system.cpu.icache.overall_misses 29227 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 359488500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 359488500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 359488500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12237155 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12237155 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12237155 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002388 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002388 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002388 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12299.876826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12299.876826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12299.876826 # average overall miss latency +system.cpu.icache.occ_blocks::0 1805.405384 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.881546 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12179178 # number of ReadReq hits +system.cpu.icache.demand_hits 12179178 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12179178 # number of overall hits +system.cpu.icache.ReadReq_misses 29230 # number of ReadReq misses +system.cpu.icache.demand_misses 29230 # number of demand (read+write) misses +system.cpu.icache.overall_misses 29230 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 357885000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 357885000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 357885000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12208408 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12208408 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12208408 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002394 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002394 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002394 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12243.756415 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12243.756415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12243.756415 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,67 +354,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1106 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1106 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1106 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 28121 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 28121 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 28121 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1069 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1069 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 28161 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 28161 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 28161 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 247525500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 247525500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 247525500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 246973000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 246973000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 246973000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002298 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002298 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002298 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8802.158529 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.002307 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002307 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002307 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8770.036575 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157957 # number of replacements -system.cpu.dcache.tagsinuse 4072.327719 # Cycle average of tags in use -system.cpu.dcache.total_refs 44754174 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162053 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 276.169981 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 306664000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4072.327719 # Average occupied blocks per context +system.cpu.dcache.replacements 157879 # number of replacements +system.cpu.dcache.tagsinuse 4072.329363 # Cycle average of tags in use +system.cpu.dcache.total_refs 44742203 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 161975 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 276.229066 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 306596000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4072.329363 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26407726 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18310440 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 18642 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17246 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 44718166 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 44718166 # number of overall hits -system.cpu.dcache.ReadReq_misses 109117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1539461 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 29 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1648578 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1648578 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2423500000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 52284424500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 398000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 54707924500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 54707924500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 26516843 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 26395464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18310275 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 18919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17375 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 44705739 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 44705739 # number of overall hits +system.cpu.dcache.ReadReq_misses 108834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1539626 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1648460 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1648460 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2418698500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 52283649500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 386000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 54702348000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 54702348000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 26504298 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 18671 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17246 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46366744 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46366744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004115 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.077555 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001553 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035555 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035555 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22210.104750 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33962.811984 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13724.137931 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33184.917244 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33184.917244 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 18946 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17375 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46354199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46354199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001425 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035562 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035562 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22223.739824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33958.668859 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14296.296296 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33183.909831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33183.909831 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,74 +423,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123460 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 53919 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1432572 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 29 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1486491 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1486491 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55198 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106889 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 162087 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 162087 # number of overall MSHR misses +system.cpu.dcache.writebacks 123472 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 53734 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1432703 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1486437 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1486437 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 55100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106923 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 162023 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 162023 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1037796500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3662032500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4699829000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4699829000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1035726000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3662471000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4698197000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4698197000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002082 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003496 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003496 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18801.342440 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34260.143700 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005387 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18797.205082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.350542 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114992 # number of replacements -system.cpu.l2cache.tagsinuse 18307.930672 # Cycle average of tags in use -system.cpu.l2cache.total_refs 72391 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133845 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.540857 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114920 # number of replacements +system.cpu.l2cache.tagsinuse 18304.700184 # Cycle average of tags in use +system.cpu.l2cache.total_refs 72415 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.541323 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2377.365392 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15930.565280 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072551 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486162 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 50505 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123461 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 12 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4300 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 54805 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 54805 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32740 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 21 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102589 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 135329 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 135329 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1120810000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3525271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4646081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4646081500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 83245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123461 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 33 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106889 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 190134 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 190134 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.393297 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959771 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.711756 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.711756 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34233.659133 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.055493 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34331.750770 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34331.750770 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2370.650310 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15934.049874 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072347 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486269 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 50510 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123473 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 16 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 54819 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 54819 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32664 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 31 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 135262 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 135262 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1118309000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3526121000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4644430000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4644430000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 83174 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123473 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 47 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 190081 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 190081 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.392719 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.659574 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.711602 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.711602 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34236.743816 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.321020 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34336.546850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34336.546850 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88460 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 79 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 79 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 79 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32661 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 21 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102589 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 135250 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 135250 # number of overall MSHR misses +system.cpu.l2cache.writebacks 88456 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 80 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32584 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 135182 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 135182 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1015115500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 652000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3196978500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4212094000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4212094000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1012754000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 962000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197891500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4210645500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4210645500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392348 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959771 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.711340 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.711340 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.355776 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31047.619048 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31162.975563 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391757 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.659574 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.711181 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.711181 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.328259 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31032.258065 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.140724 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index f40a3547d..dcd4bf473 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,7 +62,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout index c5450c656..746f2d87f 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:19:11 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:17:49 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index be6b34c01..2fa280f51 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.068149 # Number of seconds simulated sim_ticks 68148678500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2568565 # Simulator instruction rate (inst/s) -host_tick_rate 1285774138 # Simulator tick rate (ticks/s) -host_mem_usage 229364 # Number of bytes of host memory used -host_seconds 53.00 # Real time elapsed on the host +host_inst_rate 3860753 # Simulator instruction rate (inst/s) +host_tick_rate 1932617843 # Simulator tick rate (ticks/s) +host_mem_usage 204428 # Number of bytes of host memory used +host_seconds 35.26 # Real time elapsed on the host sim_insts 136139203 # Number of instructions simulated system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 136297358 # number of cpu cycles simulated @@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 8898970 # nu system.cpu.num_int_insts 115187758 # number of integer instructions system.cpu.num_fp_insts 2326977 # number of float instructions system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read -system.cpu.num_int_register_writes 113225733 # number of times the integer registers were written +system.cpu.num_int_register_writes 113147747 # number of times the integer registers were written system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written system.cpu.num_mem_refs 58160249 # number of memory refs diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index ef97a0705..51f71312a 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,7 +165,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index 81a020192..7c4300466 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:15:05 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 5c7b8642c..15f83a274 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.202942 # Number of seconds simulated sim_ticks 202941992000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 927071 # Simulator instruction rate (inst/s) -host_tick_rate 1381979289 # Simulator tick rate (ticks/s) -host_mem_usage 238016 # Number of bytes of host memory used -host_seconds 146.85 # Real time elapsed on the host +host_inst_rate 2092270 # Simulator instruction rate (inst/s) +host_tick_rate 3118935472 # Simulator tick rate (ticks/s) +host_mem_usage 213400 # Number of bytes of host memory used +host_seconds 65.07 # Real time elapsed on the host sim_insts 136139203 # Number of instructions simulated system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 405883984 # number of cpu cycles simulated @@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 8898970 # nu system.cpu.num_int_insts 115187758 # number of integer instructions system.cpu.num_fp_insts 2326977 # number of float instructions system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read -system.cpu.num_int_register_writes 113225732 # number of times the integer registers were written +system.cpu.num_int_register_writes 113147746 # number of times the integer registers were written system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written system.cpu.num_mem_refs 58160249 # number of memory refs diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 93cd8d25f..0e065d7b6 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index bf70270df..0aaab6517 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 11 2011 21:12:14 -gem5 started Sep 11 2011 22:28:54 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 18:44:48 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 483520764000 because target called exit() +Exiting @ tick 483463019500 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 24e250396..42652cb1d 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.483521 # Number of seconds simulated -sim_ticks 483520764000 # Number of ticks simulated +sim_seconds 0.483463 # Number of seconds simulated +sim_ticks 483463019500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88254 # Simulator instruction rate (inst/s) -host_tick_rate 24765480 # Simulator tick rate (ticks/s) -host_mem_usage 263692 # Number of bytes of host memory used -host_seconds 19523.98 # Real time elapsed on the host +host_inst_rate 167165 # Simulator instruction rate (inst/s) +host_tick_rate 46903472 # Simulator tick rate (ticks/s) +host_mem_usage 214756 # Number of bytes of host memory used +host_seconds 10307.62 # Real time elapsed on the host sim_insts 1723073849 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,141 +51,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 967041529 # number of cpu cycles simulated +system.cpu.numCycles 966926040 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 298900449 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 243980938 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18344304 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264330532 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 238781777 # Number of BTB hits +system.cpu.BPredUnit.lookups 298898243 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 243989412 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18339920 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 264347245 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 238745657 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 17662867 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3505 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295983189 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2175588902 # Number of instructions fetch has processed -system.cpu.fetch.Branches 298900449 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 256444644 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 484812336 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87085918 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 107601139 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 294 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285066920 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5311321 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 956724152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.521766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.026486 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 17668157 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3423 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 295953389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2175230772 # Number of instructions fetch has processed +system.cpu.fetch.Branches 298898243 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 256413814 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 484717826 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87053301 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 107577195 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 285045078 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5311594 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 956547645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.521914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.026495 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 471911868 49.33% 49.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 35379148 3.70% 53.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 65139184 6.81% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 66872594 6.99% 66.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 46913058 4.90% 71.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 59711536 6.24% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 54259656 5.67% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 17705492 1.85% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 138831616 14.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 471829873 49.33% 49.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35367236 3.70% 53.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 65085859 6.80% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 66860371 6.99% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 46850107 4.90% 71.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 59747954 6.25% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 54343246 5.68% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17692463 1.85% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 138770536 14.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 956724152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309088 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.249737 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 323003673 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92138171 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 459624740 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13631035 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68326533 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46888019 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2352946295 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2296 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68326533 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343140693 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46558738 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19729 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 451876616 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46801843 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2296129706 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2700855 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 37763142 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 956547645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309122 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.249635 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 322987122 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92097194 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 459538157 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13626726 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68298446 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46874540 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 671 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2352694278 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2235 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68298446 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343127088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46537686 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27220 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 451783493 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46773712 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2295847883 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19963 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2697037 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 37730930 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264720698 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10606897757 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10606896049 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1708 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 2264588148 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10605407368 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10605405778 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1590 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558400742 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 819 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 812 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 98759000 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 618794544 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222188124 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 74432694 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 62140550 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2187930244 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 806 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018487398 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3289652 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 458712680 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1051172668 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 349 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 956724152 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.109790 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.840040 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 558268197 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 10043 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10038 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 98804137 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 618742816 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222099567 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 74239442 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 61602093 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2187718033 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2090 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018498325 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3274725 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 458502719 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1049949895 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1587 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 956547645 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.110191 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.840946 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 261965292 27.38% 27.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150944559 15.78% 43.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 168632678 17.63% 60.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 136410439 14.26% 75.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125113434 13.08% 88.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73446986 7.68% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 29046356 3.04% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10235900 1.07% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 928508 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262039584 27.39% 27.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150878554 15.77% 43.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 168430661 17.61% 60.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 136432052 14.26% 75.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124835406 13.05% 88.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73540708 7.69% 95.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 29241453 3.06% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10225405 1.07% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 923822 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 956724152 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 956547645 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 898312 3.71% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 170 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18874903 77.94% 81.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4444569 18.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 901388 3.68% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 177 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19016870 77.70% 81.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4557312 18.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238989796 61.38% 61.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1018767 0.05% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1238993791 61.38% 61.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1017752 0.05% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued @@ -207,91 +207,91 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 11 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 1 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 14 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 13 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 2 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 583947158 28.93% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194531653 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 583952461 28.93% 90.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194534287 9.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018487398 # Type of FU issued -system.cpu.iq.rate 2.087281 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24217954 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011998 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021206278 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2646821889 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958327848 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 276 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042705213 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55649565 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018498325 # Type of FU issued +system.cpu.iq.rate 2.087542 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24475747 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012126 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021294480 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2646401011 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958335598 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042973928 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 55719619 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 132867772 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 211365 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180609 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 47341078 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 132816045 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 210497 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180679 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 47252521 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 452178 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 451790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68326533 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22149991 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1213461 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2187949319 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7278781 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 618794544 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222188124 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 743 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219838 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 61091 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180609 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18951981 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1826621 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20778602 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986068567 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570288882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 32418831 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68298446 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22155006 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1213609 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2187738627 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7300026 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 618742816 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222099567 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2027 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219640 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 61277 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180679 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18953795 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1821941 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 20775736 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986087052 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 570299160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 32411273 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 18269 # number of nop insts executed -system.cpu.iew.exec_refs 761473758 # number of memory reference insts executed -system.cpu.iew.exec_branches 238644907 # Number of branches executed -system.cpu.iew.exec_stores 191184876 # Number of stores executed -system.cpu.iew.exec_rate 2.053757 # Inst execution rate -system.cpu.iew.wb_sent 1967261719 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958327963 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1288121662 # num instructions producing a value -system.cpu.iew.wb_consumers 2036910460 # num instructions consuming a value +system.cpu.iew.exec_nop 18504 # number of nop insts executed +system.cpu.iew.exec_refs 761501875 # number of memory reference insts executed +system.cpu.iew.exec_branches 238650211 # Number of branches executed +system.cpu.iew.exec_stores 191202715 # Number of stores executed +system.cpu.iew.exec_rate 2.054022 # Inst execution rate +system.cpu.iew.wb_sent 1967277607 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958335722 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1288034280 # num instructions producing a value +system.cpu.iew.wb_consumers 2036866160 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.025071 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.632390 # average fanout of values written-back +system.cpu.iew.wb_rate 2.025321 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.632361 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 464956551 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 457 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18344332 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888397620 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.939530 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.671610 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 464746992 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 18339818 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888249200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.939854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.672088 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 383037346 43.12% 43.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 200906061 22.61% 65.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 81946763 9.22% 74.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 38644775 4.35% 79.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19780530 2.23% 81.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30949131 3.48% 85.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22271905 2.51% 87.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12048122 1.36% 88.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98812987 11.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 383075847 43.13% 43.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 200735352 22.60% 65.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 81917807 9.22% 74.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 38649475 4.35% 79.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19675094 2.22% 81.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 31029952 3.49% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22284246 2.51% 87.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12052552 1.36% 88.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98828875 11.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888397620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888249200 # Number of insts commited each cycle system.cpu.commit.count 1723073867 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 660773817 # Number of memory references committed @@ -301,50 +301,50 @@ system.cpu.commit.branches 213462365 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98812987 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98828875 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2977614452 # The number of ROB reads -system.cpu.rob.rob_writes 4444617859 # The number of ROB writes -system.cpu.timesIdled 920049 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10317377 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2977240585 # The number of ROB reads +system.cpu.rob.rob_writes 4444170390 # The number of ROB writes +system.cpu.timesIdled 920776 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10378395 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1723073849 # Number of Instructions Simulated system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated -system.cpu.cpi 0.561230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561230 # CPI: Total CPI of All Threads -system.cpu.ipc 1.781799 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.781799 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9941893014 # number of integer regfile reads -system.cpu.int_regfile_writes 1939859629 # number of integer regfile writes -system.cpu.fp_regfile_reads 106 # number of floating regfile reads -system.cpu.fp_regfile_writes 43 # number of floating regfile writes -system.cpu.misc_regfile_reads 2914173755 # number of misc regfile reads +system.cpu.cpi 0.561163 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561163 # CPI: Total CPI of All Threads +system.cpu.ipc 1.782012 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.782012 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9942029327 # number of integer regfile reads +system.cpu.int_regfile_writes 1939848996 # number of integer regfile writes +system.cpu.fp_regfile_reads 117 # number of floating regfile reads +system.cpu.fp_regfile_writes 59 # number of floating regfile writes +system.cpu.misc_regfile_reads 2913839911 # number of misc regfile reads system.cpu.misc_regfile_writes 126 # number of misc regfile writes system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 611.960208 # Cycle average of tags in use -system.cpu.icache.total_refs 285065889 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 382125.856568 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 609.858480 # Cycle average of tags in use +system.cpu.icache.total_refs 285044064 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 383123.741935 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 611.960208 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.298809 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 285065889 # number of ReadReq hits -system.cpu.icache.demand_hits 285065889 # number of demand (read+write) hits -system.cpu.icache.overall_hits 285065889 # number of overall hits -system.cpu.icache.ReadReq_misses 1031 # number of ReadReq misses -system.cpu.icache.demand_misses 1031 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1031 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35526500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35526500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35526500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 285066920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 285066920 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 285066920 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 609.858480 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.297782 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 285044064 # number of ReadReq hits +system.cpu.icache.demand_hits 285044064 # number of demand (read+write) hits +system.cpu.icache.overall_hits 285044064 # number of overall hits +system.cpu.icache.ReadReq_misses 1014 # number of ReadReq misses +system.cpu.icache.demand_misses 1014 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1014 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35191500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35191500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35191500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 285045078 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 285045078 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 285045078 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34458.292919 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34458.292919 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34458.292919 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34705.621302 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34705.621302 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34705.621302 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,169 +354,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 285 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 285 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 744 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 744 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 744 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25635000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25627000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25627000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34363.270777 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34444.892473 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9570715 # number of replacements -system.cpu.dcache.tagsinuse 4087.762174 # Cycle average of tags in use -system.cpu.dcache.total_refs 666971462 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9574811 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 69.658969 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3484394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.762174 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 499575855 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167395484 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits +system.cpu.dcache.replacements 9570827 # number of replacements +system.cpu.dcache.tagsinuse 4087.732038 # Cycle average of tags in use +system.cpu.dcache.total_refs 666909210 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9574923 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 69.651653 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3484303000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.732038 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 499513800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 167395288 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 666971339 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 666971339 # number of overall hits -system.cpu.dcache.ReadReq_misses 10446749 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5190563 # number of WriteReq misses +system.cpu.dcache.demand_hits 666909088 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 666909088 # number of overall hits +system.cpu.dcache.ReadReq_misses 10448466 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 5190759 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15637312 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15637312 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 184495426500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 128540257604 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15639225 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15639225 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 184465722500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 128555474171 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 313035684104 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 313035684104 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 510022604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 313021196671 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 313021196671 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 509962266 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 64 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 682608651 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 682608651 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.020483 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.030075 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.046875 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.022908 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.022908 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 17660.558945 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24764.222610 # average WriteReq miss latency +system.cpu.dcache.demand_accesses 682548313 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 682548313 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.020489 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.022913 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.022913 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 17654.813874 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24766.219000 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 20018.509837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 20018.509837 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 267225153 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 90802 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency 20015.134808 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 20015.134808 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 266703683 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 90656 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2942.943470 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16583.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2941.930848 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16333.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3128462 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2764582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3297919 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 3128328 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2766203 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3298099 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6062501 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6062501 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7682167 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892644 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9574811 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9574811 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 6064302 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6064302 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7682263 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1892660 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9574923 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9574923 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 92043723000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 45263737820 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 137307460820 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 137307460820 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 92044930000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 45262385908 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 137307315908 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 137307315908 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015062 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015064 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.014027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.014027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.479054 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.611082 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.486445 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23914.694614 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2927649 # number of replacements -system.cpu.l2cache.tagsinuse 26780.067409 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7851232 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2954973 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.656956 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 102089125500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15983.054222 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10797.013187 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.487764 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.329499 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5655215 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3128462 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980262 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6635477 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6635477 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2027697 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 912383 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2940080 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2940080 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69611953000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31645995500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 101257948500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 101257948500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7682912 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3128462 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892645 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9575557 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9575557 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263923 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.482068 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.307040 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.307040 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34330.549880 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.990295 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34440.541924 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34440.541924 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 56517000 # number of cycles access was blocked +system.cpu.l2cache.replacements 2927819 # number of replacements +system.cpu.l2cache.tagsinuse 26780.774124 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7851022 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2955142 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.656733 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 102041743500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15984.490640 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10796.283484 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487808 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.329476 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5655252 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3128328 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 980176 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6635428 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6635428 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2027753 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 912486 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2940239 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2940239 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 69614113000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 31648901500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 101263014500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 101263014500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7683005 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3128328 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1892662 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9575667 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9575667 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.263927 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.482118 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.307053 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.307053 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34330.666999 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.259813 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34440.402464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34440.402464 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 56231500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 6610 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6603 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8550.226929 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8516.053309 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1217515 # number of writebacks +system.cpu.l2cache.writebacks 1217598 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2027686 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 912383 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2940069 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2940069 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 2027742 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 912486 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2940228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2940228 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 63233834500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28812323000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 92046157500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 92046157500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 63235914500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815026500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 92050941000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 92050941000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263922 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482068 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.307039 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.307039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.220246 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.197552 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263926 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.307052 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.307052 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.384778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31578.595726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 342457a8b..e5f29e92c 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 7a94cf61c..e68aac2cc 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 12:28:18 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 18:53:02 +gem5 executing on u200540-lin command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2 @@ -25,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105782426500 because target called exit() +122 123 124 Exiting @ tick 105874925000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 9c02493cb..37554b8e7 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105782 # Number of seconds simulated -sim_ticks 105782426500 # Number of ticks simulated +sim_seconds 0.105875 # Number of seconds simulated +sim_ticks 105874925000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104930 # Simulator instruction rate (inst/s) -host_tick_rate 58832155 # Simulator tick rate (ticks/s) -host_mem_usage 220996 # Number of bytes of host memory used -host_seconds 1798.04 # Real time elapsed on the host -sim_insts 188667447 # Number of instructions simulated +host_inst_rate 114442 # Simulator instruction rate (inst/s) +host_tick_rate 64221605 # Simulator tick rate (ticks/s) +host_mem_usage 218340 # Number of bytes of host memory used +host_seconds 1648.59 # Real time elapsed on the host +sim_insts 188667572 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 211564854 # number of cpu cycles simulated +system.cpu.numCycles 211749851 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 102102959 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80693522 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9934423 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84198795 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79209656 # Number of BTB hits +system.cpu.BPredUnit.lookups 102127285 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80698368 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9933568 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84243150 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79257318 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4697254 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 112889 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44543100 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 416703604 # Number of instructions fetch has processed -system.cpu.fetch.Branches 102102959 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83906910 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 108778714 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 33211132 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 34936553 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 779 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4698618 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 111511 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 44551125 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 416786863 # Number of instructions fetch has processed +system.cpu.fetch.Branches 102127285 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83955936 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 108810185 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 33218375 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35074253 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 40617038 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2208646 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 211506610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137206 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.647564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 40624886 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2204416 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 211691341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.135529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.646861 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102929819 48.67% 48.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4598020 2.17% 50.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32955527 15.58% 66.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18221421 8.62% 75.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9181259 4.34% 79.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12523238 5.92% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8470282 4.00% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4319419 2.04% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 18307625 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 103083318 48.70% 48.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4611723 2.18% 50.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32955553 15.57% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18242297 8.62% 75.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9176940 4.34% 79.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12529739 5.92% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8472403 4.00% 89.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4322449 2.04% 91.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 18296919 8.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 211506610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.482608 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.969626 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53228641 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 33488153 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 100485702 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1214398 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23089716 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14176819 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166958 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 422710144 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 694356 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23089716 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62181422 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 455271 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28556828 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 92670031 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4553342 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 388732639 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2224138 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 666278753 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1657677699 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1639787081 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17890618 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061648 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 368217100 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2705646 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2657641 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23338281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 46771972 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16999423 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3794588 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2434419 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332719440 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2206649 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261972515 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1005249 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 143535623 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 342170938 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 571067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 211506610 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.238602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.491475 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 211691341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.482302 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.968298 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53244805 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 33622636 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 100506105 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1219607 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23098188 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14186059 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166456 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 422686981 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 695509 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23098188 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62205667 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 461892 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28663713 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 92688664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4573217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 388586256 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 22473 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2248529 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 666261253 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1656600047 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1638859233 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17740814 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298061848 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 368199405 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2723713 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2675909 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23519864 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 46897665 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16902365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3883401 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2525721 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 332696460 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2225712 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261853052 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 956132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 143515224 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 342118821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 589705 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 211691341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.236957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.489139 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 97729672 46.21% 46.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 37811383 17.88% 64.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34093128 16.12% 80.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22769109 10.77% 90.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11443716 5.41% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4778532 2.26% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2323194 1.10% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 402147 0.19% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 155729 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 97854722 46.23% 46.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 37874169 17.89% 64.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34110087 16.11% 80.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22786114 10.76% 90.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11453676 5.41% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4761165 2.25% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2318956 1.10% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 393514 0.19% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 138938 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 211506610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 211691341 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 397392 17.88% 17.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5524 0.25% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 54 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 43 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1333839 60.01% 78.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 485736 21.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 398184 18.25% 18.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 54 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1324595 60.71% 79.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 453293 20.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 205005652 78.25% 78.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928362 0.35% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 5862 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33106 0.01% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166621 0.06% 78.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 256879 0.10% 78.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76399 0.03% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467584 0.18% 78.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207638 0.08% 79.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71818 0.03% 79.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 328 0.00% 79.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40692198 15.53% 94.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14060068 5.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 204944335 78.27% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 928862 0.35% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166569 0.06% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 257495 0.10% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76397 0.03% 78.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 468208 0.18% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207568 0.08% 79.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71821 0.03% 79.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 40739224 15.56% 94.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13959176 5.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261972515 # Type of FU issued -system.cpu.iq.rate 1.238261 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2222588 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008484 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 734922033 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 476231649 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 242866615 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3757444 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2242269 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1844486 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262305042 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1890061 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 261853052 # Type of FU issued +system.cpu.iq.rate 1.236615 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2181696 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008332 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 734785745 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 476212492 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 242882419 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3749528 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2237188 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1845400 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262148601 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1886147 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1588917 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16920299 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31179 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12638 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4352602 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17045968 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31330 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12732 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4255519 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 21 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 19 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23089716 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13717 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1061 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334979671 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3743340 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 46771972 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16999423 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2182801 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 23098188 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13857 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 833 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334975630 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3751995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 46897665 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16902365 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2201836 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 328 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12638 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9998550 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1696549 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11695099 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 249247765 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38548373 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12724750 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 12732 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9997150 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1695546 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11692696 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 249230612 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 38607191 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12622440 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53582 # number of nop insts executed -system.cpu.iew.exec_refs 52189835 # number of memory reference insts executed -system.cpu.iew.exec_branches 52589546 # Number of branches executed -system.cpu.iew.exec_stores 13641462 # Number of stores executed -system.cpu.iew.exec_rate 1.178115 # Inst execution rate -system.cpu.iew.wb_sent 246271273 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 244711101 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148454614 # num instructions producing a value -system.cpu.iew.wb_consumers 247957784 # num instructions consuming a value +system.cpu.iew.exec_nop 53458 # number of nop insts executed +system.cpu.iew.exec_refs 52205543 # number of memory reference insts executed +system.cpu.iew.exec_branches 52589382 # Number of branches executed +system.cpu.iew.exec_stores 13598352 # Number of stores executed +system.cpu.iew.exec_rate 1.177005 # Inst execution rate +system.cpu.iew.wb_sent 246260336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 244727819 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148531018 # num instructions producing a value +system.cpu.iew.wb_consumers 247826872 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.156672 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598709 # average fanout of values written-back +system.cpu.iew.wb_rate 1.155740 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.599334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188681835 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 146288700 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635582 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9795726 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 188416895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.001406 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.682967 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188681960 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146293697 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1636007 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9795278 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 188593154 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.000471 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.681076 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 105298145 55.89% 55.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 40798709 21.65% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19462081 10.33% 87.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8761911 4.65% 92.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4909468 2.61% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2009419 1.07% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1710426 0.91% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1008180 0.54% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4458556 2.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 105401505 55.89% 55.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 40855723 21.66% 77.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19482895 10.33% 87.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8763575 4.65% 92.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4920568 2.61% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2013461 1.07% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1707502 0.91% 97.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008267 0.53% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4439658 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 188416895 # Number of insts commited each cycle -system.cpu.commit.count 188681835 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 188593154 # Number of insts commited each cycle +system.cpu.commit.count 188681960 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498493 # Number of memory references committed -system.cpu.commit.loads 29851672 # Number of loads committed +system.cpu.commit.refs 42498543 # Number of memory references committed +system.cpu.commit.loads 29851697 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283870 # Number of branches committed +system.cpu.commit.branches 40283895 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150114973 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115073 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4458556 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4439658 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 518923673 # The number of ROB reads -system.cpu.rob.rob_writes 693093847 # The number of ROB writes -system.cpu.timesIdled 1715 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667447 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667447 # Number of Instructions Simulated -system.cpu.cpi 1.121364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.121364 # CPI: Total CPI of All Threads -system.cpu.ipc 0.891771 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.891771 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1112037925 # number of integer regfile reads -system.cpu.int_regfile_writes 407325224 # number of integer regfile writes -system.cpu.fp_regfile_reads 2928951 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497682 # number of floating regfile writes -system.cpu.misc_regfile_reads 502867512 # number of misc regfile reads -system.cpu.misc_regfile_writes 824410 # number of misc regfile writes -system.cpu.icache.replacements 1940 # number of replacements -system.cpu.icache.tagsinuse 1334.073699 # Cycle average of tags in use -system.cpu.icache.total_refs 40612809 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3646 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11139.004114 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 519123952 # The number of ROB reads +system.cpu.rob.rob_writes 693113124 # The number of ROB writes +system.cpu.timesIdled 1721 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58510 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667572 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667572 # Number of Instructions Simulated +system.cpu.cpi 1.122344 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.122344 # CPI: Total CPI of All Threads +system.cpu.ipc 0.890993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.890993 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1112090730 # number of integer regfile reads +system.cpu.int_regfile_writes 407417013 # number of integer regfile writes +system.cpu.fp_regfile_reads 2928432 # number of floating regfile reads +system.cpu.fp_regfile_writes 2499453 # number of floating regfile writes +system.cpu.misc_regfile_reads 503028333 # number of misc regfile reads +system.cpu.misc_regfile_writes 824460 # number of misc regfile writes +system.cpu.icache.replacements 1929 # number of replacements +system.cpu.icache.tagsinuse 1329.893683 # Cycle average of tags in use +system.cpu.icache.total_refs 40620654 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3638 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11165.655305 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1334.073699 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.651403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 40612809 # number of ReadReq hits -system.cpu.icache.demand_hits 40612809 # number of demand (read+write) hits -system.cpu.icache.overall_hits 40612809 # number of overall hits -system.cpu.icache.ReadReq_misses 4229 # number of ReadReq misses -system.cpu.icache.demand_misses 4229 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4229 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101377500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101377500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101377500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 40617038 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 40617038 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 40617038 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1329.893683 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.649362 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 40620654 # number of ReadReq hits +system.cpu.icache.demand_hits 40620654 # number of demand (read+write) hits +system.cpu.icache.overall_hits 40620654 # number of overall hits +system.cpu.icache.ReadReq_misses 4232 # number of ReadReq misses +system.cpu.icache.demand_misses 4232 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4232 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 101343500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 101343500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 101343500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 40624886 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 40624886 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 40624886 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23971.979191 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23971.979191 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23971.979191 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 23946.951796 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23946.951796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23946.951796 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,139 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 583 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 583 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 583 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3646 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3646 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3646 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3638 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74805000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74805000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74805000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74666000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20517.004937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20523.914239 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20523.914239 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20523.914239 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1408.142162 # Cycle average of tags in use -system.cpu.dcache.total_refs 48578921 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1851 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 26244.689897 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1403.749083 # Cycle average of tags in use +system.cpu.dcache.total_refs 48644661 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1849 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 26308.632234 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1408.142162 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343785 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 36170054 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356741 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27532 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 48526795 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 48526795 # number of overall hits -system.cpu.dcache.ReadReq_misses 1787 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7546 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1403.749083 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.342712 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 36235521 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356728 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27793 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24619 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 48592249 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 48592249 # number of overall hits +system.cpu.dcache.ReadReq_misses 1802 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7559 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9333 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9333 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59024500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236727000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 9361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9361 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59198500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 237194000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 295751500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 295751500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 36171841 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 296392500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 296392500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 36237323 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27534 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24594 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 48536128 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 48536128 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000073 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000192 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000192 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33029.938444 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31371.190034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 27795 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24619 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 48601610 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 48601610 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32851.553829 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31379.018389 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31688.792457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31688.792457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 31662.482641 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31662.482641 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 19 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1026 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 1044 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6468 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7482 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7482 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1090 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1851 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1851 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 7512 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7512 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 758 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1849 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1849 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24308000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62630000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62630000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62497000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62497000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.181340 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35157.798165 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31864.116095 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33800.432666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33800.432666 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1934.153388 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2689 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.637412 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1924.111202 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2681 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.638195 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1931.095297 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.058091 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058932 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 1920.073953 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 4.037248 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058596 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000123 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 19 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1723 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2693 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3774 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 92316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37162000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129478000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129478000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 1720 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1720 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2685 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 3767 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3767 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92055500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37184500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129240000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129240000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 19 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1090 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5497 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5497 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.611073 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991743 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.686556 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.686556 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34279.985147 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34377.428307 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34307.896131 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34307.896131 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 5487 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5487 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.610783 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.686532 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.686532 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34285.102421 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.451017 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34308.468277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34308.468277 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,24 +498,24 @@ system.cpu.l2cache.writebacks 0 # nu system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2679 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3760 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3760 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 2671 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 3753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3753 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83267000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33562000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116829000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116829000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83018000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116608000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116608000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607897 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.684009 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.684009 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.373647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31047.178538 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607598 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.683980 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.683980 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.242980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.610179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.610179 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index ee5b3b672..b59640844 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,7 +62,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index 705894fd8..a36de6b20 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:14:52 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index c1047d2b2..9a564c8ae 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.096723 # Number of seconds simulated sim_ticks 96722951500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2494224 # Simulator instruction rate (inst/s) -host_tick_rate 1247118942 # Simulator tick rate (ticks/s) -host_mem_usage 225000 # Number of bytes of host memory used -host_seconds 77.56 # Real time elapsed on the host +host_inst_rate 3820563 # Simulator instruction rate (inst/s) +host_tick_rate 1910292029 # Simulator tick rate (ticks/s) +host_mem_usage 200496 # Number of bytes of host memory used +host_seconds 50.63 # Real time elapsed on the host sim_insts 193444769 # Number of instructions simulated system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445904 # number of cpu cycles simulated @@ -19,8 +19,8 @@ system.cpu.num_func_calls 1957920 # nu system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls system.cpu.num_int_insts 167974818 # number of integer instructions system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read -system.cpu.num_int_register_writes 163703467 # number of times the integer registers were written +system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060137 # number of times the integer registers were written system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written system.cpu.num_mem_refs 76733959 # number of memory refs diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 89315cddc..6069e1413 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,7 +165,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index d8ad09e2a..1a7df931f 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:16:32 +gem5 compiled Nov 30 2011 17:14:16 +gem5 started Nov 30 2011 17:16:48 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 03f17b992..106cfd4f6 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.270577 # Number of seconds simulated sim_ticks 270576960000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1189238 # Simulator instruction rate (inst/s) -host_tick_rate 1663421950 # Simulator tick rate (ticks/s) -host_mem_usage 233652 # Number of bytes of host memory used -host_seconds 162.66 # Real time elapsed on the host +host_inst_rate 2077025 # Simulator instruction rate (inst/s) +host_tick_rate 2905196336 # Simulator tick rate (ticks/s) +host_mem_usage 209472 # Number of bytes of host memory used +host_seconds 93.14 # Real time elapsed on the host sim_insts 193444769 # Number of instructions simulated system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 541153920 # number of cpu cycles simulated @@ -19,8 +19,8 @@ system.cpu.num_func_calls 1957920 # nu system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls system.cpu.num_int_insts 167974818 # number of integer instructions system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read -system.cpu.num_int_register_writes 163703466 # number of times the integer registers were written +system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060136 # number of times the integer registers were written system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written system.cpu.num_mem_refs 76733959 # number of memory refs diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index cc2f70a95..395184da9 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -19,6 +19,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +memories=system.nvram system.physmem2 system.partition_desc system.physmem system.hypervisor_desc system.rom nvram=system.nvram nvram_addr=133429198848 nvram_bin=/dist/m5/system/binaries/nvram1 @@ -161,6 +162,7 @@ port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.phys [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=2 pio_size=8 @@ -233,6 +235,7 @@ system=system [system.t1000.fake_clk] type=IsaFake +fake_mem=false pio_addr=644245094400 pio_latency=2 pio_size=4294967296 @@ -249,6 +252,7 @@ pio=system.iobus.port[0] [system.t1000.fake_jbi] type=IsaFake +fake_mem=false pio_addr=549755813888 pio_latency=2 pio_size=4294967296 @@ -265,6 +269,7 @@ pio=system.iobus.port[11] [system.t1000.fake_l2_1] type=IsaFake +fake_mem=false pio_addr=725849473024 pio_latency=2 pio_size=8 @@ -281,6 +286,7 @@ pio=system.iobus.port[2] [system.t1000.fake_l2_2] type=IsaFake +fake_mem=false pio_addr=725849473088 pio_latency=2 pio_size=8 @@ -297,6 +303,7 @@ pio=system.iobus.port[3] [system.t1000.fake_l2_3] type=IsaFake +fake_mem=false pio_addr=725849473152 pio_latency=2 pio_size=8 @@ -313,6 +320,7 @@ pio=system.iobus.port[4] [system.t1000.fake_l2_4] type=IsaFake +fake_mem=false pio_addr=725849473216 pio_latency=2 pio_size=8 @@ -329,6 +337,7 @@ pio=system.iobus.port[5] [system.t1000.fake_l2esr_1] type=IsaFake +fake_mem=false pio_addr=734439407616 pio_latency=2 pio_size=8 @@ -345,6 +354,7 @@ pio=system.iobus.port[6] [system.t1000.fake_l2esr_2] type=IsaFake +fake_mem=false pio_addr=734439407680 pio_latency=2 pio_size=8 @@ -361,6 +371,7 @@ pio=system.iobus.port[7] [system.t1000.fake_l2esr_3] type=IsaFake +fake_mem=false pio_addr=734439407744 pio_latency=2 pio_size=8 @@ -377,6 +388,7 @@ pio=system.iobus.port[8] [system.t1000.fake_l2esr_4] type=IsaFake +fake_mem=false pio_addr=734439407808 pio_latency=2 pio_size=8 @@ -393,6 +405,7 @@ pio=system.iobus.port[9] [system.t1000.fake_membnks] type=IsaFake +fake_mem=false pio_addr=648540061696 pio_latency=2 pio_size=16384 @@ -409,6 +422,7 @@ pio=system.iobus.port[1] [system.t1000.fake_ssi] type=IsaFake +fake_mem=false pio_addr=1095216660480 pio_latency=2 pio_size=268435456 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 39438a2c7..6ef01a659 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout -Redirecting stderr to build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:35:14 -gem5 started Jun 12 2011 07:35:20 -gem5 executing on zizzer +gem5 compiled Nov 27 2011 04:34:45 +gem5 started Nov 27 2011 04:35:04 +gem5 executing on chips command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 4b265dc78..a8935aa0a 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -3,10 +3,10 @@ sim_seconds 1.116889 # Number of seconds simulated sim_ticks 2233777512 # Number of ticks simulated sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 2349387 # Simulator instruction rate (inst/s) -host_tick_rate 2354253 # Simulator tick rate (ticks/s) -host_mem_usage 524024 # Number of bytes of host memory used -host_seconds 948.83 # Real time elapsed on the host +host_inst_rate 941153 # Simulator instruction rate (inst/s) +host_tick_rate 943102 # Simulator tick rate (ticks/s) +host_mem_usage 535596 # Number of bytes of host memory used +host_seconds 2368.54 # Real time elapsed on the host sim_insts 2229160714 # Number of instructions simulated system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -18,8 +18,8 @@ system.cpu.num_func_calls 44037246 # nu system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls system.cpu.num_int_insts 1839325658 # number of integer instructions system.cpu.num_fp_insts 14608322 # number of float instructions -system.cpu.num_int_register_reads 4304894311 # number of times the integer registers were read -system.cpu.num_int_register_writes 2108336490 # number of times the integer registers were written +system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read +system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written system.cpu.num_mem_refs 547951940 # number of memory refs diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 6ed416710..35f7f2ba7 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index d350ca8e5..2cb4f1a9c 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 12:27:58 -gem5 started Aug 20 2011 13:15:14 -gem5 executing on zizzer -command line: ./build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing +gem5 compiled Nov 21 2011 16:28:02 +gem5 started Nov 22 2011 19:01:51 +gem5 executing on u200540-lin +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 9807000 because target called exit() +Exiting @ tick 10001500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 5bb9beb5c..3aaa40ec4 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 9807000 # Number of ticks simulated +sim_ticks 10001500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16610 # Simulator instruction rate (inst/s) -host_tick_rate 28382842 # Simulator tick rate (ticks/s) -host_mem_usage 221852 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host +host_inst_rate 48143 # Simulator instruction rate (inst/s) +host_tick_rate 83889434 # Simulator tick rate (ticks/s) +host_mem_usage 212568 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,244 +51,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 19615 # number of cpu cycles simulated +system.cpu.numCycles 20004 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2510 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1858 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1876 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 752 # Number of BTB hits +system.cpu.BPredUnit.lookups 2398 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6260 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12668 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2510 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1020 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1646 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1029 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.423992 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.773203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1920 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.338054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.716635 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8435 74.90% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.43% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 191 1.70% 79.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 2.18% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 240 2.13% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 319 2.83% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 123 1.09% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 122 1.08% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1312 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8816 76.59% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.95% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.97% 84.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 313 2.72% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127963 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.645832 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6543 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1078 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2628 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 952 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14071 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 952 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6829 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2400 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 182 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13225 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12790 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 60358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 59038 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 11510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119876 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.606579 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6265 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2491 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6541 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2270 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7101 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 440 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2690 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1760 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 41 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11414 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5140 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13918 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.824188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485862 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.438063 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7565 67.17% 67.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.85% 79.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 849 7.54% 86.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 557 4.95% 91.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 476 4.23% 95.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.47% 98.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 148 1.31% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.38% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8025 69.72% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11510 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.75% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 141 64.68% 67.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 32.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5672 61.11% 61.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2322 25.02% 86.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1278 13.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9282 # Type of FU issued -system.cpu.iq.rate 0.473209 # Inst issue rate -system.cpu.iq.fu_busy_cnt 218 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023486 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30073 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16544 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8314 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 8706 # Type of FU issued +system.cpu.iq.rate 0.435213 # Inst issue rate +system.cpu.iq.fu_busy_cnt 203 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29184 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 952 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11442 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 210 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2690 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1760 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 301 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 397 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8848 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2122 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 434 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_refs 3344 # number of memory reference insts executed -system.cpu.iew.exec_branches 1461 # Number of branches executed -system.cpu.iew.exec_stores 1222 # Number of stores executed -system.cpu.iew.exec_rate 0.451083 # Inst execution rate -system.cpu.iew.wb_sent 8506 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8330 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3963 # num instructions producing a value -system.cpu.iew.wb_consumers 7807 # num instructions consuming a value +system.cpu.iew.exec_nop 1 # number of nop insts executed +system.cpu.iew.exec_refs 3178 # number of memory reference insts executed +system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_stores 1169 # Number of stores executed +system.cpu.iew.exec_rate 0.414017 # Inst execution rate +system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7840 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3690 # num instructions producing a value +system.cpu.iew.wb_consumers 7291 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.424675 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.507621 # average fanout of values written-back +system.cpu.iew.wb_rate 0.391922 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5548 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.556590 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.365529 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.540192 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.352731 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7969 77.29% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1090 10.57% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 425 4.12% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 280 2.72% 94.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.77% 96.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 171 1.66% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.65% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 38 0.37% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8288 78.01% 78.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.95% 92.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10624 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed @@ -298,49 +298,49 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21353 # The number of ROB reads -system.cpu.rob.rob_writes 23544 # The number of ROB writes +system.cpu.rob.rob_reads 21207 # The number of ROB reads +system.cpu.rob.rob_writes 22566 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.417843 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.417843 # CPI: Total CPI of All Threads -system.cpu.ipc 0.292582 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.292582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40279 # number of integer regfile reads -system.cpu.int_regfile_writes 8179 # number of integer regfile writes -system.cpu.fp_regfile_reads 29 # number of floating regfile reads -system.cpu.misc_regfile_reads 15700 # number of misc regfile reads +system.cpu.cpi 3.485625 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.485625 # CPI: Total CPI of All Threads +system.cpu.ipc 0.286893 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.286893 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 37816 # number of integer regfile reads +system.cpu.int_regfile_writes 7658 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.misc_regfile_reads 14993 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 150.950866 # Cycle average of tags in use -system.cpu.icache.total_refs 1667 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.631757 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 148.864335 # Cycle average of tags in use +system.cpu.icache.total_refs 1560 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.252525 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 150.950866 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.073706 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1667 # number of ReadReq hits -system.cpu.icache.demand_hits 1667 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1667 # number of overall hits -system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses -system.cpu.icache.demand_misses 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.179222 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.179222 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.179222 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34663.461538 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34663.461538 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34663.461538 # average overall miss latency +system.cpu.icache.occ_blocks::0 148.864335 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.072688 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1560 # number of ReadReq hits +system.cpu.icache.demand_hits 1560 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1560 # number of overall hits +system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.icache.demand_misses 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1920 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1920 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.187500 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.187500 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.187500 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,67 +350,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9940000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9940000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9940000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33581.081081 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33581.081081 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.154688 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.154688 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.154688 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.326406 # Cycle average of tags in use -system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.500000 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.089443 # Cycle average of tags in use +system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.326406 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022541 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1789 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 89.089443 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021750 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 2398 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2398 # number of overall hits -system.cpu.dcache.ReadReq_misses 177 # number of ReadReq misses +system.cpu.dcache.demand_hits 2311 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2311 # number of overall hits +system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 481 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5493500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 473 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10725000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 16199000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16199000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 16075500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16075500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1871 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.090031 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2784 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2784 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.090326 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.167072 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167072 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31036.723164 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.169899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.169899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31659.763314 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35279.605263 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33677.754678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33677.754678 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33986.257928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33986.257928 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,64 +420,64 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 325 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 112 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4735000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4735000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.057986 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.059861 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.054185 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.054185 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.055316 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.055316 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 191.048911 # Cycle average of tags in use -system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.120549 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 191.048911 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005830 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits -system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 43 # number of overall hits +system.cpu.l2cache.occ_blocks::0 188.120549 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits +system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 42 # number of overall hits system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12611500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14062000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14062000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency 12613500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1452000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 14065500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14065500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 452 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.895122 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.897311 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34363.760218 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34381.418093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34381.418093 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.906874 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.906874 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34389.975550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34389.975550 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,17 +495,17 @@ system.cpu.l2cache.ReadExReq_mshr_misses 42 # nu system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11306000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11304000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1319000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885086 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31232.044199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.895787 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.895787 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index dc4523b69..9d8c34c47 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -458,7 +458,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 9264a5759..709d070a3 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout -Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:07:22 -gem5 started Aug 20 2011 13:07:32 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:13:49 +gem5 started Nov 21 2011 20:51:35 +gem5 executing on u200540-lin command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 101c2c9bd..faa6a7461 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.000104 # Number of seconds simulated sim_ticks 104317500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86437 # Simulator instruction rate (inst/s) -host_tick_rate 8848828 # Simulator tick rate (ticks/s) -host_mem_usage 223064 # Number of bytes of host memory used -host_seconds 11.79 # Real time elapsed on the host +host_inst_rate 97517 # Simulator instruction rate (inst/s) +host_tick_rate 9983124 # Simulator tick rate (ticks/s) +host_mem_usage 222460 # Number of bytes of host memory used +host_seconds 10.45 # Real time elapsed on the host sim_insts 1018993 # Number of instructions simulated system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 208636 # number of cpu cycles simulated @@ -656,6 +656,7 @@ system.cpu1.rob.rob_reads 446977 # Th system.cpu1.rob.rob_writes 572400 # The number of ROB writes system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 34329 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 231385 # Number of Instructions Simulated system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction @@ -1053,6 +1054,7 @@ system.cpu2.rob.rob_reads 425878 # Th system.cpu2.rob.rob_writes 535627 # The number of ROB writes system.cpu2.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 34616 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 215254 # Number of Instructions Simulated system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction @@ -1450,6 +1452,7 @@ system.cpu3.rob.rob_reads 392929 # Th system.cpu3.rob.rob_writes 465356 # The number of ROB writes system.cpu3.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 34882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu3.committedInsts 183965 # Number of Instructions Simulated system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index 116829bef..bbf4c512c 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000 type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing +memories=system.physmem system.funcmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 1aa89be3a..d120607c7 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jun/30/2011 15:23:20 +Real time: Dec/01/2011 11:06:07 Profiler Stats -------------- -Elapsed_time_in_seconds: 151 -Elapsed_time_in_minutes: 2.51667 -Elapsed_time_in_hours: 0.0419444 -Elapsed_time_in_days: 0.00174769 +Elapsed_time_in_seconds: 143 +Elapsed_time_in_minutes: 2.38333 +Elapsed_time_in_hours: 0.0397222 +Elapsed_time_in_days: 0.00165509 -Virtual_time_in_seconds: 150.32 -Virtual_time_in_minutes: 2.50533 -Virtual_time_in_hours: 0.0417556 -Virtual_time_in_days: 0.00173981 +Virtual_time_in_seconds: 142.63 +Virtual_time_in_minutes: 2.37717 +Virtual_time_in_hours: 0.0396194 +Virtual_time_in_days: 0.00165081 -Ruby_current_time: 19206609 +Ruby_current_time: 19175808 Ruby_start_time: 0 -Ruby_cycles: 19206609 +Ruby_cycles: 19175808 -mbytes_resident: 38.1719 -mbytes_total: 350.137 -resident_ratio: 0.109031 +mbytes_resident: 39.8008 +mbytes_total: 372.789 +resident_ratio: 0.106765 -ruby_cycles_executed: [ 19206610 19206610 19206610 19206610 19206610 19206610 19206610 19206610 ] +ruby_cycles_executed: [ 19175809 19175809 19175809 19175809 19175809 19175809 19175809 19175809 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,35 +66,35 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 617223 average: 15.9984 | standard deviation: 0.126769 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 617103 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 616306 average: 15.9984 | standard deviation: 0.126863 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 616186 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 18560 count: 617095 average: 3983.23 | standard deviation: 3091.48 | 1958 7234 12895 17218 16392 19324 21913 23040 20107 17635 18744 17664 14678 13253 11927 11510 9984 9094 8955 7366 7320 7020 7151 6384 5796 6150 6284 5849 5571 5411 5812 5515 5578 5752 5123 5366 5351 5690 5365 5155 5714 5985 5836 5810 5790 6196 6060 6028 6515 5987 6288 6464 6728 6464 5805 6373 6462 6286 5932 5787 5998 5754 5359 5554 4904 4842 4658 4654 4179 3712 3844 3635 3341 3043 2889 2846 2573 2269 2155 1811 1823 1648 1528 1310 1117 1148 1096 888 791 669 704 582 559 471 393 357 372 328 280 240 208 190 171 149 136 110 99 100 84 51 71 47 54 38 26 33 27 24 9 21 12 10 10 8 6 4 3 8 2 4 1 1 0 2 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 128 max: 18430 count: 400882 average: 3989 | standard deviation: 3091.45 | 1289 4698 8338 11139 10596 12561 14059 14947 12937 11454 12069 11542 9578 8485 7768 7478 6445 5914 5838 4795 4779 4612 4687 4121 3750 4070 4110 3828 3636 3589 3777 3595 3661 3728 3313 3503 3457 3720 3533 3351 3688 3862 3840 3738 3743 4006 3911 3986 4198 3877 4126 4244 4365 4178 3786 4167 4192 4144 3889 3837 3884 3679 3486 3586 3193 3136 3072 3020 2690 2412 2478 2326 2195 1935 1894 1881 1693 1468 1375 1186 1185 1062 976 865 733 739 718 581 515 442 455 374 368 306 265 247 234 227 190 160 143 115 111 97 96 72 59 65 58 29 45 32 34 32 17 21 16 12 6 14 8 8 4 6 4 1 2 5 0 3 0 1 0 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 128 max: 18560 count: 216213 average: 3972.51 | standard deviation: 3091.51 | 669 2536 4557 6079 5796 6763 7854 8093 7170 6181 6675 6122 5100 4768 4159 4032 3539 3180 3117 2571 2541 2408 2464 2263 2046 2080 2174 2021 1935 1822 2035 1920 1917 2024 1810 1863 1894 1970 1832 1804 2026 2123 1996 2072 2047 2190 2149 2042 2317 2110 2162 2220 2363 2286 2019 2206 2270 2142 2043 1950 2114 2075 1873 1968 1711 1706 1586 1634 1489 1300 1366 1309 1146 1108 995 965 880 801 780 625 638 586 552 445 384 409 378 307 276 227 249 208 191 165 128 110 138 101 90 80 65 75 60 52 40 38 40 35 26 22 26 15 20 6 9 12 11 12 3 7 4 2 6 2 2 3 1 3 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 137 average: 2 | standard deviation: 0 | 0 0 137 ] -miss_latency_L2Cache: [binsize: 32 max: 5122 count: 381 average: 718.126 | standard deviation: 886.594 | 138 12 4 4 2 1 4 3 4 1 3 1 4 6 4 12 11 3 7 5 6 3 7 4 3 2 2 9 3 3 5 4 4 2 1 1 0 4 2 1 2 4 3 2 4 2 3 2 3 2 1 6 3 0 0 1 3 1 1 1 3 1 2 2 1 3 2 2 0 1 0 1 0 1 2 0 1 1 0 0 0 1 0 2 0 0 0 1 0 0 2 2 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 2 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Directory: [binsize: 128 max: 18560 count: 596443 average: 4004.3 | standard deviation: 3090.24 | 0 6443 12193 16390 15511 18623 21339 22431 19595 17226 18360 17307 14378 13003 11647 11254 9740 8889 8722 7166 7133 6825 6966 6199 5607 5973 6104 5689 5403 5228 5646 5330 5391 5582 4935 5191 5179 5485 5177 4949 5520 5784 5630 5622 5591 5968 5859 5823 6304 5783 6092 6260 6507 6278 5613 6193 6289 6116 5750 5601 5813 5587 5219 5407 4746 4720 4544 4529 4055 3610 3747 3529 3267 2976 2813 2789 2504 2218 2115 1762 1793 1617 1498 1291 1089 1114 1073 872 782 653 691 573 551 464 387 352 363 324 277 238 204 186 167 147 132 109 99 99 84 48 71 46 54 38 26 32 26 24 9 21 12 10 9 8 6 4 3 7 2 4 1 1 0 2 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache_wCC: [binsize: 128 max: 16283 count: 20134 average: 3447.69 | standard deviation: 3066.86 | 1663 781 693 802 855 681 558 594 504 402 373 346 288 246 274 248 236 203 230 198 184 194 181 185 187 176 179 157 167 183 165 184 187 170 188 175 172 205 188 206 193 201 206 188 199 228 201 205 211 204 196 204 221 186 192 180 173 170 182 186 185 167 140 147 158 122 114 125 124 102 97 106 74 67 76 57 69 51 40 49 30 31 30 19 28 34 23 16 9 16 13 9 8 7 6 5 9 4 3 2 4 4 4 2 4 1 0 1 0 3 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 16251 count: 20094 average: 3266.72 | standard deviation: 3050.73 | 2471 881 768 988 710 626 531 553 384 280 301 287 238 235 214 225 201 190 216 173 190 184 159 171 178 162 179 161 159 163 193 179 158 178 178 187 185 216 193 186 208 195 211 214 175 232 200 214 208 188 180 241 205 183 185 188 192 188 162 180 156 153 152 141 133 100 126 109 113 73 89 80 62 60 75 53 50 42 34 36 34 32 21 19 21 27 14 14 9 9 8 13 5 8 3 5 6 2 2 3 6 2 3 3 0 2 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 32 max: 4797 count: 20094 average: 153.966 | standard deviation: 327.973 | 14427 323 273 311 242 171 230 200 267 190 189 176 186 226 208 196 183 155 163 104 109 95 81 100 85 86 82 80 89 68 67 61 56 68 32 36 39 30 30 24 20 23 25 24 27 27 16 18 21 9 9 11 11 10 3 9 8 5 6 12 7 4 2 3 3 4 3 2 0 3 1 0 3 1 3 0 0 1 1 1 2 3 0 2 0 2 1 1 0 1 0 0 1 0 1 0 0 2 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 35 count: 20094 average: 24.6147 | standard deviation: 1.1555 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14747 141 4595 55 186 190 140 16 10 12 0 2 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 15 count: 20094 average: 1.75132 | standard deviation: 1.59712 | 4681 5277 5118 3039 587 560 669 35 60 27 26 12 2 0 0 1 ] -imcomplete_wCC_Times: 40 -miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 17771 count: 596443 average: 3283.36 | standard deviation: 3055.79 | 72798 24883 23368 27946 21765 18407 16221 15718 11636 8834 8867 8466 7158 6513 6247 6520 5952 5752 5944 5382 5569 5346 5766 5366 4882 5316 5467 5197 5248 5017 5404 5211 5093 5513 4992 5389 5465 5873 5742 5352 5875 6155 6038 6113 5950 6465 6238 6262 6638 5830 6122 6167 6215 5879 5583 5750 5631 5339 5061 4719 4830 4371 4359 4195 3470 3558 3329 3292 2871 2471 2538 2367 2107 1920 1610 1620 1463 1327 1206 1050 887 874 786 692 586 619 559 454 380 346 346 247 240 249 197 183 166 150 116 113 90 91 70 58 62 45 39 37 33 27 24 13 18 9 6 12 8 5 5 10 5 2 1 1 2 2 1 2 0 0 1 1 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_dir_initial_forward_request: [binsize: 32 max: 3618 count: 596443 average: 11.5481 | standard deviation: 55.8855 | 593296 109 154 127 130 115 152 106 84 93 87 102 60 82 76 63 100 87 110 89 84 106 80 59 46 52 64 37 40 38 33 59 39 30 43 18 37 30 22 22 15 15 17 9 11 15 17 12 21 9 7 8 7 9 6 8 9 4 2 3 11 7 2 2 6 3 8 2 3 7 1 3 3 2 2 1 1 1 1 2 0 1 0 0 3 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 41 count: 596443 average: 24.8313 | standard deviation: 1.27996 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 382893 5021 183701 1553 7759 8400 5678 618 367 272 88 61 26 3 0 1 1 1 ] -miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4597 count: 596443 average: 684.559 | standard deviation: 463.144 | 0 0 0 14606 19430 17327 18933 22154 25449 21291 20425 20602 22604 24348 19368 17980 16793 17052 17524 13928 13535 13314 14817 15991 13289 13017 13217 13995 14362 10738 9376 8076 7926 7703 5944 5701 5314 5494 5744 4573 4527 4336 4606 4732 3699 3192 2768 2797 2796 2096 1976 1861 1885 1884 1493 1453 1428 1523 1471 1139 1008 939 873 894 646 629 590 605 581 499 466 402 392 440 358 328 271 244 264 214 194 164 180 203 128 112 106 122 117 81 75 73 72 57 46 42 52 40 37 23 22 21 29 19 27 11 15 13 19 13 10 7 8 5 6 3 5 7 3 6 4 3 1 0 3 1 2 1 3 2 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 19260 count: 616178 average: 3982.78 | standard deviation: 3082.99 | 1923 6985 12940 16852 16221 19485 21968 22951 19997 17263 18715 17525 14827 13389 11916 11467 9741 9146 8989 7432 7315 6919 7000 6576 5812 6092 6224 5757 5791 5458 5654 5406 5563 5824 5241 5556 5626 5960 5764 5346 5797 6190 5864 5845 5833 6364 5999 6055 6418 5956 6228 6258 6699 6227 5888 6447 6542 6194 5887 5714 5840 5660 5392 5444 4800 4719 4729 4711 4183 3673 3732 3729 3275 3025 2719 2757 2359 2299 2195 1846 1727 1590 1597 1397 1161 1163 1044 963 855 750 706 567 535 493 433 386 341 284 244 200 229 184 159 127 122 109 89 83 92 58 46 46 46 37 29 28 14 29 18 8 12 12 11 6 4 6 3 4 8 1 1 0 0 0 1 1 0 1 3 2 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 19260 count: 400216 average: 3981.88 | standard deviation: 3082.28 | 1243 4477 8345 10896 10482 12822 14257 14991 13035 11171 12161 11312 9600 8686 7757 7430 6366 5969 5893 4842 4737 4498 4545 4304 3761 3939 4124 3752 3763 3597 3656 3521 3666 3822 3405 3568 3665 3830 3670 3513 3661 4055 3779 3750 3811 4107 3922 3889 4147 3877 4071 4022 4373 4030 3884 4203 4265 3973 3782 3724 3840 3696 3553 3494 3146 3017 3099 3015 2765 2385 2427 2442 2122 1932 1749 1789 1529 1490 1440 1187 1097 1038 1021 913 749 724 658 630 567 506 453 350 341 332 291 261 218 200 161 136 148 125 105 83 89 58 47 45 58 41 29 30 32 26 20 23 8 17 11 5 9 4 10 4 4 4 2 3 7 0 0 0 0 0 1 1 0 0 3 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 18260 count: 215962 average: 3984.45 | standard deviation: 3084.31 | 680 2508 4595 5956 5739 6663 7711 7960 6962 6092 6554 6213 5227 4703 4159 4037 3375 3177 3096 2590 2578 2421 2455 2272 2051 2153 2100 2005 2028 1861 1998 1885 1897 2002 1836 1988 1961 2130 2094 1833 2136 2135 2085 2095 2022 2257 2077 2166 2271 2079 2157 2236 2326 2197 2004 2244 2277 2221 2105 1990 2000 1964 1839 1950 1654 1702 1630 1696 1418 1288 1305 1287 1153 1093 970 968 830 809 755 659 630 552 576 484 412 439 386 333 288 244 253 217 194 161 142 125 123 84 83 64 81 59 54 44 33 51 42 38 34 17 17 16 14 11 9 5 6 12 7 3 3 8 1 2 0 2 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 123 average: 2 | standard deviation: 0 | 0 0 123 ] +miss_latency_L2Cache: [binsize: 32 max: 4602 count: 587 average: 524.404 | standard deviation: 575.604 | 117 31 17 15 14 16 18 14 12 6 14 15 13 13 16 19 19 9 7 10 14 11 8 11 6 5 11 7 6 9 7 9 7 8 5 1 6 4 2 6 4 1 4 1 3 1 2 3 1 0 2 1 1 4 1 2 2 0 1 3 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 2 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 128 max: 19260 count: 595460 average: 4004.24 | standard deviation: 3081.89 | 0 6188 12231 15961 15370 18780 21406 22348 19464 16843 18315 17167 14540 13140 11663 11195 9529 8941 8787 7206 7141 6741 6782 6375 5648 5897 6020 5592 5593 5286 5471 5226 5388 5643 5029 5377 5455 5741 5566 5141 5594 5959 5667 5695 5617 6159 5794 5853 6201 5728 6013 6050 6489 6025 5708 6264 6348 6005 5735 5541 5672 5497 5233 5308 4685 4600 4609 4592 4067 3569 3646 3647 3187 2942 2666 2707 2298 2240 2144 1802 1693 1562 1567 1371 1128 1143 1021 937 843 732 688 556 521 486 423 379 336 281 240 195 225 180 156 127 120 108 89 82 92 56 46 46 46 37 29 28 14 29 18 7 12 12 11 6 4 6 3 4 8 1 1 0 0 0 1 1 0 1 3 2 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 128 max: 15323 count: 20008 average: 3470.19 | standard deviation: 3051.05 | 1620 735 662 830 806 661 533 572 512 402 390 349 283 241 247 271 211 204 202 225 173 176 216 201 164 195 204 165 198 170 183 180 175 181 212 178 171 219 198 205 203 231 197 150 216 205 205 202 217 228 215 208 210 202 180 183 194 189 152 173 168 163 159 136 115 119 120 119 116 104 86 82 88 83 53 50 61 59 51 44 34 28 30 26 33 20 23 26 12 18 18 11 14 7 10 7 5 3 4 5 4 4 3 0 2 1 0 1 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 14531 count: 19973 average: 3286.02 | standard deviation: 3034.97 | 2366 851 763 1000 739 600 526 499 414 279 302 284 223 190 201 205 196 202 204 188 168 184 204 174 176 191 200 175 170 184 179 180 197 203 153 181 200 211 221 172 223 211 206 174 215 238 200 205 218 193 205 203 241 178 171 171 195 185 156 151 169 144 142 120 117 103 131 116 94 82 64 82 79 67 55 42 58 58 38 31 26 26 26 27 24 20 21 20 8 18 13 7 6 6 9 3 7 1 4 3 2 1 2 2 2 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3577 count: 19973 average: 156.924 | standard deviation: 329.403 | 14267 324 247 266 249 212 209 211 267 213 183 195 183 269 202 178 182 149 178 113 114 89 79 82 79 88 86 74 84 68 68 55 59 68 33 45 35 33 33 35 22 37 23 32 20 18 18 18 18 11 10 10 15 6 11 7 6 8 10 4 5 5 5 4 1 3 5 1 2 0 1 2 4 4 2 1 3 0 2 1 0 2 1 1 2 0 1 0 1 0 0 0 1 0 0 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 36 count: 19973 average: 24.6278 | standard deviation: 1.16146 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14532 174 4629 66 198 202 135 17 12 3 1 3 1 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 13 count: 19973 average: 1.76343 | standard deviation: 1.58863 | 4611 5093 5259 3035 593 545 679 44 47 30 30 5 1 1 ] +imcomplete_wCC_Times: 35 +miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18671 count: 595460 average: 3283.61 | standard deviation: 3047.8 | 72165 24468 23589 28218 21559 18206 15911 15616 11515 8792 8964 8619 7132 6518 6106 6539 5828 5706 6059 5367 5389 5550 5744 5387 4929 5462 5563 5288 5190 4936 5610 5463 5285 5809 5185 5540 5654 6042 5818 5319 5923 6246 6141 5833 5842 6348 6011 6246 6403 5853 6123 6090 6408 5927 5445 5501 5710 5194 5091 4769 4841 4310 4148 4233 3521 3452 3346 3188 2807 2518 2419 2428 1989 1819 1664 1663 1394 1388 1305 1040 966 869 864 761 579 595 534 442 377 349 314 253 244 205 172 157 171 149 124 82 90 83 63 63 40 46 42 34 24 18 20 22 11 12 11 4 10 4 12 4 3 1 2 2 1 3 1 0 1 0 0 2 1 0 2 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_initial_forward_request: [binsize: 32 max: 3303 count: 595460 average: 11.5399 | standard deviation: 54.8109 | 592211 155 150 128 123 141 148 120 118 67 88 105 59 56 83 79 110 112 109 98 98 110 60 65 61 45 46 39 36 40 34 44 47 40 33 32 31 20 18 26 25 20 8 13 15 15 15 15 14 13 6 16 11 7 4 1 6 4 2 2 8 1 3 4 6 5 7 5 2 0 1 3 2 3 0 1 1 0 0 1 3 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 38 count: 595460 average: 24.832 | standard deviation: 1.28038 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 382093 4983 183588 1587 7757 8248 5728 645 407 262 65 54 37 5 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4197 count: 595460 average: 684.261 | standard deviation: 462.33 | 0 0 0 14346 19482 17049 19024 22354 25699 21621 20682 20151 22254 24251 19256 18086 16597 16944 17480 13958 13719 13444 14504 15774 13254 12999 13088 13958 14531 10737 9327 7956 7818 7732 5995 5675 5481 5614 5737 4631 4569 4356 4641 4726 3602 3150 2765 2788 2741 2051 1964 1878 1781 1973 1553 1525 1390 1518 1506 1178 988 906 832 865 699 620 608 591 570 472 424 413 434 450 331 286 250 260 248 195 191 175 163 156 115 125 105 117 114 116 70 61 61 59 45 55 44 50 35 31 37 26 24 29 20 21 23 12 13 8 9 6 7 5 3 3 3 1 2 2 1 4 3 0 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 90 average: 2 | standard deviation: 0 | 0 0 90 ] -miss_latency_LD_L2Cache: [binsize: 32 max: 5122 count: 259 average: 763.996 | standard deviation: 937.868 | 89 10 3 2 2 1 3 1 2 1 2 1 2 5 3 10 6 2 4 4 3 1 4 4 2 1 1 7 2 2 4 3 2 2 1 1 0 4 1 1 1 2 3 0 1 1 2 1 1 2 1 3 2 0 0 1 3 1 1 1 1 1 2 1 1 3 2 2 0 0 0 1 0 1 2 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 2 2 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_Directory: [binsize: 128 max: 18430 count: 387501 average: 4009.4 | standard deviation: 3090.24 | 0 4189 7892 10592 10045 12137 13688 14564 12617 11204 11808 11321 9385 8325 7589 7314 6275 5785 5680 4672 4666 4484 4561 3994 3628 3943 3985 3715 3528 3476 3671 3476 3535 3615 3190 3388 3348 3602 3402 3214 3562 3739 3700 3632 3610 3850 3781 3845 4058 3747 4002 4107 4224 4056 3663 4054 4081 4030 3766 3709 3755 3567 3399 3488 3088 3052 2993 2940 2611 2345 2415 2262 2146 1897 1846 1845 1648 1436 1345 1150 1164 1043 960 852 714 716 706 570 511 434 446 369 363 302 260 244 227 223 187 158 140 111 108 96 92 71 59 64 58 28 45 32 34 32 17 20 16 12 6 14 8 8 4 6 4 1 2 5 0 3 0 1 0 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 14805 count: 13032 average: 3474.07 | standard deviation: 3070.18 | 1095 502 440 527 535 412 360 372 314 244 255 216 186 157 173 159 162 128 155 122 111 128 122 127 121 126 124 111 107 113 105 118 126 113 123 115 109 118 131 137 125 123 140 106 133 156 130 141 140 130 124 137 141 122 123 113 111 114 123 128 129 112 87 98 105 84 79 80 79 67 63 64 49 38 48 36 45 32 30 36 21 19 16 13 19 23 12 11 4 8 9 5 5 4 5 3 7 4 3 2 3 4 3 1 4 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 47 average: 2 | standard deviation: 0 | 0 0 47 ] -miss_latency_ST_L2Cache: [binsize: 32 max: 3512 count: 122 average: 620.746 | standard deviation: 760.929 | 49 2 1 2 0 0 1 2 2 0 1 0 2 1 1 2 5 1 3 1 3 2 3 0 1 1 1 2 1 1 1 1 2 0 0 0 0 0 1 0 1 2 0 2 3 1 1 1 2 0 0 3 1 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_Directory: [binsize: 128 max: 18560 count: 208942 average: 3994.85 | standard deviation: 3090.24 | 0 2254 4301 5798 5466 6486 7651 7867 6978 6022 6552 5986 4993 4678 4058 3940 3465 3104 3042 2494 2467 2341 2405 2205 1979 2030 2119 1974 1875 1752 1975 1854 1856 1967 1745 1803 1831 1883 1775 1735 1958 2045 1930 1990 1981 2118 2078 1978 2246 2036 2090 2153 2283 2222 1950 2139 2208 2086 1984 1892 2058 2020 1820 1919 1658 1668 1551 1589 1444 1265 1332 1267 1121 1079 967 944 856 782 770 612 629 574 538 439 375 398 367 302 271 219 245 204 188 162 127 108 136 101 90 80 64 75 59 51 40 38 40 35 26 20 26 14 20 6 9 12 10 12 3 7 4 2 5 2 2 3 1 2 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 16283 count: 7102 average: 3399.28 | standard deviation: 3060.37 | 568 279 253 275 320 269 198 222 190 158 118 130 102 89 101 89 74 75 75 76 73 66 59 58 66 50 55 46 60 70 60 66 61 57 65 60 63 87 57 69 68 78 66 82 66 72 71 64 71 74 72 67 80 64 69 67 62 56 59 58 56 55 53 49 53 38 35 45 45 35 34 42 25 29 28 21 24 19 10 13 9 12 14 6 9 11 11 5 5 8 4 4 3 3 1 2 2 0 0 0 1 0 1 1 0 0 0 0 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 74 average: 2 | standard deviation: 0 | 0 0 74 ] +miss_latency_LD_L2Cache: [binsize: 32 max: 4602 count: 386 average: 529.723 | standard deviation: 594.125 | 77 21 13 9 10 11 8 10 7 5 10 8 11 9 9 13 14 4 3 7 10 8 6 6 3 3 11 3 2 8 3 6 5 4 3 1 4 1 2 4 3 1 2 0 3 1 1 3 1 0 0 1 0 2 0 1 2 0 1 3 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 128 max: 19260 count: 386757 average: 4003.38 | standard deviation: 3081.43 | 0 3978 7889 10309 9945 12364 13879 14603 12682 10905 11892 11078 9410 8521 7581 7247 6229 5838 5769 4689 4633 4381 4401 4173 3648 3811 3989 3639 3626 3482 3548 3399 3559 3703 3281 3456 3557 3676 3544 3384 3529 3903 3647 3649 3677 3970 3780 3758 4010 3721 3937 3888 4239 3904 3761 4085 4136 3861 3680 3616 3728 3587 3441 3401 3072 2952 3024 2940 2693 2324 2370 2380 2063 1874 1721 1755 1485 1446 1403 1161 1078 1018 1004 896 730 711 645 613 559 494 443 343 332 331 286 258 214 197 158 132 147 122 102 83 87 58 47 45 58 40 29 30 32 26 20 23 8 17 11 4 9 4 10 4 4 4 2 3 7 0 0 0 0 0 1 1 0 0 3 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15323 count: 12999 average: 3467.41 | standard deviation: 3042.84 | 1049 460 426 545 509 428 358 369 340 255 263 226 188 162 170 182 137 130 124 152 104 115 142 131 113 128 135 113 137 114 108 122 107 119 124 111 108 154 126 129 132 152 132 101 134 137 142 131 137 156 134 134 134 126 123 118 129 112 102 108 112 109 112 93 74 65 75 75 72 61 57 62 59 58 28 34 44 44 37 26 19 20 17 17 19 13 13 17 8 12 10 7 9 1 5 3 4 3 3 4 1 3 3 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 49 average: 2 | standard deviation: 0 | 0 0 49 ] +miss_latency_ST_L2Cache: [binsize: 32 max: 3792 count: 201 average: 514.189 | standard deviation: 539.55 | 40 10 4 6 4 5 10 4 5 1 4 7 2 4 7 6 5 5 4 3 4 3 2 5 3 2 0 4 4 1 4 3 2 4 2 0 2 3 0 2 1 0 2 1 0 0 1 0 0 0 2 0 1 2 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ] +miss_latency_ST_Directory: [binsize: 128 max: 18260 count: 208703 average: 4005.83 | standard deviation: 3082.75 | 0 2210 4342 5652 5425 6416 7527 7745 6782 5938 6423 6089 5130 4619 4082 3948 3300 3103 3018 2517 2508 2360 2381 2202 2000 2086 2031 1953 1967 1804 1923 1827 1829 1940 1748 1921 1898 2065 2022 1757 2065 2056 2020 2046 1940 2189 2014 2095 2191 2007 2076 2162 2250 2121 1947 2179 2212 2144 2055 1925 1944 1910 1792 1907 1613 1648 1585 1652 1374 1245 1276 1267 1124 1068 945 952 813 794 741 641 615 544 563 475 398 432 376 324 284 238 245 213 189 155 137 121 122 84 82 63 78 58 54 44 33 50 42 37 34 16 17 16 14 11 9 5 6 12 7 3 3 8 1 2 0 2 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 13978 count: 7009 average: 3475.33 | standard deviation: 3066.41 | 571 275 236 285 297 233 175 203 172 147 127 123 95 79 77 89 74 74 78 73 69 61 74 70 51 67 69 52 61 56 75 58 68 62 88 67 63 65 72 76 71 79 65 49 82 68 63 71 80 72 81 74 76 76 57 65 65 77 50 65 56 54 47 43 41 54 45 44 44 43 29 20 29 25 25 16 17 15 14 18 15 8 13 9 14 7 10 9 4 6 8 4 5 6 5 4 1 0 1 1 3 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -124,9 +124,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 150 +user_time: 142 system_time: 0 -page_reclaims: 10945 +page_reclaims: 11222 page_faults: 0 swaps: 0 block_inputs: 0 @@ -135,231 +135,231 @@ block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 1849923 14799384 -total_msg_count_Response_Data: 1849725 133180200 -total_msg_count_Response_Control: 12887505 103100040 -total_msg_count_Writeback_Data: 640509 46116648 -total_msg_count_Writeback_Control: 4596030 36768240 -total_msg_count_Broadcast_Control: 9248415 73987320 -total_msg_count_Unblock_Control: 1849767 14798136 -total_msgs: 32921874 total_bytes: 422749968 +total_msg_count_Request_Control: 1846575 14772600 +total_msg_count_Response_Data: 1846395 132940440 +total_msg_count_Response_Control: 12864582 102916656 +total_msg_count_Writeback_Data: 639753 46062216 +total_msg_count_Writeback_Control: 4586013 36688104 +total_msg_count_Broadcast_Control: 9231810 73854480 +total_msg_count_Unblock_Control: 1846434 14771472 +total_msgs: 32861562 total_bytes: 422005968 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 3.80194 - links_utilized_percent_switch_0_link_0: 4.80702 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 2.79687 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 6 48 [ 0 0 0 6 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 77300 5565600 [ 0 0 0 0 77300 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 538532 4308256 [ 0 0 0 0 538532 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 73030 584240 [ 0 0 0 73030 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Broadcast_Control: 539263 4314104 [ 0 0 0 539263 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 77305 618440 [ 0 0 77305 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 2438 175536 [ 0 0 0 0 2438 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 536831 4294648 [ 0 0 0 0 536831 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 26866 1934352 [ 0 0 0 0 0 26866 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 119193 953544 [ 0 0 73030 0 0 46163 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 77302 618416 [ 0 0 0 0 0 77302 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 3.80255 + links_utilized_percent_switch_0_link_0: 4.80554 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.79956 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 77158 5555376 [ 0 0 0 0 77158 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 537519 4300152 [ 0 0 0 0 537519 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 72761 582088 [ 0 0 0 72761 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 538300 4306400 [ 0 0 0 538300 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 77159 617272 [ 0 0 77159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 2500 180000 [ 0 0 0 0 2500 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 535802 4286416 [ 0 0 0 0 535802 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 26942 1939824 [ 0 0 0 0 0 26942 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 118579 948632 [ 0 0 72761 0 0 45818 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 77158 617264 [ 0 0 0 0 0 77158 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 3.80592 - links_utilized_percent_switch_1_link_0: 4.80942 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 2.80243 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 538953 4311624 [ 0 0 0 0 538953 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 73054 584432 [ 0 0 0 73054 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Broadcast_Control: 539203 4313624 [ 0 0 0 539203 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 77364 618912 [ 0 0 77364 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 3.7936 + links_utilized_percent_switch_1_link_0: 4.79165 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 2.79555 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 76825 5531400 [ 0 0 0 0 76825 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 535222 4281776 [ 0 0 0 0 535222 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 72394 579152 [ 0 0 0 72394 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 538630 4309040 [ 0 0 0 538630 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 76828 614624 [ 0 0 76828 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Data: 2539 182808 [ 0 0 0 0 2539 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 536667 4293336 [ 0 0 0 0 536667 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 27019 1945368 [ 0 0 0 0 0 27019 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 119088 952704 [ 0 0 73054 0 0 46034 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 77361 618888 [ 0 0 0 0 0 77361 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 536093 4288744 [ 0 0 0 0 536093 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 26844 1932768 [ 0 0 0 0 0 26844 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 117943 943544 [ 0 0 72394 0 0 45549 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 76826 614608 [ 0 0 0 0 0 76826 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 3.80003 - links_utilized_percent_switch_2_link_0: 4.8041 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.79595 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 77233 5560776 [ 0 0 0 0 77233 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 538121 4304968 [ 0 0 0 0 538121 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 72863 582904 [ 0 0 0 72863 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Broadcast_Control: 539328 4314624 [ 0 0 0 539328 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 77236 617888 [ 0 0 77236 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 2541 182952 [ 0 0 0 0 2541 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 536792 4294336 [ 0 0 0 0 536792 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 26770 1927440 [ 0 0 0 0 0 26770 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 118955 951640 [ 0 0 72863 0 0 46092 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 77233 617864 [ 0 0 0 0 0 77233 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 3.78298 + links_utilized_percent_switch_2_link_0: 4.78107 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.7849 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 76562 5512464 [ 0 0 0 0 76562 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 533430 4267440 [ 0 0 0 0 533430 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 72230 577840 [ 0 0 0 72230 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 538895 4311160 [ 0 0 0 538895 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 76566 612528 [ 0 0 76566 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2532 182304 [ 0 0 0 0 2532 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 536364 4290912 [ 0 0 0 0 536364 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 26414 1901808 [ 0 0 0 0 0 26414 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 118043 944344 [ 0 0 72230 0 0 45813 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 76566 612528 [ 0 0 0 0 0 76566 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 3.79339 - links_utilized_percent_switch_3_link_0: 4.79528 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 2.7915 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 77020 5545440 [ 0 0 0 0 77020 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 536659 4293272 [ 0 0 0 0 536659 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 72633 581064 [ 0 0 0 72633 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Broadcast_Control: 539543 4316344 [ 0 0 0 539543 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 77022 616176 [ 0 0 77022 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 2550 183600 [ 0 0 0 0 2550 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 537000 4296000 [ 0 0 0 0 537000 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 26631 1917432 [ 0 0 0 0 0 26631 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 118632 949056 [ 0 0 72633 0 0 45999 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 77023 616184 [ 0 0 0 0 0 77023 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 3.7968 + links_utilized_percent_switch_3_link_0: 4.80233 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 2.79128 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 77067 5548824 [ 0 0 0 0 77067 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 536996 4295968 [ 0 0 0 0 536996 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 72780 582240 [ 0 0 0 72780 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 538388 4307104 [ 0 0 0 538388 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 77070 616560 [ 0 0 77070 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 2435 175320 [ 0 0 0 0 2435 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 535956 4287648 [ 0 0 0 0 535956 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 26617 1916424 [ 0 0 0 0 0 26617 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 118939 951512 [ 0 0 72780 0 0 46159 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 77069 616552 [ 0 0 0 0 0 77069 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 3.78578 - links_utilized_percent_switch_4_link_0: 4.78625 bw: 16000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 2.78531 bw: 16000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 76794 5529168 [ 0 0 0 0 76794 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 535094 4280752 [ 0 0 0 0 535094 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 72536 580288 [ 0 0 0 72536 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Broadcast_Control: 539767 4318136 [ 0 0 0 539767 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 76796 614368 [ 0 0 76796 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 2575 185400 [ 0 0 0 0 2575 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 537202 4297616 [ 0 0 0 0 537202 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Data: 26361 1897992 [ 0 0 0 0 0 26361 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Control: 118709 949672 [ 0 0 72536 0 0 46173 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 76796 614368 [ 0 0 0 0 0 76796 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 3.79588 + links_utilized_percent_switch_4_link_0: 4.79971 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 2.79204 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 77000 5544000 [ 0 0 0 0 77000 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 536573 4292584 [ 0 0 0 0 536573 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 72734 581872 [ 0 0 0 72734 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 538458 4307664 [ 0 0 0 538458 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 77003 616024 [ 0 0 77003 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 2470 177840 [ 0 0 0 0 2470 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 535989 4287912 [ 0 0 0 0 535989 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 26638 1917936 [ 0 0 0 0 0 26638 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 118830 950640 [ 0 0 72734 0 0 46096 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 77000 616000 [ 0 0 0 0 0 77000 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 3.79864 - links_utilized_percent_switch_5_link_0: 4.80515 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 2.79214 bw: 16000 base_latency: 1 +links_utilized_percent_switch_5: 3.79933 + links_utilized_percent_switch_5_link_0: 4.80022 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 2.79844 bw: 16000 base_latency: 1 outgoing_messages_switch_5_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 77256 5562432 [ 0 0 0 0 77256 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 538226 4305808 [ 0 0 0 0 538226 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 72967 583736 [ 0 0 0 72967 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Broadcast_Control: 539312 4314496 [ 0 0 0 539312 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 77259 618072 [ 0 0 77259 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 2389 172008 [ 0 0 0 0 2389 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 536926 4295408 [ 0 0 0 0 536926 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Data: 26709 1923048 [ 0 0 0 0 0 26709 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Control: 119224 953792 [ 0 0 72967 0 0 46257 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 77258 618064 [ 0 0 0 0 0 77258 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 77026 5545872 [ 0 0 0 0 77026 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 536618 4292944 [ 0 0 0 0 536618 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 72681 581448 [ 0 0 0 72681 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 538427 4307416 [ 0 0 0 538427 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 77030 616240 [ 0 0 77030 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 2480 178560 [ 0 0 0 0 2480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 535948 4287584 [ 0 0 0 0 535948 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 26945 1940040 [ 0 0 0 0 0 26945 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 118416 947328 [ 0 0 72681 0 0 45735 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 77028 616224 [ 0 0 0 0 0 77028 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 3.79434 - links_utilized_percent_switch_6_link_0: 4.79649 bw: 16000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 2.79218 bw: 16000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 77057 5548104 [ 0 0 0 0 77057 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 536838 4294704 [ 0 0 0 0 536838 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 72627 581016 [ 0 0 0 72627 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Broadcast_Control: 539505 4316040 [ 0 0 0 539505 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 77060 616480 [ 0 0 77060 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 2522 181584 [ 0 0 0 0 2522 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 536986 4295888 [ 0 0 0 0 536986 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Data: 26689 1921608 [ 0 0 0 0 0 26689 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Control: 118562 948496 [ 0 0 72627 0 0 45935 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 77060 616480 [ 0 0 0 0 0 77060 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 3.78971 + links_utilized_percent_switch_6_link_0: 4.7944 bw: 16000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 2.78502 bw: 16000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 76878 5535216 [ 0 0 0 0 76878 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 535716 4285728 [ 0 0 0 0 535716 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 72531 580248 [ 0 0 0 72531 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 538575 4308600 [ 0 0 0 538575 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 76883 615064 [ 0 0 76883 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 2515 181080 [ 0 0 0 0 2515 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 536065 4288520 [ 0 0 0 0 536065 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 26322 1895184 [ 0 0 0 0 0 26322 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 118739 949912 [ 0 0 72531 0 0 46208 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 76880 615040 [ 0 0 0 0 0 76880 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 3.78024 - links_utilized_percent_switch_7_link_0: 4.77582 bw: 16000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 2.78465 bw: 16000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 76555 5511960 [ 0 0 0 0 76555 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 533412 4267296 [ 0 0 0 0 533412 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 72132 577056 [ 0 0 0 72132 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Broadcast_Control: 540006 4320048 [ 0 0 0 540006 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 76559 612472 [ 0 0 76559 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 2578 185616 [ 0 0 0 0 2578 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 537431 4299448 [ 0 0 0 0 537431 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Data: 26458 1904976 [ 0 0 0 0 0 26458 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Control: 117805 942440 [ 0 0 72132 0 0 45673 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 76556 612448 [ 0 0 0 0 0 76556 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 3.79344 + links_utilized_percent_switch_7_link_0: 4.79695 bw: 16000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 2.78993 bw: 16000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 76949 5540328 [ 0 0 0 0 76949 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 536120 4288960 [ 0 0 0 0 536120 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 72534 580272 [ 0 0 0 72534 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 538505 4308040 [ 0 0 0 538505 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 76951 615608 [ 0 0 76951 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 2534 182448 [ 0 0 0 0 2534 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 535977 4287816 [ 0 0 0 0 535977 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 26529 1910088 [ 0 0 0 0 0 26529 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 118537 948296 [ 0 0 72534 0 0 46003 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 76951 615608 [ 0 0 0 0 0 76951 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 13.8902 - links_utilized_percent_switch_8_link_0: 10.6861 bw: 16000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 17.0942 bw: 16000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Request_Control: 616601 4932808 [ 0 0 616601 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Data: 213503 15372216 [ 0 0 0 0 0 213503 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Control: 950168 7601344 [ 0 0 581842 0 0 368326 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 616589 4932712 [ 0 0 0 0 0 616589 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 596443 42943896 [ 0 0 0 0 596443 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 581842 4654736 [ 0 0 0 581842 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Broadcast_Control: 616561 4932488 [ 0 0 0 616561 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 13.8893 + links_utilized_percent_switch_8_link_0: 10.686 bw: 16000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 17.0926 bw: 16000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 615490 4923920 [ 0 0 615490 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 213251 15354072 [ 0 0 0 0 0 213251 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 948026 7584208 [ 0 0 580645 0 0 367381 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 615478 4923824 [ 0 0 0 0 0 615478 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 35 280 [ 0 0 0 35 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 595460 42873120 [ 0 0 0 0 595460 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 580645 4645160 [ 0 0 0 580645 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Broadcast_Control: 615454 4923632 [ 0 0 0 615454 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 5.45174 - links_utilized_percent_switch_9_link_0: 4.80702 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 4.80942 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 4.80411 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 4.79528 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 4.78625 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 4.80515 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 4.79649 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 4.77582 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 10.6861 bw: 16000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Request_Control: 6 48 [ 0 0 0 6 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Data: 77300 5565600 [ 0 0 0 0 77300 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 538532 4308256 [ 0 0 0 0 538532 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 73030 584240 [ 0 0 0 73030 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Broadcast_Control: 539263 4314104 [ 0 0 0 539263 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 538953 4311624 [ 0 0 0 0 538953 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 73054 584432 [ 0 0 0 73054 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Broadcast_Control: 539203 4313624 [ 0 0 0 539203 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 77233 5560776 [ 0 0 0 0 77233 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Control: 538121 4304968 [ 0 0 0 0 538121 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Writeback_Control: 72863 582904 [ 0 0 0 72863 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Broadcast_Control: 539328 4314624 [ 0 0 0 539328 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 77020 5545440 [ 0 0 0 0 77020 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Control: 536659 4293272 [ 0 0 0 0 536659 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Writeback_Control: 72633 581064 [ 0 0 0 72633 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Broadcast_Control: 539543 4316344 [ 0 0 0 539543 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 76794 5529168 [ 0 0 0 0 76794 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Control: 535094 4280752 [ 0 0 0 0 535094 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Writeback_Control: 72536 580288 [ 0 0 0 72536 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Broadcast_Control: 539767 4318136 [ 0 0 0 539767 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 5.45088 + links_utilized_percent_switch_9_link_0: 4.80555 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 4.79165 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 4.78107 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 4.80233 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 4.79971 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 4.80022 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 4.7944 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 4.79695 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 10.686 bw: 16000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 77158 5555376 [ 0 0 0 0 77158 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 537519 4300152 [ 0 0 0 0 537519 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 72761 582088 [ 0 0 0 72761 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Broadcast_Control: 538300 4306400 [ 0 0 0 538300 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 76825 5531400 [ 0 0 0 0 76825 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 535222 4281776 [ 0 0 0 0 535222 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 72394 579152 [ 0 0 0 72394 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Broadcast_Control: 538630 4309040 [ 0 0 0 538630 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 76562 5512464 [ 0 0 0 0 76562 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Control: 533430 4267440 [ 0 0 0 0 533430 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 72230 577840 [ 0 0 0 72230 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Broadcast_Control: 538895 4311160 [ 0 0 0 538895 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 77067 5548824 [ 0 0 0 0 77067 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Control: 536996 4295968 [ 0 0 0 0 536996 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 72780 582240 [ 0 0 0 72780 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Broadcast_Control: 538388 4307104 [ 0 0 0 538388 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 77000 5544000 [ 0 0 0 0 77000 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Control: 536573 4292584 [ 0 0 0 0 536573 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 72734 581872 [ 0 0 0 72734 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Broadcast_Control: 538458 4307664 [ 0 0 0 538458 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_5_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 77256 5562432 [ 0 0 0 0 77256 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Control: 538226 4305808 [ 0 0 0 0 538226 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Writeback_Control: 72967 583736 [ 0 0 0 72967 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Broadcast_Control: 539312 4314496 [ 0 0 0 539312 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 77057 5548104 [ 0 0 0 0 77057 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Control: 536838 4294704 [ 0 0 0 0 536838 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Writeback_Control: 72627 581016 [ 0 0 0 72627 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Broadcast_Control: 539505 4316040 [ 0 0 0 539505 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 76555 5511960 [ 0 0 0 0 76555 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Control: 533412 4267296 [ 0 0 0 0 533412 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Writeback_Control: 72132 577056 [ 0 0 0 72132 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Broadcast_Control: 540006 4320048 [ 0 0 0 540006 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Request_Control: 616601 4932808 [ 0 0 616601 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Writeback_Data: 213503 15372216 [ 0 0 0 0 0 213503 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Writeback_Control: 950168 7601344 [ 0 0 581842 0 0 368326 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Unblock_Control: 616589 4932712 [ 0 0 0 0 0 616589 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 77026 5545872 [ 0 0 0 0 77026 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Control: 536618 4292944 [ 0 0 0 0 536618 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 72681 581448 [ 0 0 0 72681 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Broadcast_Control: 538427 4307416 [ 0 0 0 538427 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 76878 5535216 [ 0 0 0 0 76878 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Control: 535716 4285728 [ 0 0 0 0 535716 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 72531 580248 [ 0 0 0 72531 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Broadcast_Control: 538575 4308600 [ 0 0 0 538575 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 76949 5540328 [ 0 0 0 0 76949 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Control: 536120 4288960 [ 0 0 0 0 536120 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 72534 580272 [ 0 0 0 72534 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Broadcast_Control: 538505 4308040 [ 0 0 0 538505 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Request_Control: 615490 4923920 [ 0 0 615490 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Data: 213251 15354072 [ 0 0 0 0 0 213251 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Control: 948026 7584208 [ 0 0 580645 0 0 367381 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Unblock_Control: 615478 4923824 [ 0 0 0 0 0 615478 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -370,158 +370,187 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 77411 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77411 + system.l1_cntrl0.L1DcacheMemory_total_misses: 77237 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77237 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.921% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.079% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.6853% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.3147% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 77411 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 77237 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 77411 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 77411 + system.l1_cntrl0.L2cacheMemory_total_misses: 77237 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 77237 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 64.921% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 35.079% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 64.6853% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 35.3147% - system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 77411 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 77237 100% --- L1Cache --- - Event Counts - -Load [50163 50373 50109 49830 50293 50155 50215 50165 ] 401303 +Load [50136 49921 50357 50224 50012 49787 49899 50223 ] 400559 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26758 27016 27072 26870 27172 27373 27169 26987 ] 216417 -L2_Replacement [76787 77246 77049 76546 77291 77352 77223 77010 ] 616504 -L1_to_L2 [859071 863449 863191 862532 865779 865320 858921 859823 ] 6898086 -Trigger_L2_to_L1D [83 75 72 97 106 109 96 85 ] 723 +Store [27021 27243 26701 26881 27313 27202 26808 26983 ] 216152 +L2_Replacement [76992 77018 76870 76939 77149 76815 76551 77059 ] 615393 +L1_to_L2 [864411 861133 858042 856241 861917 856546 858388 857418 ] 6874096 +Trigger_L2_to_L1D [69 68 88 81 78 83 72 66 ] 605 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -Complete_L2_to_L1 [83 75 72 97 106 109 96 85 ] 723 -Other_GETX [189334 189081 189025 189235 188935 188724 188932 189112 ] 1512378 -Other_GETS [350433 350231 350480 350771 350328 350479 350396 350431 ] 2803549 -Merged_GETS [10 3 3 3 6 3 5 7 ] 40 +Complete_L2_to_L1 [69 68 88 81 78 83 72 66 ] 605 +Other_GETX [188764 188525 189074 188898 188476 188570 188959 188774 ] 1510040 +Other_GETS [349694 349902 349501 349607 349824 350060 349936 349614 ] 2798138 +Merged_GETS [3 3 7 8 4 4 3 3 ] 35 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 Invalidate [0 0 0 0 0 0 0 0 ] 0 -Ack [535038 538171 536787 533353 538476 538901 538068 536606 ] 4295400 -Shared_Ack [56 55 51 59 56 52 53 53 ] 435 -Data [2755 2815 2859 2820 2860 2835 2861 2845 ] 22650 -Shared_Data [1009 1056 1071 1024 1054 1042 1027 995 ] 8278 -Exclusive_Data [73030 73385 73127 72711 73386 73483 73345 73180 ] 585647 -Writeback_Ack [72536 72967 72627 72132 73030 73054 72863 72633 ] 581842 +Ack [536505 536561 535658 536064 537454 535179 533370 536950 ] 4287741 +Shared_Ack [68 57 58 56 65 43 60 46 ] 453 +Data [2826 2857 2890 2843 2907 2930 2862 2864 ] 22979 +Shared_Data [1016 1083 990 1096 1067 1056 1035 1025 ] 8368 +Exclusive_Data [73158 73086 72998 73010 73184 72839 72665 73178 ] 584118 +Writeback_Ack [72734 72681 72531 72534 72761 72394 72230 72780 ] 580645 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -All_acks [1053 1100 1117 1071 1100 1092 1072 1043 ] 8648 -All_acks_no_sharers [75741 76157 75940 75484 76201 76268 76161 75977 ] 607929 +All_acks [1073 1133 1040 1146 1126 1092 1084 1065 ] 8759 +All_acks_no_sharers [75927 75894 75839 75803 76031 75733 75479 76002 ] 606708 Flush_line [0 0 0 0 0 0 0 0 ] 0 Block_Ack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -I Load [50076 50286 50031 49740 50186 50034 50114 50080 ] 400547 +I Load [50047 49835 50236 50128 49915 49677 49804 50123 ] 399765 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [26720 26972 27029 26818 27116 27330 27120 26941 ] 216046 -I L2_Replacement [1534 1454 1528 1570 1434 1483 1499 1597 ] 12099 -I L1_to_L2 [333 307 342 357 292 348 331 347 ] 2657 -I Trigger_L2_to_L1D [1 2 1 2 2 2 2 0 ] 12 +I Store [26955 27193 26644 26819 27244 27148 26758 26946 ] 215707 +I L2_Replacement [1447 1462 1521 1513 1490 1522 1468 1451 ] 11874 +I L1_to_L2 [325 321 333 286 324 339 341 298 ] 2567 +I Trigger_L2_to_L1D [0 1 2 2 0 2 2 1 ] 10 I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -I Other_GETX [188391 188183 188103 188283 188063 187808 188059 188100 ] 1504990 -I Other_GETS [348721 348642 348788 349056 348663 348773 348635 348794 ] 2790072 +I Other_GETX [187875 187612 188145 187963 187564 187635 188071 187887 ] 1502752 +I Other_GETS [348011 348249 347829 347932 348133 348354 348179 347977 ] 2784664 I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 I NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 I Invalidate [0 0 0 0 0 0 0 0 ] 0 I Flush_line [0 0 0 0 0 0 0 0 ] 0 -S Load [0 2 0 1 2 1 2 1 ] 9 +S Load [2 0 1 0 1 1 0 0 ] 5 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 0 1 2 0 2 1 ] 6 -S L2_Replacement [2717 2825 2894 2844 2827 2815 2861 2780 ] 22563 -S L1_to_L2 [2744 2855 2912 2869 2862 2842 2886 2816 ] 22786 -S Trigger_L2_to_L1D [0 2 4 2 6 3 6 6 ] 29 +S Store [0 0 0 0 0 0 0 0 ] 0 +S L2_Replacement [2811 2875 2818 2892 2898 2899 2853 2828 ] 22874 +S L1_to_L2 [2840 2904 2849 2910 2927 2932 2884 2855 ] 23101 +S Trigger_L2_to_L1D [4 2 5 3 3 4 2 3 ] 26 S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -S Other_GETX [30 41 23 33 39 29 34 40 ] 269 -S Other_GETS [52 48 62 55 53 46 60 59 ] 435 +S Other_GETX [33 37 32 24 31 36 37 31 ] 261 +S Other_GETS [58 42 51 51 67 63 67 54 ] 453 S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 S NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 S Invalidate [0 0 0 0 0 0 0 0 ] 0 S Flush_line [0 0 0 0 0 0 0 0 ] 0 -O Load [0 1 0 0 0 1 1 1 ] 4 +O Load [1 0 0 0 0 0 0 0 ] 1 O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [0 1 0 0 1 0 0 0 ] 2 -O L2_Replacement [1046 943 991 1014 1011 1060 1048 950 ] 8063 -O L1_to_L2 [241 194 208 210 234 226 212 218 ] 1743 -O Trigger_L2_to_L1D [0 4 2 0 1 3 2 2 ] 14 +O Store [0 0 0 0 0 0 0 0 ] 0 +O L2_Replacement [1034 1025 1000 1026 1017 1022 1069 1000 ] 8193 +O L1_to_L2 [233 219 218 238 204 238 227 241 ] 1818 +O Trigger_L2_to_L1D [1 1 1 0 1 0 2 0 ] 6 O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -O Other_GETX [6 8 10 12 8 9 8 9 ] 70 -O Other_GETS [8 15 8 8 15 10 13 20 ] 97 -O Merged_GETS [4 0 0 3 2 1 3 4 ] 17 +O Other_GETX [7 6 6 6 5 14 7 4 ] 55 +O Other_GETS [11 16 15 6 12 8 15 6 ] 89 +O Merged_GETS [0 2 0 2 3 2 2 1 ] 12 O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 O NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 O Invalidate [0 0 0 0 0 0 0 0 ] 0 O Flush_line [0 0 0 0 0 0 0 0 ] 0 -M Load [29 24 21 26 29 38 37 21 ] 225 +M Load [6 4 6 4 7 7 6 3 ] 43 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [18 11 9 18 20 11 16 16 ] 119 -M L2_Replacement [45693 45922 45536 45273 45742 45550 45631 45652 ] 364999 -M L1_to_L2 [47010 47145 46806 46575 47020 46896 46940 46936 ] 375328 -M Trigger_L2_to_L1D [60 45 42 62 65 71 61 47 ] 453 +M Store [5 3 3 6 5 6 3 4 ] 35 +M L2_Replacement [45602 45311 45801 45565 45377 45134 45302 45711 ] 363803 +M L1_to_L2 [46867 46598 47080 46895 46684 46406 46592 46951 ] 374073 +M Trigger_L2_to_L1D [44 35 54 51 42 49 41 37 ] 353 M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -M Other_GETX [563 531 562 537 531 556 506 627 ] 4413 -M Other_GETS [1046 949 998 1026 1016 1067 1054 957 ] 8113 -M Merged_GETS [4 2 2 0 2 1 1 0 ] 12 +M Other_GETX [525 553 558 591 557 545 513 532 ] 4374 +M Other_GETS [1038 1031 1000 1026 1021 1034 1076 1002 ] 8228 +M Merged_GETS [0 1 3 3 1 2 1 0 ] 11 M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 M NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 M Invalidate [0 0 0 0 0 0 0 0 ] 0 M Flush_line [0 0 0 0 0 0 0 0 ] 0 -MM Load [12 14 10 13 16 16 10 20 ] 111 +MM Load [6 4 4 0 1 4 3 3 ] 25 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [3 8 10 6 7 6 5 5 ] 50 -MM L2_Replacement [25797 26102 26100 25845 26277 26444 26184 26031 ] 208780 -MM L1_to_L2 [26547 26825 26859 26638 26995 27155 26956 26784 ] 214759 -MM Trigger_L2_to_L1D [22 22 23 31 32 30 25 30 ] 215 +MM Store [1 2 3 3 3 1 1 0 ] 14 +MM L2_Replacement [26098 26345 25730 25943 26367 26238 25859 26069 ] 208649 +MM L1_to_L2 [26802 27050 26484 26695 27094 26988 26585 26786 ] 214484 +MM Trigger_L2_to_L1D [20 29 26 25 32 28 25 25 ] 210 MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -MM Other_GETX [341 312 322 369 291 317 322 330 ] 2604 -MM Other_GETS [594 565 612 621 566 574 630 592 ] 4754 -MM Merged_GETS [2 1 1 0 2 1 1 3 ] 11 +MM Other_GETX [319 314 330 311 316 338 323 315 ] 2566 +MM Other_GETS [563 553 597 583 582 592 591 570 ] 4631 +MM Merged_GETS [3 0 4 3 0 0 0 2 ] 12 MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MM Invalidate [0 0 0 0 0 0 0 0 ] 0 MM Flush_line [0 0 0 0 0 0 0 0 ] 0 +IR Load [0 0 1 1 0 0 1 1 ] 4 +IR Ifetch [0 0 0 0 0 0 0 0 ] 0 +IR Store [0 1 1 1 0 2 1 0 ] 6 +IR L1_to_L2 [0 0 10 8 0 11 5 0 ] 34 +IR Flush_line [0 0 0 0 0 0 0 0 ] 0 + +SR Load [3 2 5 1 3 3 1 3 ] 21 +SR Ifetch [0 0 0 0 0 0 0 0 ] 0 +SR Store [1 0 0 2 0 1 1 0 ] 5 +SR L1_to_L2 [0 7 10 3 7 9 12 3 ] 51 +SR Flush_line [0 0 0 0 0 0 0 0 ] 0 + +OR Load [1 0 0 0 1 0 1 0 ] 3 +OR Ifetch [0 0 0 0 0 0 0 0 ] 0 +OR Store [0 1 1 0 0 0 1 0 ] 3 +OR L1_to_L2 [9 1 0 0 0 0 0 0 ] 10 +OR Flush_line [0 0 0 0 0 0 0 0 ] 0 + +MR Load [20 17 39 36 23 34 27 30 ] 226 +MR Ifetch [0 0 0 0 0 0 0 0 ] 0 +MR Store [24 18 15 15 19 15 14 7 ] 127 +MR L1_to_L2 [149 91 150 151 166 136 118 77 ] 1038 + +MMR Load [14 22 14 15 19 17 18 17 ] 136 +MMR Ifetch [0 0 0 0 0 0 0 0 ] 0 +MMR Store [6 7 12 10 13 11 7 8 ] 74 +MMR L1_to_L2 [72 72 66 74 102 75 52 93 ] 606 +MMR Flush_line [0 0 0 0 0 0 0 0 ] 0 + IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM L1_to_L2 [269788 275496 274549 274038 277652 278285 272728 272413 ] 2194949 -IM Other_GETX [1 2 0 0 0 2 0 2 ] 7 -IM Other_GETS [4 4 2 1 2 3 1 2 ] 19 +IM L1_to_L2 [276842 276456 272937 272333 276389 275394 273741 269624 ] 2193716 +IM Other_GETX [2 1 1 0 2 1 2 1 ] 10 +IM Other_GETS [3 4 2 3 2 2 1 2 ] 19 IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IM Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM Ack [183535 185381 185654 184323 186113 187547 186235 185054 ] 1483842 -IM Data [1016 1005 1013 965 1044 1032 988 1018 ] 8081 -IM Exclusive_Data [25703 25965 26015 25852 26071 26295 26131 25923 ] 207955 +IM Ack [185315 186777 183129 184420 187041 186647 183757 185106 ] 1482192 +IM Data [996 1028 1030 1019 1045 1049 1004 1030 ] 8201 +IM Exclusive_Data [25958 26164 25614 25801 26198 26099 25753 25916 ] 207503 IM Flush_line [0 0 0 0 0 0 0 0 ] 0 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM L1_to_L2 [0 0 0 1 0 0 2 0 ] 3 +SM L1_to_L2 [1 0 0 3 0 2 11 0 ] 17 SM Other_GETX [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 SM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 SM Invalidate [0 0 0 0 0 0 0 0 ] 0 -SM Ack [0 0 0 7 7 0 14 7 ] 35 -SM Data [0 0 0 1 2 0 2 1 ] 6 +SM Ack [7 0 0 14 0 7 7 0 ] 35 +SM Data [1 0 0 2 0 1 1 0 ] 5 SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 SM Flush_line [0 0 0 0 0 0 0 0 ] 0 @@ -529,16 +558,16 @@ OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 OM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OM L1_to_L2 [0 0 0 0 12 0 0 0 ] 12 +OM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 OM Other_GETX [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS [0 0 0 0 0 0 0 0 ] 0 OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OM Invalidate [0 0 0 0 0 0 0 0 ] 0 -OM Ack [0 7 0 0 7 0 0 0 ] 14 +OM Ack [0 7 7 0 0 0 7 0 ] 21 OM All_acks [0 0 0 0 0 0 0 0 ] 0 -OM All_acks_no_sharers [0 1 0 0 1 0 0 0 ] 2 +OM All_acks_no_sharers [0 1 1 0 0 0 1 0 ] 3 OM Flush_line [0 0 0 0 0 0 0 0 ] 0 ISM Load [0 0 0 0 0 0 0 0 ] 0 @@ -546,57 +575,57 @@ ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 ISM Store [0 0 0 0 0 0 0 0 ] 0 ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 ISM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -ISM Ack [51 33 28 17 27 21 19 37 ] 233 -ISM All_acks_no_sharers [1016 1005 1013 966 1046 1032 990 1019 ] 8087 +ISM Ack [28 15 25 9 38 27 31 21 ] 194 +ISM All_acks_no_sharers [997 1028 1030 1021 1045 1050 1005 1030 ] 8206 ISM Flush_line [0 0 0 0 0 0 0 0 ] 0 M_W Load [0 0 0 0 0 0 0 0 ] 0 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 M_W Store [0 0 0 0 0 0 0 0 ] 0 M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_W L1_to_L2 [431 524 347 549 424 448 489 544 ] 3756 -M_W Ack [1661 1807 1862 1871 1702 1731 1860 1773 ] 14267 -M_W All_acks_no_sharers [47327 47420 47112 46859 47315 47188 47214 47257 ] 377692 +M_W L1_to_L2 [452 467 453 489 544 459 543 469 ] 3876 +M_W Ack [1629 1807 1767 1717 1719 1755 1715 1612 ] 13721 +M_W All_acks_no_sharers [47200 46922 47384 47209 46986 46740 46912 47262 ] 376615 M_W Flush_line [0 0 0 0 0 0 0 0 ] 0 MM_W Load [0 0 0 0 0 0 0 0 ] 0 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 MM_W Store [0 0 0 0 0 0 0 0 ] 0 MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_to_L2 [560 709 745 691 755 619 743 630 ] 5452 -MM_W Ack [2563 2529 2630 2549 2762 2805 2694 2622 ] 21154 -MM_W All_acks_no_sharers [25703 25965 26015 25852 26071 26295 26131 25923 ] 207955 +MM_W L1_to_L2 [801 846 874 523 893 734 591 741 ] 6003 +MM_W Ack [2493 2679 2501 2472 2713 2487 2629 2618 ] 20592 +MM_W All_acks_no_sharers [25958 26164 25614 25801 26197 26099 25753 25916 ] 207502 MM_W Flush_line [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS L1_to_L2 [510214 508312 509308 509355 508257 507247 506466 508129 ] 4067288 -IS Other_GETX [0 3 2 0 2 2 2 1 ] 12 -IS Other_GETS [3 3 6 3 9 4 1 2 ] 31 +IS L1_to_L2 [507841 505109 505606 504236 505442 501862 505670 508309 ] 4044075 +IS Other_GETX [3 1 1 1 0 0 3 2 ] 11 +IS Other_GETS [6 4 6 5 5 4 6 2 ] 38 IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IS NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IS Invalidate [0 0 0 0 0 0 0 0 ] 0 -IS Ack [344302 345200 343518 341449 344621 343564 344086 344152 ] 2750892 -IS Shared_Ack [50 51 49 52 51 51 50 53 ] 407 -IS Data [1739 1810 1846 1854 1814 1803 1871 1826 ] 14563 -IS Shared_Data [1009 1056 1071 1024 1054 1042 1027 995 ] 8278 -IS Exclusive_Data [47327 47420 47112 46859 47315 47188 47214 47257 ] 377692 +IS Ack [344063 342120 345379 344164 342669 340985 342128 344477 ] 2745985 +IS Shared_Ack [65 55 54 55 62 41 55 44 ] 431 +IS Data [1829 1829 1860 1822 1862 1880 1857 1834 ] 14773 +IS Shared_Data [1016 1083 990 1096 1067 1056 1035 1025 ] 8368 +IS Exclusive_Data [47200 46922 47384 47209 46986 46740 46912 47262 ] 376615 IS Flush_line [0 0 0 0 0 0 0 0 ] 0 SS Load [0 0 0 0 0 0 0 0 ] 0 SS Ifetch [0 0 0 0 0 0 0 0 ] 0 SS Store [0 0 0 0 0 0 0 0 ] 0 SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SS L1_to_L2 [934 749 816 921 965 860 866 746 ] 6857 -SS Ack [2926 3214 3095 3137 3237 3233 3160 2961 ] 24963 -SS Shared_Ack [6 4 2 7 5 1 3 0 ] 28 -SS All_acks [1053 1100 1117 1071 1100 1092 1072 1043 ] 8648 -SS All_acks_no_sharers [1695 1766 1800 1807 1768 1753 1826 1778 ] 14193 +SS L1_to_L2 [947 753 688 1089 794 730 802 724 ] 6527 +SS Ack [2970 3156 2850 3268 3274 3271 3096 3116 ] 25001 +SS Shared_Ack [3 2 4 1 3 2 5 2 ] 22 +SS All_acks [1073 1133 1040 1146 1126 1092 1084 1065 ] 8759 +SS All_acks_no_sharers [1772 1779 1810 1772 1803 1844 1808 1794 ] 14382 SS Flush_line [0 0 0 0 0 0 0 0 ] 0 -OI Load [0 0 1 0 0 1 1 1 ] 4 +OI Load [0 0 0 0 1 0 0 0 ] 1 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 OI Store [1 0 0 0 0 0 0 0 ] 1 OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 @@ -607,21 +636,21 @@ OI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OI Invalidate [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack [1051 948 995 1015 1015 1062 1050 955 ] 8091 +OI Writeback_Ack [1038 1028 1001 1027 1019 1025 1070 1001 ] 8209 OI Flush_line [0 0 0 0 0 0 0 0 ] 0 -MI Load [13 12 11 7 11 12 9 8 ] 83 +MI Load [12 8 11 9 11 10 9 9 ] 79 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [3 7 9 7 4 4 4 6 ] 44 +MI Store [4 1 4 7 6 3 5 7 ] 37 MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MI Other_GETX [2 1 3 1 1 1 1 3 ] 13 -MI Other_GETS [5 5 4 1 4 2 2 5 ] 28 +MI Other_GETX [0 1 1 2 1 1 3 2 ] 11 +MI Other_GETS [4 3 1 1 2 3 1 1 ] 16 MI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MI Invalidate [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [71483 72018 71629 71116 72014 71991 71812 71675 ] 573738 +MI Writeback_Ack [71696 71652 71529 71505 71741 71368 71157 71777 ] 572425 MI Flush_line [0 0 0 0 0 0 0 0 ] 0 II Load [0 0 0 0 0 0 0 0 ] 0 @@ -634,79 +663,44 @@ II Other_GETS [0 0 0 0 0 0 0 0 ] 0 II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 II NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 II Invalidate [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack [2 1 3 1 1 1 1 3 ] 13 +II Writeback_Ack [0 1 1 2 1 1 3 2 ] 11 II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 II Flush_line [0 0 0 0 0 0 0 0 ] 0 -IT Load [1 1 0 0 1 1 1 0 ] 5 +IT Load [0 0 0 1 0 0 1 1 ] 3 IT Ifetch [0 0 0 0 0 0 0 0 ] 0 -IT Store [0 0 1 0 0 0 0 0 ] 1 +IT Store [0 1 2 1 0 1 0 0 ] 5 IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IT L1_to_L2 [12 0 0 0 12 0 2 0 ] 26 -IT Complete_L2_to_L1 [1 2 1 2 2 2 2 0 ] 12 -IT Other_GETX [0 0 0 0 0 0 0 0 ] 0 -IT Other_GETS [0 0 0 0 0 0 0 0 ] 0 -IT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -IT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -IT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -IT Invalidate [0 0 0 0 0 0 0 0 ] 0 -IT Flush_line [0 0 0 0 0 0 0 0 ] 0 - -ST Load [0 1 1 1 4 0 3 3 ] 13 +IT L1_to_L2 [0 0 10 32 0 11 5 0 ] 58 +IT Complete_L2_to_L1 [0 1 2 2 0 2 2 1 ] 10 + +ST Load [0 2 3 0 2 2 1 1 ] 11 ST Ifetch [0 0 0 0 0 0 0 0 ] 0 -ST Store [0 0 3 0 0 2 2 1 ] 8 +ST Store [0 0 0 2 0 0 1 0 ] 3 ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ST L1_to_L2 [0 10 26 3 13 17 13 15 ] 97 -ST Complete_L2_to_L1 [0 2 4 2 6 3 6 6 ] 29 -ST Other_GETX [0 0 0 0 0 0 0 0 ] 0 -ST Other_GETS [0 0 0 0 0 0 0 0 ] 0 -ST Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -ST Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -ST NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -ST Invalidate [0 0 0 0 0 0 0 0 ] 0 -ST Flush_line [0 0 0 0 0 0 0 0 ] 0 - -OT Load [0 2 2 0 0 3 1 1 ] 9 +ST L1_to_L2 [0 7 10 3 7 9 12 3 ] 51 +ST Complete_L2_to_L1 [4 2 5 3 3 4 2 3 ] 26 + +OT Load [1 0 0 0 0 0 0 0 ] 1 OT Ifetch [0 0 0 0 0 0 0 0 ] 0 -OT Store [0 1 0 0 1 0 0 0 ] 2 +OT Store [0 1 0 0 0 0 1 0 ] 2 OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OT L1_to_L2 [0 5 13 0 24 11 6 1 ] 60 -OT Complete_L2_to_L1 [0 4 2 0 1 3 2 2 ] 14 -OT Other_GETX [0 0 0 0 0 0 0 0 ] 0 -OT Other_GETS [0 0 0 0 0 0 0 0 ] 0 -OT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -OT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -OT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -OT Invalidate [0 0 0 0 0 0 0 0 ] 0 -OT Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MT Load [21 23 17 28 29 37 25 17 ] 197 +OT L1_to_L2 [9 1 0 0 0 0 0 0 ] 10 +OT Complete_L2_to_L1 [1 1 1 0 1 0 2 0 ] 6 + +MT Load [12 12 28 19 15 22 15 19 ] 142 MT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MT Store [13 9 10 11 16 11 16 13 ] 99 +MT Store [20 11 8 8 14 8 11 4 ] 84 MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MT L1_to_L2 [180 244 176 228 184 237 183 166 ] 1598 -MT Complete_L2_to_L1 [60 45 42 62 65 71 61 47 ] 453 -MT Other_GETX [0 0 0 0 0 0 0 0 ] 0 -MT Other_GETS [0 0 0 0 0 0 0 0 ] 0 -MT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -MT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -MT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -MT Invalidate [0 0 0 0 0 0 0 0 ] 0 -MT Flush_line [0 0 0 0 0 0 0 0 ] 0 - -MMT Load [11 7 15 14 15 11 11 12 ] 96 +MT L1_to_L2 [149 113 176 175 166 136 119 151 ] 1185 +MT Complete_L2_to_L1 [44 35 54 51 42 49 41 37 ] 353 + +MMT Load [11 15 9 10 13 10 12 13 ] 93 MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMT Store [0 7 1 9 5 9 4 4 ] 39 +MMT Store [4 4 8 7 9 6 4 7 ] 49 MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MMT L1_to_L2 [77 74 84 97 78 129 98 78 ] 715 -MMT Complete_L2_to_L1 [22 22 23 31 32 30 25 30 ] 215 -MMT Other_GETX [0 0 0 0 0 0 0 0 ] 0 -MMT Other_GETS [0 0 0 0 0 0 0 0 ] 0 -MMT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 -MMT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 -MMT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 -MMT Invalidate [0 0 0 0 0 0 0 0 ] 0 -MMT Flush_line [0 0 0 0 0 0 0 0 ] 0 +MMT L1_to_L2 [72 118 88 98 174 75 78 93 ] 796 +MMT Complete_L2_to_L1 [20 29 26 25 32 28 25 25 ] 210 MI_F Load [0 0 0 0 0 0 0 0 ] 0 MI_F Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -804,28 +798,28 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 77473 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 77473 + system.l1_cntrl1.L1DcacheMemory_total_misses: 76911 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76911 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.6832% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.3168% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.6605% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.3395% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 77473 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 76911 100% Cache Stats: system.l1_cntrl1.L2cacheMemory - system.l1_cntrl1.L2cacheMemory_total_misses: 77473 - system.l1_cntrl1.L2cacheMemory_total_demand_misses: 77473 + system.l1_cntrl1.L2cacheMemory_total_misses: 76911 + system.l1_cntrl1.L2cacheMemory_total_demand_misses: 76911 system.l1_cntrl1.L2cacheMemory_total_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L2cacheMemory_request_type_LD: 64.6832% - system.l1_cntrl1.L2cacheMemory_request_type_ST: 35.3168% + system.l1_cntrl1.L2cacheMemory_request_type_LD: 64.6605% + system.l1_cntrl1.L2cacheMemory_request_type_ST: 35.3395% - system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor: 77473 100% + system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor: 76911 100% Cache Stats: system.l1_cntrl2.L1IcacheMemory system.l1_cntrl2.L1IcacheMemory_total_misses: 0 @@ -836,28 +830,28 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory Cache Stats: system.l1_cntrl2.L1DcacheMemory - system.l1_cntrl2.L1DcacheMemory_total_misses: 77332 - system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 77332 + system.l1_cntrl2.L1DcacheMemory_total_misses: 76638 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76638 system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.8865% - system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.1135% + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 65.05% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 34.95% - system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 77332 100% + system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76638 100% Cache Stats: system.l1_cntrl2.L2cacheMemory - system.l1_cntrl2.L2cacheMemory_total_misses: 77332 - system.l1_cntrl2.L2cacheMemory_total_demand_misses: 77332 + system.l1_cntrl2.L2cacheMemory_total_misses: 76638 + system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76638 system.l1_cntrl2.L2cacheMemory_total_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L2cacheMemory_request_type_LD: 64.8865% - system.l1_cntrl2.L2cacheMemory_request_type_ST: 35.1135% + system.l1_cntrl2.L2cacheMemory_request_type_LD: 65.05% + system.l1_cntrl2.L2cacheMemory_request_type_ST: 34.95% - system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor: 77332 100% + system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor: 76638 100% Cache Stats: system.l1_cntrl3.L1IcacheMemory system.l1_cntrl3.L1IcacheMemory_total_misses: 0 @@ -868,28 +862,28 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory Cache Stats: system.l1_cntrl3.L1DcacheMemory - system.l1_cntrl3.L1DcacheMemory_total_misses: 77107 - system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 77107 + system.l1_cntrl3.L1DcacheMemory_total_misses: 77136 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 77136 system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.0226% - system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.9774% + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.0474% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.9526% - system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 77107 100% + system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 77136 100% Cache Stats: system.l1_cntrl3.L2cacheMemory - system.l1_cntrl3.L2cacheMemory_total_misses: 77107 - system.l1_cntrl3.L2cacheMemory_total_demand_misses: 77107 + system.l1_cntrl3.L2cacheMemory_total_misses: 77136 + system.l1_cntrl3.L2cacheMemory_total_demand_misses: 77136 system.l1_cntrl3.L2cacheMemory_total_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L2cacheMemory_request_type_LD: 65.0226% - system.l1_cntrl3.L2cacheMemory_request_type_ST: 34.9774% + system.l1_cntrl3.L2cacheMemory_request_type_LD: 65.0474% + system.l1_cntrl3.L2cacheMemory_request_type_ST: 34.9526% - system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor: 77107 100% + system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor: 77136 100% Cache Stats: system.l1_cntrl4.L1IcacheMemory system.l1_cntrl4.L1IcacheMemory_total_misses: 0 @@ -900,28 +894,28 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory Cache Stats: system.l1_cntrl4.L1DcacheMemory - system.l1_cntrl4.L1DcacheMemory_total_misses: 76879 - system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76879 + system.l1_cntrl4.L1DcacheMemory_total_misses: 77072 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 77072 system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L1DcacheMemory_request_type_LD: 65.2103% - system.l1_cntrl4.L1DcacheMemory_request_type_ST: 34.7897% + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.9847% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.0153% - system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76879 100% + system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 77072 100% Cache Stats: system.l1_cntrl4.L2cacheMemory - system.l1_cntrl4.L2cacheMemory_total_misses: 76879 - system.l1_cntrl4.L2cacheMemory_total_demand_misses: 76879 + system.l1_cntrl4.L2cacheMemory_total_misses: 77072 + system.l1_cntrl4.L2cacheMemory_total_demand_misses: 77072 system.l1_cntrl4.L2cacheMemory_total_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L2cacheMemory_request_type_LD: 65.2103% - system.l1_cntrl4.L2cacheMemory_request_type_ST: 34.7897% + system.l1_cntrl4.L2cacheMemory_request_type_LD: 64.9847% + system.l1_cntrl4.L2cacheMemory_request_type_ST: 35.0153% - system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor: 76879 100% + system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor: 77072 100% Cache Stats: system.l1_cntrl5.L1IcacheMemory system.l1_cntrl5.L1IcacheMemory_total_misses: 0 @@ -932,28 +926,28 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory Cache Stats: system.l1_cntrl5.L1DcacheMemory - system.l1_cntrl5.L1DcacheMemory_total_misses: 77334 - system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77334 + system.l1_cntrl5.L1DcacheMemory_total_misses: 77098 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77098 system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.0904% - system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.9096% + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.6917% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.3083% - system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 77334 100% + system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 77098 100% Cache Stats: system.l1_cntrl5.L2cacheMemory - system.l1_cntrl5.L2cacheMemory_total_misses: 77334 - system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77334 + system.l1_cntrl5.L2cacheMemory_total_misses: 77098 + system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77098 system.l1_cntrl5.L2cacheMemory_total_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L2cacheMemory_request_type_LD: 65.0904% - system.l1_cntrl5.L2cacheMemory_request_type_ST: 34.9096% + system.l1_cntrl5.L2cacheMemory_request_type_LD: 64.6917% + system.l1_cntrl5.L2cacheMemory_request_type_ST: 35.3083% - system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor: 77334 100% + system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor: 77098 100% Cache Stats: system.l1_cntrl6.L1IcacheMemory system.l1_cntrl6.L1IcacheMemory_total_misses: 0 @@ -964,28 +958,28 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory Cache Stats: system.l1_cntrl6.L1DcacheMemory - system.l1_cntrl6.L1DcacheMemory_total_misses: 77132 - system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 77132 + system.l1_cntrl6.L1DcacheMemory_total_misses: 76971 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76971 system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.9238% - system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.0762% + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 65.3441% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 34.6559% - system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 77132 100% + system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76971 100% Cache Stats: system.l1_cntrl6.L2cacheMemory - system.l1_cntrl6.L2cacheMemory_total_misses: 77132 - system.l1_cntrl6.L2cacheMemory_total_demand_misses: 77132 + system.l1_cntrl6.L2cacheMemory_total_misses: 76971 + system.l1_cntrl6.L2cacheMemory_total_demand_misses: 76971 system.l1_cntrl6.L2cacheMemory_total_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L2cacheMemory_request_type_LD: 64.9238% - system.l1_cntrl6.L2cacheMemory_request_type_ST: 35.0762% + system.l1_cntrl6.L2cacheMemory_request_type_LD: 65.3441% + system.l1_cntrl6.L2cacheMemory_request_type_ST: 34.6559% - system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor: 77132 100% + system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor: 76971 100% Cache Stats: system.l1_cntrl7.L1IcacheMemory system.l1_cntrl7.L1IcacheMemory_total_misses: 0 @@ -996,28 +990,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory Cache Stats: system.l1_cntrl7.L1DcacheMemory - system.l1_cntrl7.L1DcacheMemory_total_misses: 76656 - system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76656 + system.l1_cntrl7.L1DcacheMemory_total_misses: 77032 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77032 system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.9747% - system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.0253% + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 65.1444% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 34.8556% - system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 76656 100% + system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 77032 100% Cache Stats: system.l1_cntrl7.L2cacheMemory - system.l1_cntrl7.L2cacheMemory_total_misses: 76656 - system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76656 + system.l1_cntrl7.L2cacheMemory_total_misses: 77032 + system.l1_cntrl7.L2cacheMemory_total_demand_misses: 77032 system.l1_cntrl7.L2cacheMemory_total_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L2cacheMemory_request_type_LD: 64.9747% - system.l1_cntrl7.L2cacheMemory_request_type_ST: 35.0253% + system.l1_cntrl7.L2cacheMemory_request_type_LD: 65.1444% + system.l1_cntrl7.L2cacheMemory_request_type_ST: 34.8556% - system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor: 76656 100% + system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor: 77032 100% Cache Stats: system.dir_cntrl0.probeFilter system.dir_cntrl0.probeFilter_total_misses: 0 @@ -1028,42 +1022,42 @@ Cache Stats: system.dir_cntrl0.probeFilter Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 809970 - memory_reads: 596448 - memory_writes: 213496 - memory_refreshes: 40014 - memory_total_request_delays: 51602030 - memory_delays_per_request: 63.7086 - memory_delays_in_input_queue: 646180 - memory_delays_behind_head_of_bank_queue: 21076052 - memory_delays_stalled_at_head_of_bank_queue: 29879798 - memory_stalls_for_bank_busy: 4500380 + memory_total_requests: 808732 + memory_reads: 595464 + memory_writes: 213239 + memory_refreshes: 39950 + memory_total_request_delays: 51490960 + memory_delays_per_request: 63.6688 + memory_delays_in_input_queue: 644740 + memory_delays_behind_head_of_bank_queue: 21033206 + memory_delays_stalled_at_head_of_bank_queue: 29813014 + memory_stalls_for_bank_busy: 4502024 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 7593434 - memory_stalls_for_arbitration: 6101712 - memory_stalls_for_bus: 8274143 + memory_stalls_for_anti_starvation: 7572316 + memory_stalls_for_arbitration: 6089674 + memory_stalls_for_bus: 8254819 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2054053 - memory_stalls_for_read_read_turnaround: 1356076 - accesses_per_bank: 25444 25179 25313 25496 25529 25456 25605 25357 25603 25364 25411 25489 25081 25155 25324 25146 25289 25267 25373 25278 25317 25229 25358 25224 25162 24872 25264 24851 25233 25398 25551 25352 + memory_stalls_for_read_write_turnaround: 2040089 + memory_stalls_for_read_read_turnaround: 1354092 + accesses_per_bank: 25475 25139 25271 25488 25557 25416 25567 25333 25458 25373 25338 25458 25092 25108 25283 25098 25229 25311 25279 25201 25282 25211 25353 25102 25122 24801 25255 24809 25129 25398 25504 25292 --- Directory --- - Event Counts - -GETX [219229 ] 219229 -GETS [406399 ] 406399 -PUT [582062 ] 582062 -Unblock [13 ] 13 -UnblockS [22841 ] 22841 -UnblockM [593735 ] 593735 -Writeback_Clean [7984 ] 7984 -Writeback_Dirty [107 ] 107 -Writeback_Exclusive_Clean [360342 ] 360342 -Writeback_Exclusive_Dirty [213396 ] 213396 +GETX [218960 ] 218960 +GETS [405714 ] 405714 +PUT [580856 ] 580856 +Unblock [11 ] 11 +UnblockS [23141 ] 23141 +UnblockM [592326 ] 592326 +Writeback_Clean [8089 ] 8089 +Writeback_Dirty [120 ] 120 +Writeback_Exclusive_Clean [359292 ] 359292 +Writeback_Exclusive_Dirty [213131 ] 213131 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [596443 ] 596443 -Memory_Ack [213496 ] 213496 +Memory_Data [595460 ] 595460 +Memory_Ack [213239 ] 213239 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 @@ -1072,22 +1066,22 @@ Exclusive_Data [0 ] 0 All_acks_and_shared_data [0 ] 0 All_acks_and_owner_data [0 ] 0 All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [40 ] 40 +All_Unblocks [35 ] 35 GETF [0 ] 0 PUTF [0 ] 0 - Transitions - -NX GETX [72 ] 72 -NX GETS [97 ] 97 -NX PUT [8104 ] 8104 +NX GETX [58 ] 58 +NX GETS [89 ] 89 +NX PUT [8220 ] 8220 NX Pf_Replacement [0 ] 0 NX DMA_READ [0 ] 0 NX DMA_WRITE [0 ] 0 NX GETF [0 ] 0 -NO GETX [7030 ] 7030 -NO GETS [12895 ] 12895 -NO PUT [573738 ] 573738 +NO GETX [6952 ] 6952 +NO GETS [12875 ] 12875 +NO PUT [572425 ] 572425 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 @@ -1101,16 +1095,16 @@ S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 S GETF [0 ] 0 -O GETX [8004 ] 8004 -O GETS [14563 ] 14563 +O GETX [8140 ] 8140 +O GETS [14773 ] 14773 O PUT [0 ] 0 O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O GETF [0 ] 0 -E GETX [200948 ] 200948 -E GETS [372952 ] 372952 +E GETX [200571 ] 200571 +E GETS [371997 ] 371997 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 @@ -1150,10 +1144,10 @@ NO_R All_acks_and_data_no_sharers [0 ] 0 NO_R GETF [0 ] 0 NO_B GETX [23 ] 23 -NO_B GETS [40 ] 40 -NO_B PUT [219 ] 219 -NO_B UnblockS [8209 ] 8209 -NO_B UnblockM [593701 ] 593701 +NO_B GETS [35 ] 35 +NO_B PUT [211 ] 211 +NO_B UnblockS [8312 ] 8312 +NO_B UnblockM [592289 ] 592289 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 @@ -1162,8 +1156,8 @@ NO_B GETF [0 ] 0 NO_B_X GETX [0 ] 0 NO_B_X GETS [0 ] 0 NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [12 ] 12 -NO_B_X UnblockM [11 ] 11 +NO_B_X UnblockS [9 ] 9 +NO_B_X UnblockM [14 ] 14 NO_B_X Pf_Replacement [0 ] 0 NO_B_X DMA_READ [0 ] 0 NO_B_X DMA_WRITE [0 ] 0 @@ -1172,7 +1166,7 @@ NO_B_X GETF [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [17 ] 17 +NO_B_S UnblockS [12 ] 12 NO_B_S UnblockM [23 ] 23 NO_B_S Pf_Replacement [0 ] 0 NO_B_S DMA_READ [0 ] 0 @@ -1181,43 +1175,43 @@ NO_B_S GETF [0 ] 0 NO_B_S_W GETX [0 ] 0 NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [1 ] 1 -NO_B_S_W UnblockS [40 ] 40 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [35 ] 35 NO_B_S_W Pf_Replacement [0 ] 0 NO_B_S_W DMA_READ [0 ] 0 NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [40 ] 40 +NO_B_S_W All_Unblocks [35 ] 35 NO_B_S_W GETF [0 ] 0 O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 -O_B UnblockS [14563 ] 14563 +O_B UnblockS [14773 ] 14773 O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 O_B GETF [0 ] 0 -NO_B_W GETX [1972 ] 1972 -NO_B_W GETS [3715 ] 3715 +NO_B_W GETX [2034 ] 2034 +NO_B_W GETS [3695 ] 3695 NO_B_W PUT [0 ] 0 NO_B_W UnblockS [0 ] 0 NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [581880 ] 581880 +NO_B_W Memory_Data [580687 ] 580687 NO_B_W GETF [0 ] 0 -O_B_W GETX [54 ] 54 -O_B_W GETS [83 ] 83 +O_B_W GETX [45 ] 45 +O_B_W GETS [103 ] 103 O_B_W PUT [0 ] 0 O_B_W UnblockS [0 ] 0 O_B_W Pf_Replacement [0 ] 0 O_B_W DMA_READ [0 ] 0 O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [14563 ] 14563 +O_B_W Memory_Data [14773 ] 14773 O_B_W GETF [0 ] 0 NO_W GETX [0 ] 0 @@ -1328,35 +1322,35 @@ O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 O_DR_B GETF [0 ] 0 -WB GETX [79 ] 79 -WB GETS [155 ] 155 +WB GETX [77 ] 77 +WB GETS [161 ] 161 WB PUT [0 ] 0 -WB Unblock [13 ] 13 -WB Writeback_Clean [7984 ] 7984 -WB Writeback_Dirty [107 ] 107 -WB Writeback_Exclusive_Clean [360342 ] 360342 -WB Writeback_Exclusive_Dirty [213396 ] 213396 +WB Unblock [11 ] 11 +WB Writeback_Clean [8089 ] 8089 +WB Writeback_Dirty [120 ] 120 +WB Writeback_Exclusive_Clean [359292 ] 359292 +WB Writeback_Exclusive_Dirty [213131 ] 213131 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 WB GETF [0 ] 0 -WB_O_W GETX [0 ] 0 -WB_O_W GETS [0 ] 0 +WB_O_W GETX [1 ] 1 +WB_O_W GETS [3 ] 3 WB_O_W PUT [0 ] 0 WB_O_W Pf_Replacement [0 ] 0 WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [107 ] 107 +WB_O_W Memory_Ack [120 ] 120 WB_O_W GETF [0 ] 0 -WB_E_W GETX [1047 ] 1047 -WB_E_W GETS [1899 ] 1899 +WB_E_W GETX [1059 ] 1059 +WB_E_W GETS [1983 ] 1983 WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [213389 ] 213389 +WB_E_W Memory_Ack [213119 ] 213119 WB_E_W GETF [0 ] 0 NO_F GETX [0 ] 0 @@ -1374,4 +1368,5 @@ NO_F_W Pf_Replacement [0 ] 0 NO_F_W DMA_READ [0 ] 0 NO_F_W DMA_WRITE [0 ] 0 NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF
\ No newline at end of file +NO_F_W GETF [0 ] 0 + diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index 4be47bd54..4cc740cdd 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -1,74 +1,74 @@ -system.cpu2: completed 10000 read, 5303 write accesses @1876789 -system.cpu6: completed 10000 read, 5467 write accesses @1901719 -system.cpu1: completed 10000 read, 5435 write accesses @1922051 -system.cpu7: completed 10000 read, 5297 write accesses @1933459 -system.cpu4: completed 10000 read, 5524 write accesses @1940138 -system.cpu5: completed 10000 read, 5406 write accesses @1942088 -system.cpu0: completed 10000 read, 5366 write accesses @1952899 -system.cpu3: completed 10000 read, 5440 write accesses @1977948 -system.cpu4: completed 20000 read, 10787 write accesses @3784460 -system.cpu6: completed 20000 read, 10802 write accesses @3793699 -system.cpu2: completed 20000 read, 10675 write accesses @3812149 -system.cpu5: completed 20000 read, 10824 write accesses @3843809 -system.cpu7: completed 20000 read, 10635 write accesses @3848309 -system.cpu1: completed 20000 read, 10760 write accesses @3864739 -system.cpu0: completed 20000 read, 10677 write accesses @3867909 -system.cpu3: completed 20000 read, 10802 write accesses @3932189 -system.cpu4: completed 30000 read, 16195 write accesses @5712798 -system.cpu2: completed 30000 read, 16031 write accesses @5729519 -system.cpu5: completed 30000 read, 16208 write accesses @5744739 -system.cpu1: completed 30000 read, 16141 write accesses @5773879 -system.cpu7: completed 30000 read, 16141 write accesses @5780239 -system.cpu6: completed 30000 read, 16232 write accesses @5784103 -system.cpu0: completed 30000 read, 16012 write accesses @5799238 -system.cpu3: completed 30000 read, 16245 write accesses @5831409 -system.cpu5: completed 40000 read, 21576 write accesses @7645389 -system.cpu2: completed 40000 read, 21332 write accesses @7669349 -system.cpu4: completed 40000 read, 21616 write accesses @7685173 -system.cpu1: completed 40000 read, 21665 write accesses @7712158 -system.cpu0: completed 40000 read, 21358 write accesses @7717389 -system.cpu6: completed 40000 read, 21602 write accesses @7718461 -system.cpu3: completed 40000 read, 21484 write accesses @7735829 -system.cpu7: completed 40000 read, 21641 write accesses @7781308 -system.cpu2: completed 50000 read, 26834 write accesses @9615299 -system.cpu0: completed 50000 read, 26760 write accesses @9622459 -system.cpu3: completed 50000 read, 26814 write accesses @9627019 -system.cpu5: completed 50000 read, 27114 write accesses @9630983 -system.cpu4: completed 50000 read, 27066 write accesses @9656028 -system.cpu6: completed 50000 read, 27209 write accesses @9657908 -system.cpu1: completed 50000 read, 27012 write accesses @9661059 -system.cpu7: completed 50000 read, 26974 write accesses @9754120 -system.cpu2: completed 60000 read, 32159 write accesses @11510528 -system.cpu5: completed 60000 read, 32406 write accesses @11518191 -system.cpu6: completed 60000 read, 32617 write accesses @11553009 -system.cpu3: completed 60000 read, 32203 write accesses @11554678 -system.cpu0: completed 60000 read, 32053 write accesses @11566058 -system.cpu1: completed 60000 read, 32501 write accesses @11568721 -system.cpu4: completed 60000 read, 32470 write accesses @11604588 -system.cpu7: completed 60000 read, 32381 write accesses @11680099 -system.cpu2: completed 70000 read, 37529 write accesses @13430348 -system.cpu5: completed 70000 read, 37835 write accesses @13440518 -system.cpu6: completed 70000 read, 37972 write accesses @13479051 -system.cpu3: completed 70000 read, 37489 write accesses @13479829 -system.cpu0: completed 70000 read, 37464 write accesses @13498959 -system.cpu4: completed 70000 read, 37713 write accesses @13503400 -system.cpu1: completed 70000 read, 37879 write accesses @13506829 -system.cpu7: completed 70000 read, 37696 write accesses @13588959 -system.cpu2: completed 80000 read, 42898 write accesses @15336919 -system.cpu3: completed 80000 read, 42777 write accesses @15361220 -system.cpu5: completed 80000 read, 43096 write accesses @15388319 -system.cpu4: completed 80000 read, 42937 write accesses @15407799 -system.cpu0: completed 80000 read, 42740 write accesses @15414688 -system.cpu6: completed 80000 read, 43294 write accesses @15425669 -system.cpu1: completed 80000 read, 43269 write accesses @15452049 -system.cpu7: completed 80000 read, 42960 write accesses @15504918 -system.cpu2: completed 90000 read, 48377 write accesses @17274228 -system.cpu3: completed 90000 read, 48234 write accesses @17290569 -system.cpu5: completed 90000 read, 48524 write accesses @17330090 -system.cpu6: completed 90000 read, 48654 write accesses @17333398 -system.cpu0: completed 90000 read, 48119 write accesses @17336459 -system.cpu4: completed 90000 read, 48219 write accesses @17373599 -system.cpu1: completed 90000 read, 48746 write accesses @17384429 -system.cpu7: completed 90000 read, 48558 write accesses @17482399 -system.cpu2: completed 100000 read, 53807 write accesses @19206609 +system.cpu4: completed 10000 read, 5368 write accesses @1896819 +system.cpu0: completed 10000 read, 5327 write accesses @1910725 +system.cpu5: completed 10000 read, 5493 write accesses @1929799 +system.cpu2: completed 10000 read, 5341 write accesses @1933339 +system.cpu1: completed 10000 read, 5585 write accesses @1940439 +system.cpu7: completed 10000 read, 5510 write accesses @1944309 +system.cpu6: completed 10000 read, 5231 write accesses @1946469 +system.cpu3: completed 10000 read, 5461 write accesses @1963728 +system.cpu0: completed 20000 read, 10595 write accesses @3805359 +system.cpu2: completed 20000 read, 10586 write accesses @3820599 +system.cpu3: completed 20000 read, 10867 write accesses @3829429 +system.cpu4: completed 20000 read, 10761 write accesses @3846318 +system.cpu6: completed 20000 read, 10413 write accesses @3857570 +system.cpu5: completed 20000 read, 10874 write accesses @3859158 +system.cpu7: completed 20000 read, 10747 write accesses @3866018 +system.cpu1: completed 20000 read, 11096 write accesses @3900361 +system.cpu3: completed 30000 read, 16232 write accesses @5720598 +system.cpu2: completed 30000 read, 15880 write accesses @5740479 +system.cpu7: completed 30000 read, 16148 write accesses @5769618 +system.cpu0: completed 30000 read, 16080 write accesses @5774128 +system.cpu6: completed 30000 read, 15848 write accesses @5779758 +system.cpu4: completed 30000 read, 16090 write accesses @5782899 +system.cpu1: completed 30000 read, 16550 write accesses @5821028 +system.cpu5: completed 30000 read, 16439 write accesses @5824429 +system.cpu3: completed 40000 read, 21587 write accesses @7653178 +system.cpu0: completed 40000 read, 21623 write accesses @7670365 +system.cpu2: completed 40000 read, 21273 write accesses @7684699 +system.cpu7: completed 40000 read, 21445 write accesses @7713338 +system.cpu6: completed 40000 read, 21321 write accesses @7719841 +system.cpu4: completed 40000 read, 21451 write accesses @7726211 +system.cpu1: completed 40000 read, 21832 write accesses @7734179 +system.cpu5: completed 40000 read, 21913 write accesses @7792051 +system.cpu0: completed 50000 read, 27135 write accesses @9608539 +system.cpu4: completed 50000 read, 26878 write accesses @9641109 +system.cpu3: completed 50000 read, 27076 write accesses @9643149 +system.cpu6: completed 50000 read, 26709 write accesses @9646978 +system.cpu2: completed 50000 read, 26734 write accesses @9654151 +system.cpu7: completed 50000 read, 26876 write accesses @9682409 +system.cpu5: completed 50000 read, 27248 write accesses @9689700 +system.cpu1: completed 50000 read, 27302 write accesses @9695809 +system.cpu0: completed 60000 read, 32449 write accesses @11491779 +system.cpu3: completed 60000 read, 32401 write accesses @11561629 +system.cpu6: completed 60000 read, 32081 write accesses @11565049 +system.cpu7: completed 60000 read, 32080 write accesses @11566379 +system.cpu4: completed 60000 read, 32352 write accesses @11573283 +system.cpu5: completed 60000 read, 32718 write accesses @11575018 +system.cpu2: completed 60000 read, 32150 write accesses @11585149 +system.cpu1: completed 60000 read, 32680 write accesses @11632119 +system.cpu0: completed 70000 read, 37771 write accesses @13429459 +system.cpu7: completed 70000 read, 37234 write accesses @13447809 +system.cpu4: completed 70000 read, 37607 write accesses @13456099 +system.cpu6: completed 70000 read, 37614 write accesses @13484149 +system.cpu5: completed 70000 read, 38039 write accesses @13487310 +system.cpu3: completed 70000 read, 37787 write accesses @13523429 +system.cpu1: completed 70000 read, 38168 write accesses @13544389 +system.cpu2: completed 70000 read, 37479 write accesses @13559549 +system.cpu0: completed 80000 read, 43086 write accesses @15325259 +system.cpu4: completed 80000 read, 42854 write accesses @15364368 +system.cpu7: completed 80000 read, 42627 write accesses @15378763 +system.cpu6: completed 80000 read, 42741 write accesses @15379020 +system.cpu3: completed 80000 read, 43087 write accesses @15412649 +system.cpu5: completed 80000 read, 43504 write accesses @15439469 +system.cpu1: completed 80000 read, 43522 write accesses @15480429 +system.cpu2: completed 80000 read, 42764 write accesses @15493419 +system.cpu0: completed 90000 read, 48539 write accesses @17246629 +system.cpu5: completed 90000 read, 48747 write accesses @17277729 +system.cpu6: completed 90000 read, 48097 write accesses @17293679 +system.cpu4: completed 90000 read, 48405 write accesses @17331308 +system.cpu7: completed 90000 read, 48155 write accesses @17349560 +system.cpu3: completed 90000 read, 48566 write accesses @17362109 +system.cpu2: completed 90000 read, 48156 write accesses @17435789 +system.cpu1: completed 90000 read, 49002 write accesses @17469038 +system.cpu0: completed 100000 read, 53926 write accesses @19175808 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 71b9149bc..a28e6b92e 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 30 2011 15:20:24 -gem5 started Jun 30 2011 15:20:49 -gem5 executing on SC2B0622 +gem5 compiled Dec 1 2011 11:03:29 +gem5 started Dec 1 2011 11:03:44 +gem5 executing on SC2B0612 command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 19206609 because maximum number of loads reached +Exiting @ tick 19175808 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index e81cf3216..253ebdbe3 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.019207 # Number of seconds simulated -sim_ticks 19206609 # Number of ticks simulated +sim_seconds 0.019176 # Number of seconds simulated +sim_ticks 19175808 # Number of ticks simulated sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 127969 # Simulator tick rate (ticks/s) -host_mem_usage 358544 # Number of bytes of host memory used -host_seconds 150.09 # Real time elapsed on the host -system.cpu0.num_reads 99703 # number of read accesses completed -system.cpu0.num_writes 53386 # number of write accesses completed +host_tick_rate 134618 # Simulator tick rate (ticks/s) +host_mem_usage 381740 # Number of bytes of host memory used +host_seconds 142.45 # Real time elapsed on the host +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 53926 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99601 # number of read accesses completed -system.cpu1.num_writes 53869 # number of write accesses completed +system.cpu1.num_reads 98882 # number of read accesses completed +system.cpu1.num_writes 53707 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53807 # number of write accesses completed +system.cpu2.num_reads 98977 # number of read accesses completed +system.cpu2.num_writes 53060 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99908 # number of read accesses completed -system.cpu3.num_writes 53597 # number of write accesses completed +system.cpu3.num_reads 99594 # number of read accesses completed +system.cpu3.num_writes 53686 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99417 # number of read accesses completed -system.cpu4.num_writes 53278 # number of write accesses completed +system.cpu4.num_reads 99524 # number of read accesses completed +system.cpu4.num_writes 53497 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99735 # number of read accesses completed -system.cpu5.num_writes 53654 # number of write accesses completed +system.cpu5.num_reads 99742 # number of read accesses completed +system.cpu5.num_writes 53984 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99876 # number of read accesses completed -system.cpu6.num_writes 53791 # number of write accesses completed +system.cpu6.num_reads 99887 # number of read accesses completed +system.cpu6.num_writes 53292 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98943 # number of read accesses completed -system.cpu7.num_writes 53425 # number of write accesses completed +system.cpu7.num_reads 99347 # number of read accesses completed +system.cpu7.num_writes 53300 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index 7495f5af5..8c6320343 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000 type=System children=dir_cntrl0 l1_cntrl0 physmem ruby tester mem_mode=timing +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -31,6 +32,7 @@ number_of_TBEs=256 probeFilter=system.dir_cntrl0.probeFilter probe_filter_enabled=false recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 @@ -73,9 +75,9 @@ start_index_bit=6 [system.l1_cntrl0] type=L1Cache_Controller -children=L2cacheMemory -L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache -L1IcacheMemory=system.ruby.cpu_ruby_ports.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 cache_response_latency=10 @@ -85,10 +87,27 @@ l2_cache_hit_latency=10 no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.cpu_ruby_ports +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 @@ -97,6 +116,21 @@ replacement_policy=PSEUDO_LRU size=512 start_index_bit=6 +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=false +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + [system.physmem] type=PhysicalMemory file= @@ -105,52 +139,18 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.cpu_ruby_ports.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem -children=cpu_ruby_ports network profiler tracer +children=network profiler tracer block_size_bytes=64 clock=1 mem_size=134217728 -network=system.ruby.network no_mem_vec=false -profiler=system.ruby.profiler random_seed=1234 randomization=true stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports] -type=RubySequencer -children=dcache icache -access_phys_mem=true -dcache=system.ruby.cpu_ruby_ports.dcache -deadlock_threshold=500000 -icache=system.ruby.cpu_ruby_ports.icache -max_outstanding_requests=16 -physmem=system.physmem -using_network_tester=false -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=system.tester.cpuPort[0] - -[system.ruby.cpu_ruby_ports.dcache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.ruby.cpu_ruby_ports.icache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 [system.ruby.network] type=SimpleNetwork @@ -160,6 +160,7 @@ buffer_size=0 control_msg_size=8 endpoint_bandwidth=1000 number_of_virtual_networks=10 +ruby_system=system.ruby topology=system.ruby.network.topology [system.ruby.network.topology] @@ -224,9 +225,11 @@ type=RubyProfiler all_instructions=false hot_lines=false num_of_sequencers=1 +ruby_system=system.ruby [system.ruby.tracer] type=RubyTracer +ruby_system=system.ruby warmup_length=100000 [system.tester] @@ -235,5 +238,5 @@ check_flush=false checks_to_complete=100 deadlock_threshold=50000 wakeup_frequency=10 -cpuPort=system.ruby.cpu_ruby_ports.port[0] +cpuPort=system.l1_cntrl0.sequencer.port[0] diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index c1643d6d6..bb46babb6 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Apr/28/2011 15:12:18 +Real time: Dec/01/2011 11:03:43 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.47 -Virtual_time_in_minutes: 0.00783333 -Virtual_time_in_hours: 0.000130556 -Virtual_time_in_days: 5.43981e-06 +Virtual_time_in_seconds: 0.46 +Virtual_time_in_minutes: 0.00766667 +Virtual_time_in_hours: 0.000127778 +Virtual_time_in_days: 5.32407e-06 -Ruby_current_time: 218861 +Ruby_current_time: 208411 Ruby_start_time: 0 -Ruby_cycles: 218861 +Ruby_cycles: 208411 -mbytes_resident: 35.7695 -mbytes_total: 219.633 -resident_ratio: 0.162914 +mbytes_resident: 37.7227 +mbytes_total: 242.977 +resident_ratio: 0.155268 -ruby_cycles_executed: [ 218862 ] +ruby_cycles_executed: [ 208412 ] Busy Controller Counts: L1Cache-0:0 @@ -65,17 +65,17 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1005 average: 15.808 | standard deviation: 1.13264 | 0 1 1 1 1 1 1 1 1 1 1 1 1 2 4 65 922 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 956 average: 15.7887 | standard deviation: 1.16133 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 5 75 863 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 15144 count: 990 average: 3497.61 | standard deviation: 1761.96 | 94 4 26 34 22 11 5 2 0 0 2 0 0 2 0 0 1 0 1 0 0 1 3 1 3 8 16 24 44 55 84 62 81 68 73 52 45 41 35 22 24 22 9 3 1 2 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 32 max: 5449 count: 40 average: 3885.72 | standard deviation: 1329.57 | 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 2 1 0 4 1 0 0 1 1 0 1 0 0 0 0 2 0 1 0 0 1 0 1 1 0 0 0 3 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 ] -miss_latency_ST: [binsize: 128 max: 15144 count: 890 average: 3688.06 | standard deviation: 1639.42 | 83 2 16 13 12 4 3 1 0 0 2 0 0 2 0 0 1 0 1 0 0 1 3 1 2 8 14 24 42 51 78 60 80 66 71 50 42 38 34 21 22 21 8 3 1 2 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 8 max: 999 count: 60 average: 413.883 | standard deviation: 232.639 | 6 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 5 1 1 0 0 1 0 1 0 0 0 0 0 1 3 4 3 0 2 1 0 0 1 0 0 0 2 1 1 2 0 1 1 0 1 0 0 0 0 1 2 1 3 0 0 0 0 1 0 0 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 13.2051 | standard deviation: 32.1294 | 0 21 15 17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 0 1 1 0 0 0 0 1 0 1 ] -miss_latency_L2Cache: [binsize: 128 max: 15144 count: 38 average: 3161.37 | standard deviation: 3572.78 | 16 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 2 1 1 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_Directory: [binsize: 32 max: 5926 count: 874 average: 3823.2 | standard deviation: 1334.21 | 0 0 0 0 0 2 2 0 9 7 2 8 16 4 3 11 4 1 10 6 1 5 4 1 0 2 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 1 0 1 0 1 1 2 1 1 4 3 2 6 4 2 7 7 8 8 9 15 10 13 13 8 20 17 18 24 23 18 9 19 15 21 21 16 22 24 8 21 13 24 18 15 15 16 12 12 10 9 11 11 12 12 5 11 13 7 10 10 8 2 9 8 3 5 10 6 3 9 4 5 4 6 1 2 0 2 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 64 max: 6811 count: 941 average: 3500.81 | standard deviation: 1691.94 | 69 9 9 1 10 4 14 20 8 15 4 7 3 4 5 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 7 1 9 8 8 18 13 21 17 21 28 37 31 37 40 46 28 35 31 30 27 28 32 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 64 max: 6620 count: 49 average: 3597.61 | standard deviation: 1746.75 | 5 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 64 max: 6811 count: 841 average: 3677.95 | standard deviation: 1562.59 | 61 8 4 0 5 4 3 14 3 9 2 3 1 3 5 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 5 1 9 7 8 18 12 20 17 18 28 37 27 35 37 43 27 32 30 29 26 26 31 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1159 count: 51 average: 486.745 | standard deviation: 255.245 | 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 116 count: 70 average: 16.2571 | standard deviation: 35.3332 | 0 9 16 14 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 0 1 ] +miss_latency_L2Cache: [binsize: 32 max: 4640 count: 34 average: 2534.59 | standard deviation: 1878.68 | 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ] +miss_latency_Directory: [binsize: 64 max: 6811 count: 837 average: 3831.48 | standard deviation: 1383.91 | 0 0 9 1 9 4 14 19 7 15 4 7 2 4 4 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 6 1 8 8 8 16 12 19 17 21 27 36 30 35 39 45 28 35 30 27 27 27 31 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,15 +85,14 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_dir_Times: 874 -miss_latency_LD_L1Cache: [binsize: 1 max: 115 count: 2 average: 59 | standard deviation: 79.196 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_Directory: [binsize: 32 max: 5449 count: 38 average: 4087.13 | standard deviation: 1014.85 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 2 1 0 4 1 0 0 1 1 0 1 0 0 0 0 2 0 1 0 0 1 0 1 1 0 0 0 3 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 113 count: 75 average: 12.1333 | standard deviation: 30.4935 | 0 21 14 16 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 0 1 1 0 0 0 0 1 ] -miss_latency_ST_L2Cache: [binsize: 128 max: 15144 count: 30 average: 3999.4 | standard deviation: 3582.58 | 8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 2 1 1 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_ST_Directory: [binsize: 32 max: 5926 count: 785 average: 4027.37 | standard deviation: 1077.58 | 0 0 0 0 0 1 1 0 3 5 1 7 6 1 2 4 2 0 6 3 0 2 2 0 0 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 1 0 0 0 1 1 2 1 1 4 2 2 5 4 2 7 7 8 7 9 14 10 11 13 8 18 16 18 20 22 18 9 18 14 21 20 16 22 24 8 19 13 23 18 15 14 16 11 11 10 9 11 8 12 11 4 10 13 7 9 10 8 2 9 8 2 5 9 5 3 9 3 5 4 6 1 1 0 2 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 1 average: 2 | standard deviation: 0 | 0 0 1 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 108 count: 8 average: 18.75 | standard deviation: 36.0912 | 0 0 0 0 1 2 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_IFETCH_Directory: [binsize: 8 max: 999 count: 51 average: 483.941 | standard deviation: 174.07 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 5 1 1 0 0 1 0 1 0 0 0 0 0 1 3 4 3 0 2 1 0 0 1 0 0 0 2 1 1 2 0 1 1 0 1 0 0 0 0 1 2 1 3 0 0 0 0 1 0 0 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_dir_Times: 837 +miss_latency_LD_L1Cache: [binsize: 1 max: 104 count: 6 average: 19.8333 | standard deviation: 41.248 | 0 1 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 64 max: 6620 count: 43 average: 4096.84 | standard deviation: 1184.49 | 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 64 average: 15.9219 | standard deviation: 35.0852 | 0 8 16 12 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 0 1 ] +miss_latency_ST_L2Cache: [binsize: 32 max: 4640 count: 31 average: 2779.26 | standard deviation: 1783.63 | 5 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ] +miss_latency_ST_Directory: [binsize: 64 max: 6811 count: 746 average: 4029.46 | standard deviation: 1146.93 | 0 0 4 0 4 4 3 13 2 9 2 3 0 3 4 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 4 1 8 7 8 16 11 18 17 18 27 36 26 33 36 42 27 32 29 26 26 25 30 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 9 count: 3 average: 6.33333 | standard deviation: 3.08221 | 0 0 0 1 0 0 0 1 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1159 count: 48 average: 516.771 | standard deviation: 231.637 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -125,7 +124,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10373 +page_reclaims: 10661 page_faults: 0 swaps: 0 block_inputs: 0 @@ -134,98 +133,98 @@ block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 2625 21000 -total_msg_count_Response_Data: 2622 188784 -total_msg_count_Writeback_Data: 2342 168624 -total_msg_count_Writeback_Control: 5451 43608 -total_msg_count_Unblock_Control: 2615 20920 -total_msgs: 15655 total_bytes: 442936 +total_msg_count_Request_Control: 2511 20088 +total_msg_count_Response_Data: 2511 180792 +total_msg_count_Writeback_Data: 2248 161856 +total_msg_count_Writeback_Control: 5220 41760 +total_msg_count_Unblock_Control: 2506 20048 +total_msgs: 14996 total_bytes: 424544 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 2.10979 - links_utilized_percent_switch_0_link_0: 1.99487 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 2.2247 bw: 16000 base_latency: 1 +links_utilized_percent_switch_0: 2.12273 + links_utilized_percent_switch_0_link_0: 2.00637 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.23909 bw: 16000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 782 56304 [ 0 0 0 0 0 782 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 873 6984 [ 0 0 0 0 0 873 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 750 54000 [ 0 0 0 0 0 750 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 836 6688 [ 0 0 0 0 0 836 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 2.10727 - links_utilized_percent_switch_1_link_0: 2.21967 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 1.99487 bw: 16000 base_latency: 1 +links_utilized_percent_switch_1: 2.12153 + links_utilized_percent_switch_1_link_0: 2.23669 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 2.00637 bw: 16000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 874 6992 [ 0 0 874 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 780 56160 [ 0 0 0 0 0 780 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 871 6968 [ 0 0 0 0 0 871 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 2.10739 - links_utilized_percent_switch_2_link_0: 1.99487 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.2199 bw: 16000 base_latency: 1 +links_utilized_percent_switch_2: 2.12153 + links_utilized_percent_switch_2_link_0: 2.00637 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.23669 bw: 16000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 875 7000 [ 0 0 875 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 780 56160 [ 0 0 0 0 0 780 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 871 6968 [ 0 0 0 0 0 871 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.cpu_ruby_ports.icache - system.ruby.cpu_ruby_ports.icache_total_misses: 59 - system.ruby.cpu_ruby_ports.icache_total_demand_misses: 59 - system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 51 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 51 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 59 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 51 100% -Cache Stats: system.ruby.cpu_ruby_ports.dcache - system.ruby.cpu_ruby_ports.dcache_total_misses: 872 - system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 872 - system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 820 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 820 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 4.58716% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 95.4128% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.2439% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.7561% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 872 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 820 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 931 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 931 + system.l1_cntrl0.L2cacheMemory_total_misses: 871 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 871 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.29646% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.3663% - system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.33727% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.93685% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2078% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.85534% - system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 931 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 871 100% --- L1Cache --- - Event Counts - -Load [42 ] 42 -Ifetch [61 ] 61 -Store [922 ] 922 -L2_Replacement [869 ] 869 -L1_to_L2 [16473 ] 16473 -Trigger_L2_to_L1D [47 ] 47 -Trigger_L2_to_L1I [8 ] 8 -Complete_L2_to_L1 [55 ] 55 +Load [49 ] 49 +Ifetch [55 ] 55 +Store [863 ] 863 +L2_Replacement [830 ] 830 +L1_to_L2 [15990 ] 15990 +Trigger_L2_to_L1D [31 ] 31 +Trigger_L2_to_L1I [3 ] 3 +Complete_L2_to_L1 [34 ] 34 Other_GETX [0 ] 0 Other_GETS [0 ] 0 Merged_GETS [0 ] 0 @@ -236,18 +235,18 @@ Ack [0 ] 0 Shared_Ack [0 ] 0 Data [0 ] 0 Shared_Data [0 ] 0 -Exclusive_Data [874 ] 874 -Writeback_Ack [866 ] 866 +Exclusive_Data [837 ] 837 +Writeback_Ack [830 ] 830 Writeback_Nack [0 ] 0 All_acks [0 ] 0 -All_acks_no_sharers [873 ] 873 +All_acks_no_sharers [836 ] 836 Flush_line [0 ] 0 Block_Ack [0 ] 0 - Transitions - -I Load [39 ] 39 -I Ifetch [51 ] 51 -I Store [786 ] 786 +I Load [43 ] 43 +I Ifetch [48 ] 48 +I Store [746 ] 746 I L2_Replacement [0 ] 0 I L1_to_L2 [0 ] 0 I Trigger_L2_to_L1D [0 ] 0 @@ -290,10 +289,10 @@ O Flush_line [0 ] 0 M Load [0 ] 0 M Ifetch [0 ] 0 -M Store [2 ] 2 -M L2_Replacement [85 ] 85 -M L1_to_L2 [93 ] 93 -M Trigger_L2_to_L1D [8 ] 8 +M Store [0 ] 0 +M L2_Replacement [80 ] 80 +M L1_to_L2 [87 ] 87 +M Trigger_L2_to_L1D [7 ] 7 M Trigger_L2_to_L1I [0 ] 0 M Other_GETX [0 ] 0 M Other_GETS [0 ] 0 @@ -303,13 +302,13 @@ M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 M Flush_line [0 ] 0 -MM Load [2 ] 2 -MM Ifetch [9 ] 9 -MM Store [102 ] 102 -MM L2_Replacement [784 ] 784 -MM L1_to_L2 [833 ] 833 -MM Trigger_L2_to_L1D [39 ] 39 -MM Trigger_L2_to_L1I [8 ] 8 +MM Load [6 ] 6 +MM Ifetch [0 ] 0 +MM Store [63 ] 63 +MM L2_Replacement [750 ] 750 +MM L1_to_L2 [779 ] 779 +MM Trigger_L2_to_L1D [24 ] 24 +MM Trigger_L2_to_L1I [3 ] 3 MM Other_GETX [0 ] 0 MM Other_GETS [0 ] 0 MM Merged_GETS [0 ] 0 @@ -318,11 +317,40 @@ MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 MM Flush_line [0 ] 0 +IR Load [0 ] 0 +IR Ifetch [0 ] 0 +IR Store [0 ] 0 +IR L1_to_L2 [0 ] 0 +IR Flush_line [0 ] 0 + +SR Load [0 ] 0 +SR Ifetch [0 ] 0 +SR Store [0 ] 0 +SR L1_to_L2 [0 ] 0 +SR Flush_line [0 ] 0 + +OR Load [0 ] 0 +OR Ifetch [0 ] 0 +OR Store [0 ] 0 +OR L1_to_L2 [0 ] 0 +OR Flush_line [0 ] 0 + +MR Load [0 ] 0 +MR Ifetch [0 ] 0 +MR Store [7 ] 7 +MR L1_to_L2 [52 ] 52 + +MMR Load [0 ] 0 +MMR Ifetch [3 ] 3 +MMR Store [24 ] 24 +MMR L1_to_L2 [92 ] 92 +MMR Flush_line [0 ] 0 + IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 IM L2_Replacement [0 ] 0 -IM L1_to_L2 [10256 ] 10256 +IM L1_to_L2 [9590 ] 9590 IM Other_GETX [0 ] 0 IM Other_GETS [0 ] 0 IM Other_GETS_No_Mig [0 ] 0 @@ -330,7 +358,7 @@ IM NC_DMA_GETS [0 ] 0 IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 -IM Exclusive_Data [785 ] 785 +IM Exclusive_Data [746 ] 746 IM Flush_line [0 ] 0 SM Load [0 ] 0 @@ -377,25 +405,25 @@ M_W Load [0 ] 0 M_W Ifetch [0 ] 0 M_W Store [0 ] 0 M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [292 ] 292 +M_W L1_to_L2 [263 ] 263 M_W Ack [0 ] 0 -M_W All_acks_no_sharers [88 ] 88 +M_W All_acks_no_sharers [90 ] 90 M_W Flush_line [0 ] 0 MM_W Load [0 ] 0 MM_W Ifetch [0 ] 0 MM_W Store [1 ] 1 MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [4281 ] 4281 +MM_W L1_to_L2 [4391 ] 4391 MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [785 ] 785 +MM_W All_acks_no_sharers [746 ] 746 MM_W Flush_line [0 ] 0 IS Load [0 ] 0 IS Ifetch [0 ] 0 IS Store [0 ] 0 IS L2_Replacement [0 ] 0 -IS L1_to_L2 [576 ] 576 +IS L1_to_L2 [619 ] 619 IS Other_GETX [0 ] 0 IS Other_GETS [0 ] 0 IS Other_GETS_No_Mig [0 ] 0 @@ -405,7 +433,7 @@ IS Ack [0 ] 0 IS Shared_Ack [0 ] 0 IS Data [0 ] 0 IS Shared_Data [0 ] 0 -IS Exclusive_Data [89 ] 89 +IS Exclusive_Data [91 ] 91 IS Flush_line [0 ] 0 SS Load [0 ] 0 @@ -434,8 +462,8 @@ OI Writeback_Ack [0 ] 0 OI Flush_line [0 ] 0 MI Load [0 ] 0 -MI Ifetch [0 ] 0 -MI Store [2 ] 2 +MI Ifetch [3 ] 3 +MI Store [1 ] 1 MI L2_Replacement [0 ] 0 MI L1_to_L2 [0 ] 0 MI Other_GETX [0 ] 0 @@ -444,7 +472,7 @@ MI Merged_GETS [0 ] 0 MI Other_GETS_No_Mig [0 ] 0 MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 -MI Writeback_Ack [866 ] 866 +MI Writeback_Ack [830 ] 830 MI Flush_line [0 ] 0 II Load [0 ] 0 @@ -467,13 +495,6 @@ IT Store [0 ] 0 IT L2_Replacement [0 ] 0 IT L1_to_L2 [0 ] 0 IT Complete_L2_to_L1 [0 ] 0 -IT Other_GETX [0 ] 0 -IT Other_GETS [0 ] 0 -IT Merged_GETS [0 ] 0 -IT Other_GETS_No_Mig [0 ] 0 -IT NC_DMA_GETS [0 ] 0 -IT Invalidate [0 ] 0 -IT Flush_line [0 ] 0 ST Load [0 ] 0 ST Ifetch [0 ] 0 @@ -481,13 +502,6 @@ ST Store [0 ] 0 ST L2_Replacement [0 ] 0 ST L1_to_L2 [0 ] 0 ST Complete_L2_to_L1 [0 ] 0 -ST Other_GETX [0 ] 0 -ST Other_GETS [0 ] 0 -ST Merged_GETS [0 ] 0 -ST Other_GETS_No_Mig [0 ] 0 -ST NC_DMA_GETS [0 ] 0 -ST Invalidate [0 ] 0 -ST Flush_line [0 ] 0 OT Load [0 ] 0 OT Ifetch [0 ] 0 @@ -495,41 +509,20 @@ OT Store [0 ] 0 OT L2_Replacement [0 ] 0 OT L1_to_L2 [0 ] 0 OT Complete_L2_to_L1 [0 ] 0 -OT Other_GETX [0 ] 0 -OT Other_GETS [0 ] 0 -OT Merged_GETS [0 ] 0 -OT Other_GETS_No_Mig [0 ] 0 -OT NC_DMA_GETS [0 ] 0 -OT Invalidate [0 ] 0 -OT Flush_line [0 ] 0 - -MT Load [1 ] 1 + +MT Load [0 ] 0 MT Ifetch [0 ] 0 -MT Store [1 ] 1 +MT Store [2 ] 2 MT L2_Replacement [0 ] 0 -MT L1_to_L2 [25 ] 25 -MT Complete_L2_to_L1 [8 ] 8 -MT Other_GETX [0 ] 0 -MT Other_GETS [0 ] 0 -MT Merged_GETS [0 ] 0 -MT Other_GETS_No_Mig [0 ] 0 -MT NC_DMA_GETS [0 ] 0 -MT Invalidate [0 ] 0 -MT Flush_line [0 ] 0 +MT L1_to_L2 [52 ] 52 +MT Complete_L2_to_L1 [7 ] 7 MMT Load [0 ] 0 MMT Ifetch [1 ] 1 -MMT Store [28 ] 28 +MMT Store [19 ] 19 MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [117 ] 117 -MMT Complete_L2_to_L1 [47 ] 47 -MMT Other_GETX [0 ] 0 -MMT Other_GETS [0 ] 0 -MMT Merged_GETS [0 ] 0 -MMT Other_GETS_No_Mig [0 ] 0 -MMT NC_DMA_GETS [0 ] 0 -MMT Invalidate [0 ] 0 -MMT Flush_line [0 ] 0 +MMT L1_to_L2 [65 ] 65 +MMT Complete_L2_to_L1 [27 ] 27 MI_F Load [0 ] 0 MI_F Ifetch [0 ] 0 @@ -627,42 +620,42 @@ Cache Stats: system.dir_cntrl0.probeFilter Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 1654 - memory_reads: 874 - memory_writes: 780 - memory_refreshes: 456 - memory_total_request_delays: 1201 - memory_delays_per_request: 0.726119 - memory_delays_in_input_queue: 157 + memory_total_requests: 1586 + memory_reads: 837 + memory_writes: 749 + memory_refreshes: 435 + memory_total_request_delays: 1175 + memory_delays_per_request: 0.740858 + memory_delays_in_input_queue: 168 memory_delays_behind_head_of_bank_queue: 3 - memory_delays_stalled_at_head_of_bank_queue: 1041 - memory_stalls_for_bank_busy: 197 + memory_delays_stalled_at_head_of_bank_queue: 1004 + memory_stalls_for_bank_busy: 269 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 94 - memory_stalls_for_bus: 428 + memory_stalls_for_arbitration: 76 + memory_stalls_for_bus: 376 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 194 - memory_stalls_for_read_read_turnaround: 128 - accesses_per_bank: 53 40 52 100 61 73 71 45 32 60 50 44 54 57 43 49 54 47 51 56 44 55 51 40 46 56 45 41 40 49 48 47 + memory_stalls_for_read_write_turnaround: 160 + memory_stalls_for_read_read_turnaround: 123 + accesses_per_bank: 59 53 47 85 75 57 58 40 39 53 46 64 35 48 41 50 42 53 58 54 53 40 32 36 33 45 49 57 36 47 49 52 --- Directory --- - Event Counts - -GETX [785 ] 785 -GETS [89 ] 89 -PUT [923 ] 923 +GETX [747 ] 747 +GETS [92 ] 92 +PUT [900 ] 900 Unblock [0 ] 0 UnblockS [0 ] 0 -UnblockM [871 ] 871 +UnblockM [835 ] 835 Writeback_Clean [0 ] 0 Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [84 ] 84 -Writeback_Exclusive_Dirty [780 ] 780 +Writeback_Exclusive_Clean [79 ] 79 +Writeback_Exclusive_Dirty [749 ] 749 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [874 ] 874 -Memory_Ack [780 ] 780 +Memory_Data [837 ] 837 +Memory_Ack [749 ] 749 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 @@ -686,7 +679,7 @@ NX GETF [0 ] 0 NO GETX [0 ] 0 NO GETS [0 ] 0 -NO PUT [867 ] 867 +NO PUT [830 ] 830 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 @@ -708,8 +701,8 @@ O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O GETF [0 ] 0 -E GETX [785 ] 785 -E GETS [89 ] 89 +E GETX [746 ] 746 +E GETS [91 ] 91 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 @@ -750,9 +743,9 @@ NO_R GETF [0 ] 0 NO_B GETX [0 ] 0 NO_B GETS [0 ] 0 -NO_B PUT [56 ] 56 +NO_B PUT [70 ] 70 NO_B UnblockS [0 ] 0 -NO_B UnblockM [871 ] 871 +NO_B UnblockM [835 ] 835 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 @@ -806,7 +799,7 @@ NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [874 ] 874 +NO_B_W Memory_Data [837 ] 837 NO_B_W GETF [0 ] 0 O_B_W GETX [0 ] 0 @@ -927,14 +920,14 @@ O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 O_DR_B GETF [0 ] 0 -WB GETX [0 ] 0 -WB GETS [0 ] 0 +WB GETX [1 ] 1 +WB GETS [1 ] 1 WB PUT [0 ] 0 WB Unblock [0 ] 0 WB Writeback_Clean [0 ] 0 WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [84 ] 84 -WB Writeback_Exclusive_Dirty [780 ] 780 +WB Writeback_Exclusive_Clean [79 ] 79 +WB Writeback_Exclusive_Dirty [749 ] 749 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 @@ -955,7 +948,7 @@ WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [780 ] 780 +WB_E_W Memory_Ack [749 ] 749 WB_E_W GETF [0 ] 0 NO_F GETX [0 ] 0 @@ -973,4 +966,5 @@ NO_F_W Pf_Replacement [0 ] 0 NO_F_W DMA_READ [0 ] 0 NO_F_W DMA_WRITE [0 ] 0 NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF
\ No newline at end of file +NO_F_W GETF [0 ] 0 + diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 47b2b4303..02ed228c9 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 28 2011 15:11:39 -M5 started Apr 28 2011 15:12:18 -M5 executing on SC2B0617 -command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer +gem5 compiled Dec 1 2011 11:03:29 +gem5 started Dec 1 2011 11:03:42 +gem5 executing on SC2B0612 +command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 218861 because Ruby Tester completed +Exiting @ tick 208411 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 2719314ca..493c4848e 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 224908 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -host_tick_rate 1412316 # Simulator tick rate (ticks/s) +sim_seconds 0.000208 # Number of seconds simulated +sim_ticks 208411 # Number of ticks simulated sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000219 # Number of seconds simulated -sim_ticks 218861 # Number of ticks simulated +host_tick_rate 1657766 # Simulator tick rate (ticks/s) +host_mem_usage 248812 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host ---------- End Simulation Statistics ---------- |