diff options
Diffstat (limited to 'tests')
18 files changed, 4342 insertions, 4288 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 4e78c037e..d854aacb7 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -1,44 +1,44 @@ -Real time: Sep/01/2012 14:04:53 +Real time: Oct/08/2012 22:30:18 Profiler Stats -------------- -Elapsed_time_in_seconds: 96 -Elapsed_time_in_minutes: 1.6 -Elapsed_time_in_hours: 0.0266667 -Elapsed_time_in_days: 0.00111111 +Elapsed_time_in_seconds: 177 +Elapsed_time_in_minutes: 2.95 +Elapsed_time_in_hours: 0.0491667 +Elapsed_time_in_days: 0.00204861 -Virtual_time_in_seconds: 97.01 -Virtual_time_in_minutes: 1.61683 -Virtual_time_in_hours: 0.0269472 -Virtual_time_in_days: 0.0011228 +Virtual_time_in_seconds: 108.58 +Virtual_time_in_minutes: 1.80967 +Virtual_time_in_hours: 0.0301611 +Virtual_time_in_days: 0.00125671 -Ruby_current_time: 7277301 +Ruby_current_time: 7241726 Ruby_start_time: 0 -Ruby_cycles: 7277301 +Ruby_cycles: 7241726 -mbytes_resident: 65.2539 -mbytes_total: 400.625 -resident_ratio: 0.162919 +mbytes_resident: 69.0352 +mbytes_total: 408.93 +resident_ratio: 0.168829 -ruby_cycles_executed: [ 7277302 7277302 7277302 7277302 7277302 7277302 7277302 7277302 ] +ruby_cycles_executed: [ 7241727 7241727 7241727 7241727 7241727 7241727 7241727 7241727 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 -L2Cache-0:0 +L2Cache-0:3 Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 611958 average: 15.9984 | standard deviation: 0.127313 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 611838 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 609192 average: 15.9984 | standard deviation: 0.127608 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 609071 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 4313 count: 611830 average: 1522.26 | standard deviation: 914.155 | 26 63 5067 7488 7283 6990 7667 7910 8087 9056 8958 8733 8991 8823 8076 8211 7930 7441 7590 7247 7103 7130 6873 6585 6779 6594 6349 6537 6418 6279 6424 6111 6077 6255 6019 5877 6151 5976 5707 5955 5995 5730 5780 5873 5721 5941 5822 5671 5889 5918 5657 5778 5750 5724 5870 6037 5803 5741 5904 5835 6057 5989 5802 6194 5941 6118 6386 6421 6230 6321 6327 6349 6700 6549 6246 6358 6576 6215 6722 6386 6171 6277 6153 5786 5923 5716 5062 5223 4885 4600 4454 4110 3801 3539 3453 3026 2875 2608 2302 2111 1858 1616 1477 1311 1040 878 821 671 565 470 355 326 245 208 165 125 109 72 65 54 42 40 22 9 13 11 6 3 3 4 2 2 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 32 max: 4313 count: 397447 average: 1522.3 | standard deviation: 913.551 | 18 51 3238 4837 4716 4554 5025 5174 5182 5887 5756 5654 5844 5710 5243 5401 5071 4843 4945 4673 4596 4595 4508 4311 4373 4312 4181 4358 4217 4113 4110 3919 3997 4087 3891 3766 3989 3930 3649 3806 3966 3732 3732 3863 3699 3892 3781 3641 3866 3817 3686 3741 3698 3723 3812 3927 3833 3627 3828 3737 3999 3896 3776 3993 3950 3977 4112 4203 4043 4112 4163 4136 4344 4324 4106 4105 4272 4041 4385 4179 3936 4074 3993 3743 3854 3767 3298 3402 3162 2997 2858 2675 2443 2281 2280 1951 1846 1672 1526 1284 1201 1032 949 847 677 589 533 442 371 279 231 218 159 138 102 85 66 55 43 35 25 26 18 7 9 7 3 3 1 3 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 32 max: 4275 count: 214383 average: 1522.18 | standard deviation: 915.277 | 8 12 1829 2651 2567 2436 2642 2736 2905 3169 3202 3079 3147 3113 2833 2810 2859 2598 2645 2574 2507 2535 2365 2274 2406 2282 2168 2179 2201 2166 2314 2192 2080 2168 2128 2111 2162 2046 2058 2149 2029 1998 2048 2010 2022 2049 2041 2030 2023 2101 1971 2037 2052 2001 2058 2110 1970 2114 2076 2098 2058 2093 2026 2201 1991 2141 2274 2218 2187 2209 2164 2213 2356 2225 2140 2253 2304 2174 2337 2207 2235 2203 2160 2043 2069 1949 1764 1821 1723 1603 1596 1435 1358 1258 1173 1075 1029 936 776 827 657 584 528 464 363 289 288 229 194 191 124 108 86 70 63 40 43 17 22 19 17 14 4 2 4 4 3 0 2 1 1 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 32 max: 4313 count: 611830 average: 1522.26 | standard deviation: 914.155 | 26 63 5067 7488 7283 6990 7667 7910 8087 9056 8958 8733 8991 8823 8076 8211 7930 7441 7590 7247 7103 7130 6873 6585 6779 6594 6349 6537 6418 6279 6424 6111 6077 6255 6019 5877 6151 5976 5707 5955 5995 5730 5780 5873 5721 5941 5822 5671 5889 5918 5657 5778 5750 5724 5870 6037 5803 5741 5904 5835 6057 5989 5802 6194 5941 6118 6386 6421 6230 6321 6327 6349 6700 6549 6246 6358 6576 6215 6722 6386 6171 6277 6153 5786 5923 5716 5062 5223 4885 4600 4454 4110 3801 3539 3453 3026 2875 2608 2302 2111 1858 1616 1477 1311 1040 878 821 671 565 470 355 326 245 208 165 125 109 72 65 54 42 40 22 9 13 11 6 3 3 4 2 2 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 32 max: 4383 count: 609064 average: 1521.72 | standard deviation: 904.345 | 32 52 5032 7135 6956 6643 7191 7692 7792 8614 8860 8651 8682 8570 7933 7862 7577 7303 7302 7271 7062 7195 6946 6725 6833 6635 6455 6596 6541 6201 6624 6511 6268 6255 6263 6087 6050 6098 5817 6013 5906 5708 5879 6021 5759 6142 5961 5809 5992 6058 5686 5993 5964 5880 6049 6129 5922 6257 6156 6040 6165 6200 6079 6180 6338 6273 6409 6515 6301 6433 6453 6425 6490 6458 6243 6589 6514 6206 6187 6197 5840 6084 5882 5679 5479 5409 5143 5015 4750 4389 4254 3931 3638 3440 3180 2912 2715 2519 2208 2087 1800 1500 1453 1174 1000 847 776 652 629 441 400 293 280 202 175 122 97 90 67 46 43 38 33 17 14 11 7 2 0 3 3 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 4383 count: 395982 average: 1523.28 | standard deviation: 904.332 | 20 42 3225 4623 4496 4343 4630 5003 5040 5536 5791 5608 5660 5580 5219 5068 4891 4767 4685 4702 4528 4721 4473 4393 4459 4220 4196 4330 4200 3977 4284 4253 4221 4101 4053 4017 3945 3949 3724 3911 3776 3795 3832 3911 3735 4024 3904 3725 3880 3935 3680 3917 3893 3787 3999 3931 3846 4055 4009 3982 3973 4036 3961 4002 4206 4028 4181 4262 4081 4198 4216 4220 4228 4178 4065 4230 4216 4028 4007 4016 3853 3994 3873 3698 3572 3420 3376 3246 3120 2865 2772 2618 2375 2217 2056 1890 1755 1669 1446 1325 1201 967 942 792 666 573 493 409 420 285 260 183 196 134 104 76 60 56 43 31 29 27 20 10 10 9 4 2 0 2 3 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 32 max: 4219 count: 213082 average: 1518.82 | standard deviation: 904.363 | 12 10 1807 2512 2460 2300 2561 2689 2752 3078 3069 3043 3022 2990 2714 2794 2686 2536 2617 2569 2534 2474 2473 2332 2374 2415 2259 2266 2341 2224 2340 2258 2047 2154 2210 2070 2105 2149 2093 2102 2130 1913 2047 2110 2024 2118 2057 2084 2112 2123 2006 2076 2071 2093 2050 2198 2076 2202 2147 2058 2192 2164 2118 2178 2132 2245 2228 2253 2220 2235 2237 2205 2262 2280 2178 2359 2298 2178 2180 2181 1987 2090 2009 1981 1907 1989 1767 1769 1630 1524 1482 1313 1263 1223 1124 1022 960 850 762 762 599 533 511 382 334 274 283 243 209 156 140 110 84 68 71 46 37 34 24 15 14 11 13 7 4 2 3 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 32 max: 4383 count: 609064 average: 1521.72 | standard deviation: 904.345 | 32 52 5032 7135 6956 6643 7191 7692 7792 8614 8860 8651 8682 8570 7933 7862 7577 7303 7302 7271 7062 7195 6946 6725 6833 6635 6455 6596 6541 6201 6624 6511 6268 6255 6263 6087 6050 6098 5817 6013 5906 5708 5879 6021 5759 6142 5961 5809 5992 6058 5686 5993 5964 5880 6049 6129 5922 6257 6156 6040 6165 6200 6079 6180 6338 6273 6409 6515 6301 6433 6453 6425 6490 6458 6243 6589 6514 6206 6187 6197 5840 6084 5882 5679 5479 5409 5143 5015 4750 4389 4254 3931 3638 3440 3180 2912 2715 2519 2208 2087 1800 1500 1453 1174 1000 847 776 652 629 441 400 293 280 202 175 122 97 90 67 46 43 38 33 17 14 11 7 2 0 3 3 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -49,8 +49,8 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 32 max: 4313 count: 397447 average: 1522.3 | standard deviation: 913.551 | 18 51 3238 4837 4716 4554 5025 5174 5182 5887 5756 5654 5844 5710 5243 5401 5071 4843 4945 4673 4596 4595 4508 4311 4373 4312 4181 4358 4217 4113 4110 3919 3997 4087 3891 3766 3989 3930 3649 3806 3966 3732 3732 3863 3699 3892 3781 3641 3866 3817 3686 3741 3698 3723 3812 3927 3833 3627 3828 3737 3999 3896 3776 3993 3950 3977 4112 4203 4043 4112 4163 4136 4344 4324 4106 4105 4272 4041 4385 4179 3936 4074 3993 3743 3854 3767 3298 3402 3162 2997 2858 2675 2443 2281 2280 1951 1846 1672 1526 1284 1201 1032 949 847 677 589 533 442 371 279 231 218 159 138 102 85 66 55 43 35 25 26 18 7 9 7 3 3 1 3 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 32 max: 4275 count: 214383 average: 1522.18 | standard deviation: 915.277 | 8 12 1829 2651 2567 2436 2642 2736 2905 3169 3202 3079 3147 3113 2833 2810 2859 2598 2645 2574 2507 2535 2365 2274 2406 2282 2168 2179 2201 2166 2314 2192 2080 2168 2128 2111 2162 2046 2058 2149 2029 1998 2048 2010 2022 2049 2041 2030 2023 2101 1971 2037 2052 2001 2058 2110 1970 2114 2076 2098 2058 2093 2026 2201 1991 2141 2274 2218 2187 2209 2164 2213 2356 2225 2140 2253 2304 2174 2337 2207 2235 2203 2160 2043 2069 1949 1764 1821 1723 1603 1596 1435 1358 1258 1173 1075 1029 936 776 827 657 584 528 464 363 289 288 229 194 191 124 108 86 70 63 40 43 17 22 19 17 14 4 2 4 4 3 0 2 1 1 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 32 max: 4383 count: 395982 average: 1523.28 | standard deviation: 904.332 | 20 42 3225 4623 4496 4343 4630 5003 5040 5536 5791 5608 5660 5580 5219 5068 4891 4767 4685 4702 4528 4721 4473 4393 4459 4220 4196 4330 4200 3977 4284 4253 4221 4101 4053 4017 3945 3949 3724 3911 3776 3795 3832 3911 3735 4024 3904 3725 3880 3935 3680 3917 3893 3787 3999 3931 3846 4055 4009 3982 3973 4036 3961 4002 4206 4028 4181 4262 4081 4198 4216 4220 4228 4178 4065 4230 4216 4028 4007 4016 3853 3994 3873 3698 3572 3420 3376 3246 3120 2865 2772 2618 2375 2217 2056 1890 1755 1669 1446 1325 1201 967 942 792 666 573 493 409 420 285 260 183 196 134 104 76 60 56 43 31 29 27 20 10 10 9 4 2 0 2 3 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 32 max: 4219 count: 213082 average: 1518.82 | standard deviation: 904.363 | 12 10 1807 2512 2460 2300 2561 2689 2752 3078 3069 3043 3022 2990 2714 2794 2686 2536 2617 2569 2534 2474 2473 2332 2374 2415 2259 2266 2341 2224 2340 2258 2047 2154 2210 2070 2105 2149 2093 2102 2130 1913 2047 2110 2024 2118 2057 2084 2112 2123 2006 2076 2071 2093 2050 2198 2076 2202 2147 2058 2192 2164 2118 2178 2132 2245 2228 2253 2220 2235 2237 2205 2262 2280 2178 2359 2298 2178 2180 2181 1987 2090 2009 1981 1907 1989 1767 1769 1630 1524 1482 1313 1263 1223 1124 1022 960 850 762 762 599 533 511 382 334 274 283 243 209 156 140 110 84 68 71 46 37 34 24 15 14 11 13 7 4 2 3 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -64,11 +64,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 32 max: 1034 count: 4867383 average: 43.2933 | standard deviation: 103.966 | 4034737 47969 64568 49261 58426 69451 62594 82731 80896 76781 75237 58633 43373 29776 17256 8673 4184 1779 636 243 97 32 15 13 6 11 0 3 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 35 count: 3328667 average: 1.5584 | standard deviation: 2.56943 | 1936154 350513 185166 210372 242929 153355 64954 47498 47950 34387 18982 9856 6169 6314 5648 2554 1438 1052 828 845 502 260 201 294 212 72 42 37 41 22 7 3 7 1 0 2 ] - virtual_network_0_delay_cycles: [binsize: 32 max: 1034 count: 1538716 average: 133.578 | standard deviation: 149.193 | 706080 47959 64568 49261 58426 69451 62594 82731 80896 76781 75237 58633 43373 29776 17256 8673 4184 1779 636 243 97 32 15 13 6 11 0 3 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 25 count: 2735846 average: 1.39707 | standard deviation: 2.32903 | 1670179 261675 141846 181912 192399 108048 51007 39410 36263 24263 11588 5924 4361 3561 1833 664 358 318 143 55 19 12 4 3 0 1 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 35 count: 592821 average: 2.30293 | standard deviation: 3.37074 | 265975 88838 43320 28460 50530 45307 13947 8088 11687 10124 7394 3932 1808 2753 3815 1890 1080 734 685 790 483 248 197 291 212 71 42 37 41 22 7 3 7 1 0 2 ] +Total_delay_cycles: [binsize: 32 max: 952 count: 4846224 average: 43.4035 | standard deviation: 104.135 | 4016974 47560 64526 48517 56762 68543 61969 82126 81447 76639 75747 59781 43685 30031 16694 8420 4018 1770 625 240 88 19 15 14 2 5 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 36 count: 3314048 average: 1.55974 | standard deviation: 2.57179 | 1926624 349251 185241 209732 241115 152013 64921 47824 47858 34149 18961 9850 6180 6266 5686 2508 1383 1015 946 799 505 249 194 322 184 92 54 43 40 21 9 2 6 3 0 0 2 ] + virtual_network_0_delay_cycles: [binsize: 32 max: 952 count: 1532176 average: 133.91 | standard deviation: 149.354 | 702937 47549 64526 48517 56762 68543 61969 82126 81447 76639 75747 59781 43685 30031 16694 8420 4018 1770 625 240 88 19 15 14 2 5 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 25 count: 2723943 average: 1.39954 | standard deviation: 2.33322 | 1661493 260850 142045 181681 190785 107256 50879 39510 36191 24121 11843 5877 4326 3527 1931 668 356 306 184 50 28 21 11 2 1 1 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 36 count: 590105 average: 2.29925 | standard deviation: 3.36904 | 265131 88401 43196 28051 50330 44757 14042 8314 11667 10028 7118 3973 1854 2739 3755 1840 1027 709 762 749 477 228 183 320 183 91 54 43 40 21 9 2 6 3 0 0 2 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -80,219 +80,219 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 35 count: 3328667 average: 1.5584 | s Resource Usage -------------- page_size: 4096 -user_time: 96 +user_time: 108 system_time: 0 -page_reclaims: 9081 +page_reclaims: 10063 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 216 +block_outputs: 288 Network Stats ------------- -total_msg_count_Control: 3654905 29239240 -total_msg_count_Request_Control: 1774787 14198296 -total_msg_count_Response_Data: 4297389 309412008 -total_msg_count_Response_Control: 6351852 50814816 -total_msg_count_Writeback_Data: 1535181 110533032 -total_msg_count_Writeback_Control: 620712 4965696 -total_msgs: 18234826 total_bytes: 519163088 +total_msg_count_Control: 3638301 29106408 +total_msg_count_Request_Control: 1766634 14133072 +total_msg_count_Response_Data: 4276646 307918512 +total_msg_count_Response_Control: 6324088 50592704 +total_msg_count_Writeback_Data: 1529280 110108160 +total_msg_count_Writeback_Control: 619734 4957872 +total_msgs: 18154683 total_bytes: 516816728 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 5.43268 - links_utilized_percent_switch_0_link_0: 5.50698 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 5.35837 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 74016 592128 [ 74016 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 76403 5501016 [ 0 76403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 39876 319008 [ 0 39876 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 76406 611248 [ 76406 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 497 35784 [ 0 497 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 99877 799016 [ 0 24098 75779 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 63710 4587120 [ 14133 49577 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 25744 205952 [ 25744 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 5.46201 + links_utilized_percent_switch_0_link_0: 5.53282 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 5.39119 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 73926 591408 [ 73926 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 76379 5499288 [ 0 76379 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 40006 320048 [ 0 40006 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 76383 611064 [ 76383 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 512 36864 [ 0 512 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 99490 795920 [ 0 23747 75743 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 63815 4594680 [ 13991 49824 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 26015 208120 [ 26015 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 5.43716 - links_utilized_percent_switch_1_link_0: 5.50065 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 5.37367 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 73971 591768 [ 73971 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 76300 5493600 [ 0 76300 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 39926 319408 [ 0 39926 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 76303 610424 [ 76303 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 535 38520 [ 0 535 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 99445 795560 [ 0 23764 75681 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 63975 4606200 [ 14147 49828 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 25779 206232 [ 25779 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 5.4253 + links_utilized_percent_switch_1_link_0: 5.49606 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 5.35454 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 73557 588456 [ 73557 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 75881 5463432 [ 0 75881 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 39533 316264 [ 0 39533 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 75884 607072 [ 75884 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 520 37440 [ 0 520 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 99197 793576 [ 0 23932 75265 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 63372 4562784 [ 14117 49255 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 25413 203304 [ 25413 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 5.45523 - links_utilized_percent_switch_2_link_0: 5.52262 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 5.38784 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 74184 593472 [ 74184 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 76610 5515920 [ 0 76610 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 40125 321000 [ 0 40125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 76610 612880 [ 76610 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 5.44236 + links_utilized_percent_switch_2_link_0: 5.50655 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 5.37817 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 73625 589000 [ 73625 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 75997 5471784 [ 0 75997 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 39941 319528 [ 0 39941 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 76001 608008 [ 76001 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Response_Data: 501 36072 [ 0 501 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 99904 799232 [ 0 23896 76008 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 64139 4618008 [ 14210 49929 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 25905 207240 [ 25905 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 98970 791760 [ 0 23561 75409 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 63726 4588272 [ 14011 49715 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 25931 207448 [ 25931 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 5.42603 - links_utilized_percent_switch_3_link_0: 5.49535 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 5.3567 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 73932 591456 [ 73932 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 76240 5489280 [ 0 76240 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 39734 317872 [ 0 39734 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 76242 609936 [ 76242 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 531 38232 [ 0 531 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 99585 796680 [ 0 23943 75642 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 63711 4587192 [ 14093 49618 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 25642 205136 [ 25642 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 5.41946 + links_utilized_percent_switch_3_link_0: 5.48974 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 5.34917 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 73462 587696 [ 73462 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 75785 5456520 [ 0 75785 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 39577 316616 [ 0 39577 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 75788 606304 [ 75788 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 509 36648 [ 0 509 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 98898 791184 [ 0 23744 75154 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 63317 4558824 [ 13953 49364 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 25625 205000 [ 25625 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 5.45447 - links_utilized_percent_switch_4_link_0: 5.52271 bw: 16000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 5.38622 bw: 16000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 74244 593952 [ 74244 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 76611 5515992 [ 0 76611 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 40066 320528 [ 0 40066 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 76614 612912 [ 76614 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 489 35208 [ 0 489 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 99919 799352 [ 0 23911 76008 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Data: 64120 4616640 [ 14137 49983 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Control: 25929 207432 [ 25929 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 5.4773 + links_utilized_percent_switch_4_link_0: 5.54038 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 5.41421 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 74034 592272 [ 74034 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 76465 5505480 [ 0 76465 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 40219 321752 [ 0 40219 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 76468 611744 [ 76468 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 513 36936 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 99396 795168 [ 0 23616 75780 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 64177 4620744 [ 14123 50054 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 26091 208728 [ 26091 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 5.44063 - links_utilized_percent_switch_5_link_0: 5.51002 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 5.37125 bw: 16000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Request_Control: 74115 592920 [ 74115 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 76443 5503896 [ 0 76443 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 39859 318872 [ 0 39859 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 76446 611568 [ 76446 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 562 40464 [ 0 562 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 99784 798272 [ 0 23954 75830 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Data: 63855 4597560 [ 14076 49779 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Control: 25781 206248 [ 25781 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 5.42065 + links_utilized_percent_switch_5_link_0: 5.49059 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 5.35071 bw: 16000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Request_Control: 73575 588600 [ 73575 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 75798 5457456 [ 0 75798 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 39470 315760 [ 0 39470 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 75801 606408 [ 75801 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 460 33120 [ 0 460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 99010 792080 [ 0 23823 75187 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 63391 4564152 [ 13971 49420 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 25497 203976 [ 25497 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 5.49098 - links_utilized_percent_switch_6_link_0: 5.55717 bw: 16000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 5.4248 bw: 16000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 74607 596856 [ 74607 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 77065 5548680 [ 0 77065 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 40632 325056 [ 0 40632 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 77068 616544 [ 77068 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 525 37800 [ 0 525 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 100343 802744 [ 0 23907 76436 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Data: 64557 4648104 [ 14224 50333 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Control: 26409 211272 [ 26409 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 5.47953 + links_utilized_percent_switch_6_link_0: 5.54481 bw: 16000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 5.41425 bw: 16000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 74162 593296 [ 74162 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 76509 5508648 [ 0 76509 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 40342 322736 [ 0 40342 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 76511 612088 [ 76511 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 477 34344 [ 0 477 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 99721 797768 [ 0 23841 75880 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 64166 4619952 [ 14189 49977 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 26152 209216 [ 26152 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 5.41853 - links_utilized_percent_switch_7_link_0: 5.48871 bw: 16000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 5.34835 bw: 16000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 73752 590016 [ 73752 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 76149 5482728 [ 0 76149 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 39767 318136 [ 0 39767 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 76153 609224 [ 76153 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 476 34272 [ 0 476 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 99339 794712 [ 0 23801 75538 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Data: 63660 4583520 [ 14051 49609 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Control: 25715 205720 [ 25715 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 5.45478 + links_utilized_percent_switch_7_link_0: 5.52308 bw: 16000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 5.38648 bw: 16000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 73764 590112 [ 73764 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 76239 5489208 [ 0 76239 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 40018 320144 [ 0 40018 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 76242 609936 [ 76242 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 500 36000 [ 0 500 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 99388 795104 [ 0 23773 75615 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 63796 4593312 [ 14163 49633 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 25854 206832 [ 25854 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 74.1642 - links_utilized_percent_switch_8_link_0: 84.4959 bw: 16000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 63.8326 bw: 16000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Control: 611842 4894736 [ 611842 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Data: 607680 43752960 [ 0 607680 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 1404626 11237008 [ 0 797704 606922 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Data: 511727 36844344 [ 113071 398656 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Control: 206904 1655232 [ 206904 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Control: 606461 4851688 [ 606461 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 589144 4713152 [ 589144 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 820260 59058720 [ 0 820260 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 712640 5701120 [ 0 712640 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 74.1917 + links_utilized_percent_switch_8_link_0: 84.5438 bw: 16000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 63.8397 bw: 16000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Control: 609078 4872624 [ 609078 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Data: 604849 43549128 [ 0 604849 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 1397726 11181808 [ 0 793693 604033 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 509760 36702720 [ 112518 397242 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 206578 1652624 [ 206578 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Control: 603689 4829512 [ 603689 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 586424 4691392 [ 586424 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 816199 58766328 [ 0 816199 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 710282 5682256 [ 0 710282 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 30.8757 - links_utilized_percent_switch_9_link_0: 20.0839 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 41.6675 bw: 16000 base_latency: 1 +links_utilized_percent_switch_9: 30.8768 + links_utilized_percent_switch_9_link_0: 20.0728 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 41.6809 bw: 16000 base_latency: 1 - outgoing_messages_switch_9_link_0_Control: 606459 4851672 [ 606459 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Data: 213778 15392016 [ 0 213778 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 392673 3141384 [ 0 392673 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 606455 43664760 [ 0 606455 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 606448 4851584 [ 0 606448 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Control: 603689 4829512 [ 603689 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 212483 15298776 [ 0 212483 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 391197 3129576 [ 0 391197 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 603684 43465248 [ 0 603684 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 603678 4829424 [ 0 603678 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 14.8684 - links_utilized_percent_switch_10_link_0: 5.50698 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 5.50065 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 5.52265 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 5.49535 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 5.52271 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 5.51002 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 5.55717 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 5.48871 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 84.4959 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 20.0839 bw: 16000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Request_Control: 74016 592128 [ 74016 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 76403 5501016 [ 0 76403 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 39876 319008 [ 0 39876 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 73971 591768 [ 73971 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 76300 5493600 [ 0 76300 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 39926 319408 [ 0 39926 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 74184 593472 [ 74184 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 76610 5515920 [ 0 76610 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 40125 321000 [ 0 40125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 73932 591456 [ 73932 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 76240 5489280 [ 0 76240 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 39734 317872 [ 0 39734 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 74244 593952 [ 74244 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 76611 5515992 [ 0 76611 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 40066 320528 [ 0 40066 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 74116 592928 [ 74116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 76443 5503896 [ 0 76443 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 39859 318872 [ 0 39859 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 74607 596856 [ 74607 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 77065 5548680 [ 0 77065 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 40632 325056 [ 0 40632 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 73752 590016 [ 73752 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 76149 5482728 [ 0 76149 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 39767 318136 [ 0 39767 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 611842 4894736 [ 611842 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Data: 607680 43752960 [ 0 607680 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 1404626 11237008 [ 0 797704 606922 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Writeback_Data: 511727 36844344 [ 113071 398656 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Writeback_Control: 206904 1655232 [ 206904 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Control: 606459 4851672 [ 606459 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Response_Data: 213778 15392016 [ 0 213778 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Response_Control: 392673 3141384 [ 0 392673 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 14.8741 + links_utilized_percent_switch_10_link_0: 5.53282 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 5.49606 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 5.50655 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 5.48974 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 5.54038 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 5.49059 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 5.54484 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 5.52308 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 84.5438 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 20.0728 bw: 16000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Request_Control: 73926 591408 [ 73926 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 76379 5499288 [ 0 76379 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 40006 320048 [ 0 40006 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Request_Control: 73557 588456 [ 73557 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 75881 5463432 [ 0 75881 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 39533 316264 [ 0 39533 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Request_Control: 73625 589000 [ 73625 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 75997 5471784 [ 0 75997 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 39941 319528 [ 0 39941 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Request_Control: 73462 587696 [ 73462 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 75785 5456520 [ 0 75785 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 39577 316616 [ 0 39577 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Request_Control: 74034 592272 [ 74034 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 76465 5505480 [ 0 76465 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 40219 321752 [ 0 40219 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Request_Control: 73575 588600 [ 73575 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 75798 5457456 [ 0 75798 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 39470 315760 [ 0 39470 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Request_Control: 74162 593296 [ 74162 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 76509 5508648 [ 0 76509 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 40342 322736 [ 0 40342 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Request_Control: 73764 590112 [ 73764 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 76239 5489208 [ 0 76239 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 40018 320144 [ 0 40018 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 609078 4872624 [ 609078 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Data: 604850 43549200 [ 0 604850 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 1397726 11181808 [ 0 793693 604033 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Data: 509760 36702720 [ 112518 397242 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Control: 206578 1652624 [ 206578 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Control: 603689 4829512 [ 603689 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Data: 212483 15298776 [ 0 212483 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Control: 391197 3129576 [ 0 391197 0 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -303,97 +303,97 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 76406 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76406 + system.l1_cntrl0.L1DcacheMemory_total_misses: 76383 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76383 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.1035% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.8965% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.0171% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.9829% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 76406 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 76383 100% --- L1Cache --- - Event Counts - -Load [49757 49622 50229 49448 49745 49454 49723 49492 ] 397470 +Load [49632 49257 49946 49548 49664 49262 49408 49285 ] 396002 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26865 26828 26843 26709 26663 26852 26890 26752 ] 214402 -Inv [73894 73733 74240 73410 73675 73592 73825 73561 ] 589930 -L1_Replacement [534232 531606 536705 531280 533435 534953 534561 531949 ] 4268721 -Fwd_GETX [211 202 209 208 185 223 217 211 ] 1666 -Fwd_GETS [139 180 158 134 156 156 142 160 ] 1225 +Store [26839 26546 26565 26696 26722 26622 26595 26505 ] 213090 +Inv [73670 73243 73818 73406 73571 73187 73276 73108 ] 587279 +L1_Replacement [532333 529417 532129 531738 532441 529794 530672 526615 ] 4245139 +Fwd_GETX [215 204 211 216 198 220 197 199 ] 1660 +Fwd_GETS [149 128 133 142 157 150 152 155 ] 1166 Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -Data [0 1 1 1 0 1 5 0 ] 9 -Data_Exclusive [48999 48845 49423 48678 48983 48691 48968 48730 ] 391317 -DataS_fromL1 [147 163 170 155 135 140 154 161 ] 1225 -Data_all_Acks [27465 27434 27471 27315 27285 27468 27483 27349 ] 219270 -Ack [0 1 1 1 0 1 5 0 ] 9 -Ack_all [0 1 1 1 0 1 5 0 ] 9 -WB_Ack [40066 39857 40630 39765 39876 39924 40115 39734 ] 319967 +Data [3 2 1 1 1 2 1 0 ] 11 +Data_Exclusive [48810 48521 49136 48785 48877 48495 48668 48497 ] 389789 +DataS_fromL1 [133 123 180 136 146 148 148 152 ] 1166 +Data_all_Acks [27519 27152 27192 27317 27355 27236 27180 27136 ] 218087 +Ack [3 2 1 1 1 2 1 0 ] 11 +Ack_all [3 2 1 1 1 2 1 0 ] 11 +WB_Ack [40213 39466 40340 40016 40004 39529 39939 39577 ] 319084 - Transitions - -NP Load [49742 49615 50214 49434 49740 49448 49718 49480 ] 397391 +NP Load [49621 49248 49942 49538 49654 49253 49398 49274 ] 395928 NP Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP Store [26859 26816 26840 26704 26661 26849 26887 26747 ] 214363 -NP Inv [374 407 423 376 369 391 383 386 ] 3109 +NP Store [26832 26539 26563 26694 26719 26616 26583 26501 ] 213047 +NP Inv [419 398 403 385 434 402 386 384 ] 3211 NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -I Load [9 7 11 11 3 4 5 10 ] 60 +I Load [9 8 4 8 8 9 9 9 ] 64 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [4 8 3 4 2 2 2 4 ] 29 +I Store [6 6 2 2 2 6 11 4 ] 39 I Inv [0 0 0 0 0 0 0 0 ] 0 -I L1_Replacement [36211 36248 36066 36049 36208 36037 36160 36166 ] 289145 +I L1_Replacement [35875 35980 35802 35883 35989 35989 35706 35869 ] 287093 S Load [0 0 0 0 0 0 0 0 ] 0 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 0 0 0 0 0 1 ] 1 -S Inv [490 521 514 506 515 499 500 500 ] 4045 -S L1_Replacement [320 322 351 319 312 330 324 322 ] 2600 +S Store [0 0 0 0 0 0 0 0 ] 0 +S Inv [526 446 509 499 473 487 480 527 ] 3947 +S L1_Replacement [360 335 358 328 374 346 329 324 ] 2754 -E Load [1 0 1 1 0 0 0 0 ] 3 +E Load [1 0 0 2 2 0 0 0 ] 5 E Ifetch [0 0 0 0 0 0 0 0 ] 0 -E Store [0 1 0 0 0 0 0 0 ] 1 -E Inv [23022 22998 22950 22901 23183 22849 22999 23024 ] 183926 -E L1_Replacement [25929 25781 26409 25715 25744 25779 25907 25642 ] 206906 -E Fwd_GETX [44 52 57 50 49 56 52 55 ] 415 -E Fwd_GETS [4 12 7 12 7 6 10 9 ] 67 +E Store [0 0 0 0 0 0 0 0 ] 0 +E Inv [22649 22961 22900 22871 22808 23018 22673 22806 ] 182686 +E L1_Replacement [26091 25497 26152 25854 26015 25413 25931 25625 ] 206578 +E Fwd_GETX [56 56 77 52 47 55 52 61 ] 456 +E Fwd_GETS [14 7 7 7 7 9 12 5 ] 68 E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M Load [1 0 0 0 1 1 0 1 ] 4 +M Load [1 1 0 0 0 0 0 1 ] 3 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [0 0 0 1 0 0 0 0 ] 1 -M Inv [12638 12655 12534 12557 12440 12611 12592 12582 ] 100609 -M L1_Replacement [14137 14076 14224 14051 14133 14147 14210 14093 ] 113071 -M Fwd_GETX [31 36 26 49 27 28 26 19 ] 242 -M Fwd_GETS [56 56 59 48 61 64 59 57 ] 460 +M Store [0 1 0 0 1 0 1 0 ] 3 +M Inv [12634 12496 12296 12438 12637 12420 12491 12457 ] 99869 +M L1_Replacement [14123 13971 14189 14163 13991 14117 14011 13953 ] 112518 +M Fwd_GETX [26 36 26 32 34 25 30 32 ] 241 +M Fwd_GETS [54 40 53 61 58 60 61 63 ] 450 M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 -IS Inv [0 1 0 1 0 0 0 2 ] 4 -IS L1_Replacement [298131 295401 300826 295942 296751 297563 296802 294983 ] 2376399 -IS Data_Exclusive [48999 48845 49423 48678 48983 48691 48968 48730 ] 391317 -IS DataS_fromL1 [147 163 170 155 135 140 154 161 ] 1225 -IS Data_all_Acks [603 612 629 610 624 619 601 596 ] 4894 +IS Inv [0 0 1 1 0 0 0 0 ] 2 +IS L1_Replacement [296506 293946 298292 297271 296780 294917 296229 293551 ] 2367492 +IS Data_Exclusive [48810 48521 49136 48785 48877 48495 48668 48497 ] 389789 +IS DataS_fromL1 [133 123 180 136 146 148 148 152 ] 1166 +IS Data_all_Acks [685 611 627 623 636 616 588 631 ] 5017 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM Inv [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [159504 159778 158829 159204 160287 161097 161158 160743 ] 1280600 -IM Data [0 1 1 1 0 1 5 0 ] 9 -IM Data_all_Acks [26862 26821 26842 26704 26661 26849 26882 26751 ] 214372 +IM L1_Replacement [159378 159688 157336 158239 159292 159012 158466 157293 ] 1268704 +IM Data [3 2 1 1 1 2 1 0 ] 11 +IM Data_all_Acks [26834 26541 26564 26693 26719 26620 26592 26505 ] 213068 IM Ack [0 0 0 0 0 0 0 0 ] 0 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 -SM Inv [0 0 0 0 0 0 0 1 ] 1 +SM Inv [0 0 0 0 0 0 0 0 ] 0 SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM Ack [0 1 1 1 0 1 5 0 ] 9 -SM Ack_all [0 1 1 1 0 1 5 0 ] 9 +SM Ack [3 2 1 1 1 2 1 0 ] 11 +SM Ack_all [3 2 1 1 1 2 1 0 ] 11 IS_I Load [0 0 0 0 0 0 0 0 ] 0 IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -402,24 +402,24 @@ IS_I Inv [0 0 0 0 0 0 0 0 ] 0 IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 -IS_I Data_all_Acks [0 1 0 1 0 0 0 2 ] 4 +IS_I Data_all_Acks [0 0 1 1 0 0 0 0 ] 2 -M_I Load [0 0 0 0 0 0 0 1 ] 1 +M_I Load [0 0 0 0 0 0 0 0 ] 0 M_I Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_I Store [0 1 0 0 0 1 0 0 ] 2 -M_I Inv [37345 37124 37799 37052 37137 37217 37337 37036 ] 298047 +M_I Store [0 0 0 0 0 0 0 0 ] 0 +M_I Inv [37420 36924 37681 37195 37187 36835 37224 36907 ] 297373 M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_I Fwd_GETX [136 114 126 109 109 139 139 137 ] 1009 -M_I Fwd_GETS [79 112 92 74 88 86 73 94 ] 698 +M_I Fwd_GETX [133 112 108 132 117 140 115 106 ] 963 +M_I Fwd_GETS [81 81 73 74 92 81 79 87 ] 648 M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M_I WB_Ack [2506 2507 2616 2531 2543 2484 2566 2468 ] 20221 +M_I WB_Ack [2580 2351 2479 2616 2610 2474 2524 2478 ] 20112 -SINK_WB_ACK Load [4 0 3 2 1 1 0 0 ] 11 +SINK_WB_ACK Load [0 0 0 0 0 0 1 1 ] 2 SINK_WB_ACK Ifetch [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK Store [2 2 0 0 0 0 1 0 ] 5 -SINK_WB_ACK Inv [25 27 20 17 31 25 14 30 ] 189 +SINK_WB_ACK Store [1 0 0 0 0 0 0 0 ] 1 +SINK_WB_ACK Inv [22 18 28 17 32 25 22 27 ] 191 SINK_WB_ACK L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK WB_Ack [37560 37350 38014 37234 37333 37440 37549 37266 ] 299746 +SINK_WB_ACK WB_Ack [37633 37115 37861 37400 37394 37055 37415 37099 ] 298972 Cache Stats: system.l1_cntrl1.L1IcacheMemory system.l1_cntrl1.L1IcacheMemory_total_misses: 0 @@ -430,16 +430,16 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 76303 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76303 + system.l1_cntrl1.L1DcacheMemory_total_misses: 75884 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 75884 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.81% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.19% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.9175% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.0825% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 76303 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 75884 100% Cache Stats: system.l1_cntrl2.L1IcacheMemory system.l1_cntrl2.L1IcacheMemory_total_misses: 0 @@ -450,16 +450,16 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory Cache Stats: system.l1_cntrl2.L1DcacheMemory - system.l1_cntrl2.L1DcacheMemory_total_misses: 76612 - system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76612 + system.l1_cntrl2.L1DcacheMemory_total_misses: 76001 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76001 system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.9024% - system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.0976% + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 65.0084% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 34.9916% - system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76612 100% + system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76001 100% Cache Stats: system.l1_cntrl3.L1IcacheMemory system.l1_cntrl3.L1IcacheMemory_total_misses: 0 @@ -470,16 +470,16 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory Cache Stats: system.l1_cntrl3.L1DcacheMemory - system.l1_cntrl3.L1DcacheMemory_total_misses: 76242 - system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76242 + system.l1_cntrl3.L1DcacheMemory_total_misses: 75788 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 75788 system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L1DcacheMemory_request_type_LD: 64.9117% - system.l1_cntrl3.L1DcacheMemory_request_type_ST: 35.0883% + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.0274% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.9726% - system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 76242 100% + system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 75788 100% Cache Stats: system.l1_cntrl4.L1IcacheMemory system.l1_cntrl4.L1IcacheMemory_total_misses: 0 @@ -490,16 +490,16 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory Cache Stats: system.l1_cntrl4.L1DcacheMemory - system.l1_cntrl4.L1DcacheMemory_total_misses: 76614 - system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76614 + system.l1_cntrl4.L1DcacheMemory_total_misses: 76468 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76468 system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.9372% - system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.0628% + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.903% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.097% - system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76614 100% + system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76468 100% Cache Stats: system.l1_cntrl5.L1IcacheMemory system.l1_cntrl5.L1IcacheMemory_total_misses: 0 @@ -510,16 +510,16 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory Cache Stats: system.l1_cntrl5.L1DcacheMemory - system.l1_cntrl5.L1DcacheMemory_total_misses: 76446 - system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76446 + system.l1_cntrl5.L1DcacheMemory_total_misses: 75801 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 75801 system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.9112% - system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.0888% + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.9807% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.0193% - system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 76446 100% + system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 75801 100% Cache Stats: system.l1_cntrl6.L1IcacheMemory system.l1_cntrl6.L1IcacheMemory_total_misses: 0 @@ -530,16 +530,16 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory Cache Stats: system.l1_cntrl6.L1DcacheMemory - system.l1_cntrl6.L1DcacheMemory_total_misses: 77068 - system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 77068 + system.l1_cntrl6.L1DcacheMemory_total_misses: 76511 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76511 system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L1DcacheMemory_request_type_LD: 65.1697% - system.l1_cntrl6.L1DcacheMemory_request_type_ST: 34.8303% + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 65.2795% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 34.7205% - system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 77068 100% + system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76511 100% Cache Stats: system.l1_cntrl7.L1IcacheMemory system.l1_cntrl7.L1IcacheMemory_total_misses: 0 @@ -550,96 +550,95 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory Cache Stats: system.l1_cntrl7.L1DcacheMemory - system.l1_cntrl7.L1DcacheMemory_total_misses: 76153 - system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76153 + system.l1_cntrl7.L1DcacheMemory_total_misses: 76242 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76242 system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.9285% - system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.0715% + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.9852% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.0148% - system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 76153 100% + system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 76242 100% Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 611800 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 611800 + system.l2_cntrl0.L2cacheMemory_total_misses: 609026 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 609026 system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_request_type_GETS: 64.9608% - system.l2_cntrl0.L2cacheMemory_request_type_GETX: 35.0391% - system.l2_cntrl0.L2cacheMemory_request_type_UPGRADE: 0.000163452% + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 65.0161% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 34.9839% - system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 611800 100% + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 609026 100% --- L2Cache --- - Event Counts - L1_GET_INSTR [0 ] 0 -L1_GETS [399269 ] 399269 -L1_GETX [216713 ] 216713 +L1_GETS [397720 ] 397720 +L1_GETX [215399 ] 215399 L1_UPGRADE [0 ] 0 -L1_PUTX [22133 ] 22133 -L1_PUTX_old [305447 ] 305447 +L1_PUTX [21932 ] 21932 +L1_PUTX_old [304771 ] 304771 Fwd_L1_GETX [0 ] 0 Fwd_L1_GETS [0 ] 0 Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [8370 ] 8370 -L2_Replacement_clean [4599562 ] 4599562 -Mem_Data [606455 ] 606455 -Mem_Ack [606448 ] 606448 -WB_Data [206700 ] 206700 -WB_Data_clean [193181 ] 193181 +L2_Replacement [8529 ] 8529 +L2_Replacement_clean [4596903 ] 4596903 +Mem_Data [603683 ] 603683 +Mem_Ack [603678 ] 603678 +WB_Data [205245 ] 205245 +WB_Data_clean [193163 ] 193163 Ack [3670 ] 3670 -Ack_all [187586 ] 187586 -Unblock [1225 ] 1225 +Ack_all [186345 ] 186345 +Unblock [1166 ] 1166 Unblock_Cancel [0 ] 0 -Exclusive_Unblock [605697 ] 605697 +Exclusive_Unblock [602867 ] 602867 MEM_Inv [0 ] 0 - Transitions - NP L1_GET_INSTR [0 ] 0 -NP L1_GETS [393757 ] 393757 -NP L1_GETX [212704 ] 212704 +NP L1_GETS [392288 ] 392288 +NP L1_GETX [211401 ] 211401 NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [283735 ] 283735 +NP L1_PUTX_old [283319 ] 283319 SS L1_GET_INSTR [0 ] 0 -SS L1_GETS [6 ] 6 -SS L1_GETX [9 ] 9 +SS L1_GETS [4 ] 4 +SS L1_GETX [11 ] 11 SS L1_UPGRADE [0 ] 0 -SS L1_PUTX [508 ] 508 +SS L1_PUTX [454 ] 454 SS L1_PUTX_old [1 ] 1 -SS L2_Replacement [1138 ] 1138 -SS L2_Replacement_clean [2522 ] 2522 +SS L2_Replacement [1082 ] 1082 +SS L2_Replacement_clean [2577 ] 2577 SS MEM_Inv [0 ] 0 M L1_GET_INSTR [0 ] 0 -M L1_GETS [8 ] 8 -M L1_GETX [4 ] 4 +M L1_GETS [9 ] 9 +M L1_GETX [9 ] 9 M L1_PUTX [0 ] 0 M L1_PUTX_old [0 ] 0 -M L2_Replacement [7079 ] 7079 -M L2_Replacement_clean [13130 ] 13130 +M L2_Replacement [7238 ] 7238 +M L2_Replacement_clean [12856 ] 12856 M MEM_Inv [0 ] 0 MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [1225 ] 1225 -MT L1_GETX [1666 ] 1666 -MT L1_PUTX [20221 ] 20221 -MT L1_PUTX_old [740 ] 740 -MT L2_Replacement [6 ] 6 -MT L2_Replacement_clean [582578 ] 582578 +MT L1_GETS [1166 ] 1166 +MT L1_GETX [1660 ] 1660 +MT L1_PUTX [20112 ] 20112 +MT L1_PUTX_old [693 ] 693 +MT L2_Replacement [5 ] 5 +MT L2_Replacement_clean [579923 ] 579923 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [228 ] 228 -M_I L1_GETX [121 ] 121 +M_I L1_GETS [226 ] 226 +M_I L1_GETX [136 ] 136 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [14216 ] 14216 -M_I Mem_Ack [606448 ] 606448 +M_I L1_PUTX_old [13925 ] 13925 +M_I Mem_Ack [603678 ] 603678 M_I MEM_Inv [0 ] 0 MT_I L1_GET_INSTR [0 ] 0 @@ -648,92 +647,92 @@ MT_I L1_GETX [0 ] 0 MT_I L1_UPGRADE [0 ] 0 MT_I L1_PUTX [0 ] 0 MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [4 ] 4 +MT_I WB_Data [3 ] 3 MT_I WB_Data_clean [0 ] 0 MT_I Ack_all [2 ] 2 MT_I MEM_Inv [0 ] 0 MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [77 ] 77 -MCT_I L1_GETX [88 ] 88 +MCT_I L1_GETS [67 ] 67 +MCT_I L1_GETX [78 ] 78 MCT_I L1_UPGRADE [0 ] 0 MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [6206 ] 6206 -MCT_I WB_Data [205555 ] 205555 -MCT_I WB_Data_clean [193097 ] 193097 -MCT_I Ack_all [183924 ] 183924 +MCT_I L1_PUTX_old [6254 ] 6254 +MCT_I WB_Data [204158 ] 204158 +MCT_I WB_Data_clean [193081 ] 193081 +MCT_I Ack_all [182684 ] 182684 I_I L1_GET_INSTR [0 ] 0 I_I L1_GETS [0 ] 0 I_I L1_GETX [0 ] 0 I_I L1_UPGRADE [0 ] 0 I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [2527 ] 2527 -I_I Ack_all [2522 ] 2522 +I_I L1_PUTX_old [1 ] 1 +I_I Ack [2585 ] 2585 +I_I Ack_all [2577 ] 2577 S_I L1_GET_INSTR [0 ] 0 S_I L1_GETS [0 ] 0 S_I L1_GETX [0 ] 0 S_I L1_UPGRADE [0 ] 0 S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [1 ] 1 -S_I Ack [1143 ] 1143 -S_I Ack_all [1138 ] 1138 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [1085 ] 1085 +S_I Ack_all [1082 ] 1082 S_I MEM_Inv [0 ] 0 ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [2444 ] 2444 -ISS L1_GETX [1295 ] 1295 +ISS L1_GETS [2504 ] 2504 +ISS L1_GETX [1305 ] 1305 ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [243 ] 243 +ISS L1_PUTX_old [265 ] 265 ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [2151771 ] 2151771 -ISS Mem_Data [391309 ] 391309 +ISS L2_Replacement_clean [2162401 ] 2162401 +ISS Mem_Data [389780 ] 389780 ISS MEM_Inv [0 ] 0 IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [4 ] 4 -IS L1_GETX [1 ] 1 +IS L1_GETS [7 ] 7 +IS L1_GETX [3 ] 3 IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 +IS L1_PUTX_old [1 ] 1 IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [13480 ] 13480 -IS Mem_Data [2444 ] 2444 +IS L2_Replacement_clean [14490 ] 14490 +IS Mem_Data [2504 ] 2504 IS MEM_Inv [0 ] 0 IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [1368 ] 1368 -IM L1_GETX [720 ] 720 +IM L1_GETS [1297 ] 1297 +IM L1_GETX [708 ] 708 IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [302 ] 302 +IM L1_PUTX_old [310 ] 310 IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [1171194 ] 1171194 -IM Mem_Data [212702 ] 212702 +IM L2_Replacement_clean [1167648 ] 1167648 +IM Mem_Data [211399 ] 211399 IM MEM_Inv [0 ] 0 SS_MB L1_GET_INSTR [0 ] 0 SS_MB L1_GETS [0 ] 0 SS_MB L1_GETX [0 ] 0 SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [3 ] 3 +SS_MB L1_PUTX [0 ] 0 SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [12 ] 12 +SS_MB L2_Replacement [5 ] 5 +SS_MB L2_Replacement_clean [10 ] 10 SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [9 ] 9 +SS_MB Exclusive_Unblock [11 ] 11 SS_MB MEM_Inv [0 ] 0 MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [146 ] 146 -MT_MB L1_GETX [101 ] 101 +MT_MB L1_GETS [150 ] 150 +MT_MB L1_GETX [87 ] 87 MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [838 ] 838 +MT_MB L1_PUTX [839 ] 839 MT_MB L1_PUTX_old [1 ] 1 MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [661724 ] 661724 +MT_MB L2_Replacement_clean [653837 ] 653837 MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [605688 ] 605688 +MT_MB Exclusive_Unblock [602856 ] 602856 MT_MB MEM_Inv [0 ] 0 M_MB L1_GET_INSTR [0 ] 0 @@ -748,15 +747,15 @@ M_MB Exclusive_Unblock [0 ] 0 M_MB MEM_Inv [0 ] 0 MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [6 ] 6 -MT_IIB L1_GETX [4 ] 4 +MT_IIB L1_GETS [2 ] 2 +MT_IIB L1_GETX [1 ] 1 MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [563 ] 563 -MT_IIB L1_PUTX_old [2 ] 2 +MT_IIB L1_PUTX [524 ] 524 +MT_IIB L1_PUTX_old [1 ] 1 MT_IIB L2_Replacement [0 ] 0 MT_IIB L2_Replacement_clean [3123 ] 3123 -MT_IIB WB_Data [791 ] 791 -MT_IIB WB_Data_clean [46 ] 46 +MT_IIB WB_Data [725 ] 725 +MT_IIB WB_Data_clean [53 ] 53 MT_IIB Unblock [388 ] 388 MT_IIB MEM_Inv [0 ] 0 @@ -764,12 +763,12 @@ MT_IB L1_GET_INSTR [0 ] 0 MT_IB L1_GETS [0 ] 0 MT_IB L1_GETX [0 ] 0 MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX [1 ] 1 MT_IB L1_PUTX_old [0 ] 0 MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [28 ] 28 -MT_IB WB_Data [350 ] 350 -MT_IB WB_Data_clean [38 ] 38 +MT_IB L2_Replacement_clean [38 ] 38 +MT_IB WB_Data [359 ] 359 +MT_IB WB_Data_clean [29 ] 29 MT_IB Unblock_Cancel [0 ] 0 MT_IB MEM_Inv [0 ] 0 @@ -777,45 +776,45 @@ MT_SB L1_GET_INSTR [0 ] 0 MT_SB L1_GETS [0 ] 0 MT_SB L1_GETX [0 ] 0 MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX [2 ] 2 MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [147 ] 147 +MT_SB L2_Replacement [199 ] 199 MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [837 ] 837 +MT_SB Unblock [778 ] 778 MT_SB MEM_Inv [0 ] 0 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 820237 - memory_reads: 606457 - memory_writes: 213778 - memory_refreshes: 50537 - memory_total_request_delays: 5712055 - memory_delays_per_request: 6.96391 - memory_delays_in_input_queue: 173579 - memory_delays_behind_head_of_bank_queue: 420205 - memory_delays_stalled_at_head_of_bank_queue: 5118271 - memory_stalls_for_bank_busy: 997464 + memory_total_requests: 816172 + memory_reads: 603689 + memory_writes: 212481 + memory_refreshes: 50290 + memory_total_request_delays: 5661158 + memory_delays_per_request: 6.93623 + memory_delays_in_input_queue: 172035 + memory_delays_behind_head_of_bank_queue: 410755 + memory_delays_stalled_at_head_of_bank_queue: 5078368 + memory_stalls_for_bank_busy: 989223 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 191989 - memory_stalls_for_arbitration: 983802 - memory_stalls_for_bus: 1595683 + memory_stalls_for_anti_starvation: 191950 + memory_stalls_for_arbitration: 974844 + memory_stalls_for_bus: 1583864 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 933914 - memory_stalls_for_read_read_turnaround: 415419 - accesses_per_bank: 25814 25380 25554 25794 25830 25689 25895 25624 25814 25591 25638 25766 25376 25470 25597 25469 25579 25623 25682 25615 25713 25607 25737 25536 25557 25222 25632 25231 25594 25826 25962 25820 + memory_stalls_for_read_write_turnaround: 925893 + memory_stalls_for_read_read_turnaround: 412594 + accesses_per_bank: 25637 25274 25579 25442 25390 25166 25135 25588 25465 25549 25668 25806 25364 25704 25508 25604 25528 25494 25813 25612 25354 25558 25349 25670 25347 25491 25552 25450 25524 25728 25358 25465 --- Directory --- - Event Counts - -Fetch [606459 ] 606459 -Data [213778 ] 213778 -Memory_Data [606456 ] 606456 -Memory_Ack [213775 ] 213775 +Fetch [603689 ] 603689 +Data [212483 ] 212483 +Memory_Data [603684 ] 603684 +Memory_Ack [212481 ] 212481 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -CleanReplacement [392673 ] 392673 +CleanReplacement [391197 ] 391197 - Transitions - -I Fetch [606459 ] 606459 +I Fetch [603689 ] 603689 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 @@ -831,20 +830,20 @@ ID_W Memory_Ack [0 ] 0 ID_W DMA_READ [0 ] 0 ID_W DMA_WRITE [0 ] 0 -M Data [213778 ] 213778 +M Data [212483 ] 212483 M DMA_READ [0 ] 0 M DMA_WRITE [0 ] 0 -M CleanReplacement [392673 ] 392673 +M CleanReplacement [391197 ] 391197 IM Fetch [0 ] 0 IM Data [0 ] 0 -IM Memory_Data [606456 ] 606456 +IM Memory_Data [603684 ] 603684 IM DMA_READ [0 ] 0 IM DMA_WRITE [0 ] 0 MI Fetch [0 ] 0 MI Data [0 ] 0 -MI Memory_Ack [213775 ] 213775 +MI Memory_Ack [212481 ] 212481 MI DMA_READ [0 ] 0 MI DMA_WRITE [0 ] 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr index c95b867cb..f40af13bc 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr @@ -1,74 +1,82 @@ -system.cpu6: completed 10000 read, 5365 write accesses @719672 -system.cpu4: completed 10000 read, 5437 write accesses @721238 -system.cpu2: completed 10000 read, 5421 write accesses @727405 -system.cpu5: completed 10000 read, 5337 write accesses @728640 -system.cpu1: completed 10000 read, 5306 write accesses @739695 -system.cpu0: completed 10000 read, 5242 write accesses @743577 -system.cpu3: completed 10000 read, 5450 write accesses @745629 -system.cpu7: completed 10000 read, 5714 write accesses @748519 -system.cpu6: completed 20000 read, 10620 write accesses @1427013 -system.cpu2: completed 20000 read, 10776 write accesses @1449780 -system.cpu4: completed 20000 read, 10676 write accesses @1454294 -system.cpu5: completed 20000 read, 10664 write accesses @1455327 -system.cpu1: completed 20000 read, 10677 write accesses @1463325 -system.cpu0: completed 20000 read, 10572 write accesses @1473996 -system.cpu7: completed 20000 read, 11108 write accesses @1487052 -system.cpu3: completed 20000 read, 10777 write accesses @1490754 -system.cpu5: completed 30000 read, 16039 write accesses @2158969 -system.cpu6: completed 30000 read, 16167 write accesses @2175252 -system.cpu2: completed 30000 read, 16167 write accesses @2180312 -system.cpu4: completed 30000 read, 16215 write accesses @2190381 -system.cpu0: completed 30000 read, 15974 write accesses @2206091 -system.cpu1: completed 30000 read, 16196 write accesses @2209395 -system.cpu7: completed 30000 read, 16345 write accesses @2219972 -system.cpu3: completed 30000 read, 16078 write accesses @2220143 -system.cpu5: completed 40000 read, 21392 write accesses @2899061 -system.cpu2: completed 40000 read, 21496 write accesses @2899829 -system.cpu6: completed 40000 read, 21553 write accesses @2911614 -system.cpu4: completed 40000 read, 21511 write accesses @2932562 -system.cpu1: completed 40000 read, 21671 write accesses @2938496 -system.cpu0: completed 40000 read, 21461 write accesses @2955945 -system.cpu3: completed 40000 read, 21481 write accesses @2956326 -system.cpu7: completed 40000 read, 21787 write accesses @2958263 -system.cpu2: completed 50000 read, 26881 write accesses @3632427 -system.cpu5: completed 50000 read, 26798 write accesses @3647589 -system.cpu6: completed 50000 read, 27058 write accesses @3655170 -system.cpu4: completed 50000 read, 26812 write accesses @3655319 -system.cpu1: completed 50000 read, 27071 write accesses @3688858 -system.cpu3: completed 50000 read, 26791 write accesses @3690833 -system.cpu0: completed 50000 read, 27081 write accesses @3690860 -system.cpu7: completed 50000 read, 27296 write accesses @3707477 -system.cpu2: completed 60000 read, 32129 write accesses @4356825 -system.cpu5: completed 60000 read, 32023 write accesses @4371741 -system.cpu6: completed 60000 read, 32443 write accesses @4376668 -system.cpu4: completed 60000 read, 32295 write accesses @4386108 -system.cpu3: completed 60000 read, 32175 write accesses @4408668 -system.cpu0: completed 60000 read, 32420 write accesses @4415861 -system.cpu1: completed 60000 read, 32486 write accesses @4431347 -system.cpu7: completed 60000 read, 32741 write accesses @4445010 -system.cpu2: completed 70000 read, 37617 write accesses @5091246 -system.cpu5: completed 70000 read, 37377 write accesses @5103537 -system.cpu4: completed 70000 read, 37661 write accesses @5110093 -system.cpu6: completed 70000 read, 37706 write accesses @5114409 -system.cpu3: completed 70000 read, 37523 write accesses @5122627 -system.cpu0: completed 70000 read, 37790 write accesses @5150115 -system.cpu7: completed 70000 read, 38053 write accesses @5173503 -system.cpu1: completed 70000 read, 37871 write accesses @5177041 -system.cpu2: completed 80000 read, 42964 write accesses @5827270 -system.cpu5: completed 80000 read, 42671 write accesses @5843646 -system.cpu4: completed 80000 read, 42873 write accesses @5844336 -system.cpu3: completed 80000 read, 42910 write accesses @5844576 -system.cpu6: completed 80000 read, 43090 write accesses @5845119 -system.cpu0: completed 80000 read, 43048 write accesses @5875184 -system.cpu1: completed 80000 read, 43196 write accesses @5885103 -system.cpu7: completed 80000 read, 43360 write accesses @5912912 -system.cpu2: completed 90000 read, 48230 write accesses @6556181 -system.cpu6: completed 90000 read, 48543 write accesses @6557564 -system.cpu4: completed 90000 read, 48345 write accesses @6563045 -system.cpu3: completed 90000 read, 48233 write accesses @6584230 -system.cpu5: completed 90000 read, 48065 write accesses @6589320 -system.cpu0: completed 90000 read, 48648 write accesses @6625439 -system.cpu1: completed 90000 read, 48656 write accesses @6633753 -system.cpu7: completed 90000 read, 48776 write accesses @6656500 -system.cpu2: completed 100000 read, 53615 write accesses @7277301 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +system.cpu3: completed 10000 read, 5404 write accesses @717450 +system.cpu1: completed 10000 read, 5196 write accesses @724437 +system.cpu2: completed 10000 read, 5343 write accesses @725385 +system.cpu6: completed 10000 read, 5334 write accesses @727920 +system.cpu7: completed 10000 read, 5409 write accesses @729342 +system.cpu4: completed 10000 read, 5518 write accesses @734970 +system.cpu5: completed 10000 read, 5427 write accesses @742533 +system.cpu0: completed 10000 read, 5369 write accesses @745215 +system.cpu3: completed 20000 read, 10663 write accesses @1450297 +system.cpu1: completed 20000 read, 10544 write accesses @1453395 +system.cpu2: completed 20000 read, 10794 write accesses @1458916 +system.cpu4: completed 20000 read, 10867 write accesses @1467543 +system.cpu7: completed 20000 read, 11024 write accesses @1468498 +system.cpu5: completed 20000 read, 10707 write accesses @1475684 +system.cpu6: completed 20000 read, 10882 write accesses @1478874 +system.cpu0: completed 20000 read, 10682 write accesses @1482396 +system.cpu2: completed 30000 read, 16135 write accesses @2180653 +system.cpu6: completed 30000 read, 16248 write accesses @2190702 +system.cpu0: completed 30000 read, 15981 write accesses @2193064 +system.cpu7: completed 30000 read, 16551 write accesses @2194713 +system.cpu1: completed 30000 read, 16114 write accesses @2197452 +system.cpu4: completed 30000 read, 16285 write accesses @2201477 +system.cpu3: completed 30000 read, 16078 write accesses @2211153 +system.cpu5: completed 30000 read, 15971 write accesses @2223483 +system.cpu6: completed 40000 read, 21540 write accesses @2894242 +system.cpu2: completed 40000 read, 21379 write accesses @2909918 +system.cpu0: completed 40000 read, 21281 write accesses @2925069 +system.cpu7: completed 40000 read, 21971 write accesses @2926047 +system.cpu1: completed 40000 read, 21533 write accesses @2926905 +system.cpu4: completed 40000 read, 21566 write accesses @2928243 +system.cpu3: completed 40000 read, 21457 write accesses @2944482 +system.cpu5: completed 40000 read, 21433 write accesses @2971421 +system.cpu6: completed 50000 read, 26804 write accesses @3631185 +system.cpu2: completed 50000 read, 26805 write accesses @3647917 +system.cpu1: completed 50000 read, 26966 write accesses @3648934 +system.cpu0: completed 50000 read, 26609 write accesses @3651975 +system.cpu4: completed 50000 read, 26920 write accesses @3663191 +system.cpu7: completed 50000 read, 27389 write accesses @3665118 +system.cpu3: completed 50000 read, 26923 write accesses @3682505 +system.cpu5: completed 50000 read, 26907 write accesses @3699503 +system.cpu6: completed 60000 read, 31950 write accesses @4347584 +system.cpu0: completed 60000 read, 31929 write accesses @4376408 +system.cpu4: completed 60000 read, 32384 write accesses @4384804 +system.cpu1: completed 60000 read, 32291 write accesses @4390260 +system.cpu2: completed 60000 read, 32255 write accesses @4393199 +system.cpu7: completed 60000 read, 32753 write accesses @4398494 +system.cpu3: completed 60000 read, 32296 write accesses @4430205 +system.cpu5: completed 60000 read, 32304 write accesses @4433476 +system.cpu6: completed 70000 read, 37197 write accesses @5062593 +system.cpu0: completed 70000 read, 37408 write accesses @5107223 +system.cpu4: completed 70000 read, 37809 write accesses @5113784 +system.cpu7: completed 70000 read, 38017 write accesses @5123354 +system.cpu1: completed 70000 read, 37773 write accesses @5127282 +system.cpu2: completed 70000 read, 37716 write accesses @5127504 +system.cpu5: completed 70000 read, 37617 write accesses @5160933 +system.cpu3: completed 70000 read, 37758 write accesses @5167879 +system.cpu6: completed 80000 read, 42553 write accesses @5789514 +system.cpu7: completed 80000 read, 43160 write accesses @5844814 +system.cpu4: completed 80000 read, 43182 write accesses @5848125 +system.cpu0: completed 80000 read, 43046 write accesses @5851383 +system.cpu2: completed 80000 read, 42995 write accesses @5852199 +system.cpu1: completed 80000 read, 43208 write accesses @5860776 +system.cpu5: completed 80000 read, 43003 write accesses @5898048 +system.cpu3: completed 80000 read, 43420 write accesses @5900131 +system.cpu6: completed 90000 read, 47840 write accesses @6504240 +system.cpu7: completed 90000 read, 48495 write accesses @6570600 +system.cpu2: completed 90000 read, 48384 write accesses @6574765 +system.cpu0: completed 90000 read, 48489 write accesses @6585072 +system.cpu4: completed 90000 read, 48555 write accesses @6585987 +system.cpu1: completed 90000 read, 48451 write accesses @6586255 +system.cpu5: completed 90000 read, 48304 write accesses @6624686 +system.cpu3: completed 90000 read, 48748 write accesses @6638587 +system.cpu6: completed 100000 read, 53283 write accesses @7241726 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index c1652737d..ab2c911dd 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007277 # Number of seconds simulated -sim_ticks 7277301 # Number of ticks simulated -final_tick 7277301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007242 # Number of seconds simulated +sim_ticks 7241726 # Number of ticks simulated +final_tick 7241726 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 75137 # Simulator tick rate (ticks/s) -host_mem_usage 410244 # Number of bytes of host memory used -host_seconds 96.85 # Real time elapsed on the host +host_tick_rate 40867 # Simulator tick rate (ticks/s) +host_mem_usage 418748 # Number of bytes of host memory used +host_seconds 177.20 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 98746 # number of read accesses completed -system.cpu0.num_writes 53285 # number of write accesses completed +system.cpu0.num_reads 99032 # number of read accesses completed +system.cpu0.num_writes 53300 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98932 # number of read accesses completed -system.cpu1.num_writes 53387 # number of write accesses completed +system.cpu1.num_reads 99071 # number of read accesses completed +system.cpu1.num_writes 53375 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100001 # number of read accesses completed -system.cpu2.num_writes 53615 # number of write accesses completed +system.cpu2.num_reads 99029 # number of read accesses completed +system.cpu2.num_writes 53317 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99438 # number of read accesses completed -system.cpu3.num_writes 53391 # number of write accesses completed +system.cpu3.num_reads 98175 # number of read accesses completed +system.cpu3.num_writes 53115 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99851 # number of read accesses completed -system.cpu4.num_writes 53668 # number of write accesses completed +system.cpu4.num_reads 98923 # number of read accesses completed +system.cpu4.num_writes 53385 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99263 # number of read accesses completed -system.cpu5.num_writes 53077 # number of write accesses completed +system.cpu5.num_reads 98363 # number of read accesses completed +system.cpu5.num_writes 52848 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99775 # number of read accesses completed -system.cpu6.num_writes 53756 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 53283 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98608 # number of read accesses completed -system.cpu7.num_writes 53419 # number of write accesses completed +system.cpu7.num_reads 99065 # number of read accesses completed +system.cpu7.num_writes 53415 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index 16b970150..fe78e1f63 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -1,26 +1,26 @@ -Real time: Sep/01/2012 14:14:37 +Real time: Oct/08/2012 22:36:12 Profiler Stats -------------- -Elapsed_time_in_seconds: 176 -Elapsed_time_in_minutes: 2.93333 -Elapsed_time_in_hours: 0.0488889 -Elapsed_time_in_days: 0.00203704 +Elapsed_time_in_seconds: 293 +Elapsed_time_in_minutes: 4.88333 +Elapsed_time_in_hours: 0.0813889 +Elapsed_time_in_days: 0.0033912 -Virtual_time_in_seconds: 175.42 -Virtual_time_in_minutes: 2.92367 -Virtual_time_in_hours: 0.0487278 -Virtual_time_in_days: 0.00203032 +Virtual_time_in_seconds: 186.53 +Virtual_time_in_minutes: 3.10883 +Virtual_time_in_hours: 0.0518139 +Virtual_time_in_days: 0.00215891 -Ruby_current_time: 7493512 +Ruby_current_time: 7447945 Ruby_start_time: 0 -Ruby_cycles: 7493512 +Ruby_cycles: 7447945 -mbytes_resident: 65.4062 -mbytes_total: 400.824 -resident_ratio: 0.163218 +mbytes_resident: 72.8555 +mbytes_total: 409.133 +resident_ratio: 0.178082 -ruby_cycles_executed: [ 7493513 7493513 7493513 7493513 7493513 7493513 7493513 7493513 ] +ruby_cycles_executed: [ 7447946 7447946 7447946 7447946 7447946 7447946 7447946 7447946 ] Busy Controller Counts: L2Cache-0:0 @@ -31,14 +31,14 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 620657 average: 15.9984 | standard deviation: 0.126475 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 17 620528 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 617028 average: 15.9984 | standard deviation: 0.126834 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 15 616901 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 18979 count: 620529 average: 1545.38 | standard deviation: 1553.79 | 1251 7856 100163 76282 14460 62295 38374 10797 39586 23348 9455 28279 15726 8383 20606 10995 7552 15239 8212 6568 11607 6167 5765 8648 4770 4882 6826 3823 4218 5260 3048 3485 3996 2475 2918 3204 1942 2389 2426 1748 2004 1941 1392 1599 1513 1138 1276 1120 931 1025 921 758 821 720 590 621 532 537 534 498 383 414 315 316 311 256 244 240 231 195 199 143 149 158 123 137 90 116 96 74 70 84 58 61 55 53 40 35 36 19 29 22 25 34 18 18 22 16 17 14 9 16 12 5 4 8 8 8 9 6 3 2 4 3 2 3 2 2 1 1 0 2 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 128 max: 18979 count: 403016 average: 1547.1 | standard deviation: 1558.02 | 842 5129 65466 49287 9494 40223 24863 7023 25698 15109 6159 18401 10182 5438 13193 7084 4961 9888 5285 4336 7559 4039 3694 5619 3100 3145 4472 2481 2744 3452 1980 2226 2587 1585 1869 2144 1277 1568 1572 1168 1293 1283 918 1042 979 763 821 714 598 677 599 503 543 473 389 397 360 355 363 312 249 267 213 203 208 177 153 156 145 129 128 88 94 103 82 84 63 80 62 44 47 64 36 43 37 29 25 23 23 11 17 14 20 18 14 14 15 11 12 8 5 11 8 2 4 7 6 5 7 4 3 2 2 2 1 2 1 1 1 1 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 128 max: 16824 count: 217513 average: 1542.19 | standard deviation: 1545.91 | 409 2727 34697 26995 4966 22072 13511 3774 13888 8239 3296 9878 5544 2945 7413 3911 2591 5351 2927 2232 4048 2128 2071 3029 1670 1737 2354 1342 1474 1808 1068 1259 1409 890 1049 1060 665 821 854 580 711 658 474 557 534 375 455 406 333 348 322 255 278 247 201 224 172 182 171 186 134 147 102 113 103 79 91 84 86 66 71 55 55 55 41 53 27 36 34 30 23 20 22 18 18 24 15 12 13 8 12 8 5 16 4 4 7 5 5 6 4 5 4 3 0 1 2 3 2 2 0 0 2 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 128 max: 18979 count: 620529 average: 1545.38 | standard deviation: 1553.79 | 1251 7856 100163 76282 14460 62295 38374 10797 39586 23348 9455 28279 15726 8383 20606 10995 7552 15239 8212 6568 11607 6167 5765 8648 4770 4882 6826 3823 4218 5260 3048 3485 3996 2475 2918 3204 1942 2389 2426 1748 2004 1941 1392 1599 1513 1138 1276 1120 931 1025 921 758 821 720 590 621 532 537 534 498 383 414 315 316 311 256 244 240 231 195 199 143 149 158 123 137 90 116 96 74 70 84 58 61 55 53 40 35 36 19 29 22 25 34 18 18 22 16 17 14 9 16 12 5 4 8 8 8 9 6 3 2 4 3 2 3 2 2 1 1 0 2 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 20118 count: 616900 average: 1544.99 | standard deviation: 1541.45 | 1248 7609 97380 75997 14208 61881 38781 10427 39944 23959 9302 28152 15807 8318 20610 11096 7334 15589 8401 6573 11580 6083 5763 8989 4807 4833 6867 3778 4185 5241 3129 3456 3887 2507 2882 3138 1907 2335 2433 1658 1945 1979 1376 1591 1491 1070 1235 1162 894 971 927 753 774 671 591 655 507 490 505 415 381 397 339 303 323 258 221 210 194 187 203 158 136 132 117 100 118 101 81 75 77 44 60 57 39 49 37 39 43 34 18 25 33 25 22 20 18 11 12 11 9 3 8 4 6 5 5 6 2 9 3 6 5 3 4 5 2 3 3 4 1 2 1 2 0 1 2 2 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 19819 count: 400523 average: 1543.88 | standard deviation: 1540.69 | 850 4969 63653 48951 9241 40362 24909 6768 26034 15479 6058 18203 10301 5469 13387 7195 4808 10211 5446 4306 7476 3863 3692 5820 3126 3128 4443 2376 2746 3403 2031 2270 2482 1580 1868 2005 1245 1483 1640 1043 1274 1314 917 1038 970 707 808 760 575 655 605 488 503 418 387 426 344 307 313 279 245 261 223 198 197 176 136 132 126 123 144 110 86 88 78 57 78 58 46 49 50 29 33 37 23 27 22 27 26 24 11 18 23 18 14 15 11 8 8 7 6 3 3 3 5 4 3 4 0 4 1 5 4 1 3 3 1 2 2 3 0 2 0 1 0 1 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 20118 count: 216377 average: 1547.05 | standard deviation: 1542.85 | 398 2640 33727 27046 4967 21519 13872 3659 13910 8480 3244 9949 5506 2849 7223 3901 2526 5378 2955 2267 4104 2220 2071 3169 1681 1705 2424 1402 1439 1838 1098 1186 1405 927 1014 1133 662 852 793 615 671 665 459 553 521 363 427 402 319 316 322 265 271 253 204 229 163 183 192 136 136 136 116 105 126 82 85 78 68 64 59 48 50 44 39 43 40 43 35 26 27 15 27 20 16 22 15 12 17 10 7 7 10 7 8 5 7 3 4 4 3 0 5 1 1 1 2 2 2 5 2 1 1 2 1 2 1 1 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 128 max: 20118 count: 616900 average: 1544.99 | standard deviation: 1541.45 | 1248 7609 97380 75997 14208 61881 38781 10427 39944 23959 9302 28152 15807 8318 20610 11096 7334 15589 8401 6573 11580 6083 5763 8989 4807 4833 6867 3778 4185 5241 3129 3456 3887 2507 2882 3138 1907 2335 2433 1658 1945 1979 1376 1591 1491 1070 1235 1162 894 971 927 753 774 671 591 655 507 490 505 415 381 397 339 303 323 258 221 210 194 187 203 158 136 132 117 100 118 101 81 75 77 44 60 57 39 49 37 39 43 34 18 25 33 25 22 20 18 11 12 11 9 3 8 4 6 5 5 6 2 9 3 6 5 3 4 5 2 3 3 4 1 2 1 2 0 1 2 2 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -49,8 +49,8 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 128 max: 18979 count: 403016 average: 1547.1 | standard deviation: 1558.02 | 842 5129 65466 49287 9494 40223 24863 7023 25698 15109 6159 18401 10182 5438 13193 7084 4961 9888 5285 4336 7559 4039 3694 5619 3100 3145 4472 2481 2744 3452 1980 2226 2587 1585 1869 2144 1277 1568 1572 1168 1293 1283 918 1042 979 763 821 714 598 677 599 503 543 473 389 397 360 355 363 312 249 267 213 203 208 177 153 156 145 129 128 88 94 103 82 84 63 80 62 44 47 64 36 43 37 29 25 23 23 11 17 14 20 18 14 14 15 11 12 8 5 11 8 2 4 7 6 5 7 4 3 2 2 2 1 2 1 1 1 1 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 128 max: 16824 count: 217513 average: 1542.19 | standard deviation: 1545.91 | 409 2727 34697 26995 4966 22072 13511 3774 13888 8239 3296 9878 5544 2945 7413 3911 2591 5351 2927 2232 4048 2128 2071 3029 1670 1737 2354 1342 1474 1808 1068 1259 1409 890 1049 1060 665 821 854 580 711 658 474 557 534 375 455 406 333 348 322 255 278 247 201 224 172 182 171 186 134 147 102 113 103 79 91 84 86 66 71 55 55 55 41 53 27 36 34 30 23 20 22 18 18 24 15 12 13 8 12 8 5 16 4 4 7 5 5 6 4 5 4 3 0 1 2 3 2 2 0 0 2 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 128 max: 19819 count: 400523 average: 1543.88 | standard deviation: 1540.69 | 850 4969 63653 48951 9241 40362 24909 6768 26034 15479 6058 18203 10301 5469 13387 7195 4808 10211 5446 4306 7476 3863 3692 5820 3126 3128 4443 2376 2746 3403 2031 2270 2482 1580 1868 2005 1245 1483 1640 1043 1274 1314 917 1038 970 707 808 760 575 655 605 488 503 418 387 426 344 307 313 279 245 261 223 198 197 176 136 132 126 123 144 110 86 88 78 57 78 58 46 49 50 29 33 37 23 27 22 27 26 24 11 18 23 18 14 15 11 8 8 7 6 3 3 3 5 4 3 4 0 4 1 5 4 1 3 3 1 2 2 3 0 2 0 1 0 1 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 128 max: 20118 count: 216377 average: 1547.05 | standard deviation: 1542.85 | 398 2640 33727 27046 4967 21519 13872 3659 13910 8480 3244 9949 5506 2849 7223 3901 2526 5378 2955 2267 4104 2220 2071 3169 1681 1705 2424 1402 1439 1838 1098 1186 1405 927 1014 1133 662 852 793 615 671 665 459 553 521 363 427 402 319 316 322 265 271 253 204 229 163 183 192 136 136 136 116 105 126 82 85 78 68 64 59 48 50 44 39 43 40 43 35 26 27 15 27 20 16 22 15 12 17 10 7 7 10 7 8 5 7 3 4 4 3 0 5 1 1 1 2 2 2 5 2 1 1 2 1 2 1 1 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -80,302 +80,299 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 175 +user_time: 186 system_time: 0 -page_reclaims: 9127 +page_reclaims: 9563 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 224 +block_outputs: 288 Network Stats ------------- -total_msg_count_Request_Control: 3679260 29434080 -total_msg_count_Response_Data: 3636333 261815976 -total_msg_count_ResponseL2hit_Data: 17784 1280448 -total_msg_count_ResponseLocal_Data: 25080 1805760 -total_msg_count_Response_Control: 8799 70392 -total_msg_count_Writeback_Data: 2483613 178820136 -total_msg_count_Writeback_Control: 8524208 68193664 -total_msg_count_Forwarded_Control: 25080 200640 -total_msg_count_Invalidate_Control: 60 480 -total_msg_count_Unblock_Control: 3701966 29615728 -total_msgs: 22102183 total_bytes: 571237304 +total_msg_count_Request_Control: 3657393 29259144 +total_msg_count_Response_Data: 3614358 260233776 +total_msg_count_ResponseL2hit_Data: 17664 1271808 +total_msg_count_ResponseLocal_Data: 25344 1824768 +total_msg_count_Response_Control: 8967 71736 +total_msg_count_Writeback_Data: 2468913 177761736 +total_msg_count_Writeback_Control: 8473280 67786240 +total_msg_count_Forwarded_Control: 25344 202752 +total_msg_count_Invalidate_Control: 48 384 +total_msg_count_Unblock_Control: 3680434 29443472 +total_msgs: 21971745 total_bytes: 567855816 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 79.156 - links_utilized_percent_switch_0_link_0: 89.6643 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 68.6477 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 620353 4962824 [ 620353 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 606055 43635960 [ 0 0 606055 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Data: 612164 44075808 [ 0 0 612164 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 1225742 9805936 [ 620153 605589 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Unblock_Control: 627946 5023568 [ 0 0 627946 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 606065 4848520 [ 0 606065 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 606054 43635888 [ 0 0 606054 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 5928 426816 [ 0 0 5928 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 2913 23304 [ 0 0 2913 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 215707 15530904 [ 0 0 215707 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 1615650 12925200 [ 620153 605615 389882 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Forwarded_Control: 8360 66880 [ 8360 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Invalidate_Control: 20 160 [ 20 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 606041 4848328 [ 0 0 606041 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 79.1647 + links_utilized_percent_switch_0_link_0: 89.6694 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 68.6601 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 616731 4933848 [ 616731 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 602393 43372296 [ 0 0 602393 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 608430 43806960 [ 0 0 608430 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1218487 9747896 [ 616538 601949 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Unblock_Control: 624426 4995408 [ 0 0 624426 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 602395 4819160 [ 0 602395 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 602392 43372224 [ 0 0 602392 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 5888 423936 [ 0 0 5888 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 2973 23784 [ 0 0 2973 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 214541 15446952 [ 0 0 214541 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 1605925 12847400 [ 616538 601979 387408 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Forwarded_Control: 8448 67584 [ 8448 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Invalidate_Control: 16 128 [ 16 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 602384 4819072 [ 0 0 602384 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 5.68681 - links_utilized_percent_switch_1_link_0: 5.17063 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 6.203 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 75562 5440464 [ 0 0 75562 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 740 53280 [ 0 0 740 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 1047 75384 [ 0 0 1047 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 368 2944 [ 0 0 368 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 77330 618640 [ 77330 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 1082 8656 [ 1082 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 77351 618808 [ 77351 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 1082 77904 [ 0 0 1082 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 76324 5495328 [ 0 0 76324 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 77331 618648 [ 77331 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 78307 626456 [ 0 0 78307 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 5.69472 + links_utilized_percent_switch_1_link_0: 5.17935 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 6.2101 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 75216 5415552 [ 0 0 75216 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 711 51192 [ 0 0 711 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 1083 77976 [ 0 0 1083 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 390 3120 [ 0 0 390 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 76993 615944 [ 76993 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Forwarded_Control: 1033 8264 [ 1033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Invalidate_Control: 4 32 [ 4 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 77012 616096 [ 77012 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 1033 74376 [ 0 0 1033 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 4 32 [ 0 0 4 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 75974 5470128 [ 0 0 75974 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 76995 615960 [ 76995 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 77975 623800 [ 0 0 77975 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 5.69622 - links_utilized_percent_switch_2_link_0: 5.18021 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 6.21223 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 75625 5445000 [ 0 0 75625 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 746 53712 [ 0 0 746 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 1117 80424 [ 0 0 1117 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 424 3392 [ 0 0 424 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 77470 619760 [ 77470 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 1068 8544 [ 1068 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Invalidate_Control: 5 40 [ 5 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 77491 619928 [ 77491 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 1068 76896 [ 0 0 1068 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 5 40 [ 0 0 5 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 76444 5503968 [ 0 0 76444 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 77471 619768 [ 77471 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 78453 627624 [ 0 0 78453 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 5.7131 + links_utilized_percent_switch_2_link_0: 5.19535 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 6.23085 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 75484 5434848 [ 0 0 75484 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 725 52200 [ 0 0 725 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 1041 74952 [ 0 0 1041 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 365 2920 [ 0 0 365 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 77218 617744 [ 77218 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Forwarded_Control: 1065 8520 [ 1065 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 77252 618016 [ 77252 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 1065 76680 [ 0 0 1065 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1 8 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 76208 5486976 [ 0 0 76208 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 77219 617752 [ 77219 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 78212 625696 [ 0 0 78212 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 5.72264 - links_utilized_percent_switch_3_link_0: 5.20269 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 6.24259 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 76082 5477904 [ 0 0 76082 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 739 53208 [ 0 0 739 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 1011 72792 [ 0 0 1011 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 349 2792 [ 0 0 349 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 77823 622584 [ 77823 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 1065 8520 [ 1065 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 5.70789 + links_utilized_percent_switch_3_link_0: 5.19012 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 6.22566 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 75407 5429304 [ 0 0 75407 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 713 51336 [ 0 0 713 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 1049 75528 [ 0 0 1049 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 370 2960 [ 0 0 370 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 77154 617232 [ 77154 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Forwarded_Control: 1067 8536 [ 1067 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 77834 622672 [ 77834 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 1065 76680 [ 0 0 1065 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 77172 617376 [ 77172 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 1067 76824 [ 0 0 1067 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Response_Control: 3 24 [ 0 0 3 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 76841 5532552 [ 0 0 76841 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 77825 622600 [ 77825 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 78762 630096 [ 0 0 78762 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 76145 5482440 [ 0 0 76145 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 77157 617256 [ 77157 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 78128 625024 [ 0 0 78128 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 5.68722 - links_utilized_percent_switch_4_link_0: 5.17342 bw: 16000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 6.20102 bw: 16000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Response_Data: 75598 5443056 [ 0 0 75598 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 752 54144 [ 0 0 752 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 1051 75672 [ 0 0 1051 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 365 2920 [ 0 0 365 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 77372 618976 [ 77372 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 993 7944 [ 993 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 77403 619224 [ 77403 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 993 71496 [ 0 0 993 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 3 24 [ 0 0 3 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Data: 76363 5498136 [ 0 0 76363 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Control: 77373 618984 [ 77373 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 78365 626920 [ 0 0 78365 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 5.69854 + links_utilized_percent_switch_4_link_0: 5.18272 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 6.21437 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Response_Data: 75239 5417208 [ 0 0 75239 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 723 52056 [ 0 0 723 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 1099 79128 [ 0 0 1099 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 398 3184 [ 0 0 398 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 77028 616224 [ 77028 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Forwarded_Control: 1033 8264 [ 1033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Invalidate_Control: 4 32 [ 4 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 77065 616520 [ 77065 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 1033 74376 [ 0 0 1033 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 4 32 [ 0 0 4 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 76030 5474160 [ 0 0 76030 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 77032 616256 [ 77032 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 78017 624136 [ 0 0 78017 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 5.70748 - links_utilized_percent_switch_5_link_0: 5.18942 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 6.22553 bw: 16000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Response_Data: 75875 5463000 [ 0 0 75875 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 732 52704 [ 0 0 732 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 1026 73872 [ 0 0 1026 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 360 2880 [ 0 0 360 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 77599 620792 [ 77599 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 1085 8680 [ 1085 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 77636 621088 [ 77636 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 1085 78120 [ 0 0 1085 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Data: 76603 5515416 [ 0 0 76603 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Control: 77599 620792 [ 77599 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 78593 628744 [ 0 0 78593 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 5.69722 + links_utilized_percent_switch_5_link_0: 5.18236 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 6.21208 bw: 16000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Response_Data: 75271 5419512 [ 0 0 75271 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 752 54144 [ 0 0 752 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 1041 74952 [ 0 0 1041 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 369 2952 [ 0 0 369 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 77044 616352 [ 77044 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Forwarded_Control: 970 7760 [ 970 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 77066 616528 [ 77066 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 970 69840 [ 0 0 970 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 76055 5475960 [ 0 0 76055 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 77046 616368 [ 77046 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 78008 624064 [ 0 0 78008 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 5.70137 - links_utilized_percent_switch_6_link_0: 5.18499 bw: 16000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 6.21775 bw: 16000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Response_Data: 75864 5462208 [ 0 0 75864 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 725 52200 [ 0 0 725 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 986 70992 [ 0 0 986 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 324 2592 [ 0 0 324 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 77550 620400 [ 77550 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 1024 8192 [ 1024 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 77576 620608 [ 77576 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 1024 73728 [ 0 0 1024 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 3 24 [ 0 0 3 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Data: 76554 5511888 [ 0 0 76554 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Control: 77550 620400 [ 77550 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 78524 628192 [ 0 0 78524 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 5.6935 + links_utilized_percent_switch_6_link_0: 5.17792 bw: 16000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 6.20908 bw: 16000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Response_Data: 75143 5410296 [ 0 0 75143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 757 54504 [ 0 0 757 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 1087 78264 [ 0 0 1087 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 374 2992 [ 0 0 374 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 76964 615712 [ 76964 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Forwarded_Control: 1075 8600 [ 1075 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 76988 615904 [ 76988 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 1075 77400 [ 0 0 1075 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 1 8 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 75922 5466384 [ 0 0 75922 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 76964 615712 [ 76964 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 77971 623768 [ 0 0 77971 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 5.70637 - links_utilized_percent_switch_7_link_0: 5.18977 bw: 16000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 6.22296 bw: 16000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Response_Data: 75843 5460696 [ 0 0 75843 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 744 53568 [ 0 0 744 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 1055 75960 [ 0 0 1055 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 375 3000 [ 0 0 375 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 77618 620944 [ 77618 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 1020 8160 [ 1020 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 77644 621152 [ 77644 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 1020 73440 [ 0 0 1020 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 1 8 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Data: 76622 5516784 [ 0 0 76622 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Control: 77619 620952 [ 77619 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 78595 628760 [ 0 0 78595 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 5.70265 + links_utilized_percent_switch_7_link_0: 5.18468 bw: 16000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 6.22062 bw: 16000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Response_Data: 75328 5423616 [ 0 0 75328 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 736 52992 [ 0 0 736 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 1022 73584 [ 0 0 1022 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 361 2888 [ 0 0 361 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 77059 616472 [ 77059 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Forwarded_Control: 1108 8864 [ 1108 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 77088 616704 [ 77088 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 1108 79776 [ 0 0 1108 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 76050 5475600 [ 0 0 76050 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 77061 616488 [ 77061 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 78043 624344 [ 0 0 78043 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 5.69048 - links_utilized_percent_switch_8_link_0: 5.17496 bw: 16000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 6.20601 bw: 16000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Response_Data: 75604 5443488 [ 0 0 75604 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_ResponseL2hit_Data: 750 54000 [ 0 0 750 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_ResponseLocal_Data: 1067 76824 [ 0 0 1067 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 368 2944 [ 0 0 368 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Control: 77391 619128 [ 77391 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Forwarded_Control: 1023 8184 [ 1023 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 5.7029 + links_utilized_percent_switch_8_link_0: 5.18564 bw: 16000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 6.22017 bw: 16000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Response_Data: 75304 5421888 [ 0 0 75304 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_ResponseL2hit_Data: 771 55512 [ 0 0 771 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_ResponseLocal_Data: 1026 73872 [ 0 0 1026 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 362 2896 [ 0 0 362 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 77078 616624 [ 77078 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Forwarded_Control: 1097 8776 [ 1097 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_0_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 77424 619392 [ 77424 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_ResponseLocal_Data: 1023 73656 [ 0 0 1023 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 77103 616824 [ 77103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_ResponseLocal_Data: 1097 78984 [ 0 0 1097 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Control: 1 8 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Data: 76413 5501736 [ 0 0 76413 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 77391 619128 [ 77391 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Unblock_Control: 78356 626848 [ 0 0 78356 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Data: 76046 5475312 [ 0 0 76046 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 77079 616632 [ 77079 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Unblock_Control: 78079 624632 [ 0 0 78079 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 34.0599 - links_utilized_percent_switch_9_link_0: 27.6837 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 40.4361 bw: 16000 base_latency: 1 +links_utilized_percent_switch_9: 34.065 + links_utilized_percent_switch_9_link_0: 27.6924 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 40.4376 bw: 16000 base_latency: 1 - outgoing_messages_switch_9_link_0_Request_Control: 606065 4848520 [ 0 606065 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Data: 215707 15530904 [ 0 0 215707 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 995497 7963976 [ 0 605615 389882 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Unblock_Control: 606039 4848312 [ 0 0 606039 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 606062 43636464 [ 0 0 606062 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 605615 4844920 [ 0 605615 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Request_Control: 602395 4819160 [ 0 602395 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Data: 214541 15446952 [ 0 0 214541 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 989387 7915096 [ 0 601979 387408 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Unblock_Control: 602382 4819056 [ 0 0 602382 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 602395 43372440 [ 0 0 602395 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 601978 4815824 [ 0 601978 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 15.8814 - links_utilized_percent_switch_10_link_0: 89.6643 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 5.17063 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 5.18021 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 5.20269 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 5.17342 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 5.18944 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 5.18499 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 5.18977 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 5.17496 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 27.6837 bw: 16000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Request_Control: 620353 4962824 [ 620353 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 606056 43636032 [ 0 0 606056 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Data: 612164 44075808 [ 0 0 612164 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Control: 1225742 9805936 [ 620153 605589 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Unblock_Control: 627946 5023568 [ 0 0 627946 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 75562 5440464 [ 0 0 75562 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 740 53280 [ 0 0 740 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 1047 75384 [ 0 0 1047 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 368 2944 [ 0 0 368 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Writeback_Control: 77330 618640 [ 77330 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Forwarded_Control: 1082 8656 [ 1082 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 75625 5445000 [ 0 0 75625 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 746 53712 [ 0 0 746 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 1117 80424 [ 0 0 1117 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 424 3392 [ 0 0 424 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Writeback_Control: 77470 619760 [ 77470 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Forwarded_Control: 1068 8544 [ 1068 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Invalidate_Control: 5 40 [ 5 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 76082 5477904 [ 0 0 76082 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 739 53208 [ 0 0 739 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 1011 72792 [ 0 0 1011 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 349 2792 [ 0 0 349 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Writeback_Control: 77823 622584 [ 77823 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Forwarded_Control: 1065 8520 [ 1065 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 15.884 + links_utilized_percent_switch_10_link_0: 89.6694 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 5.17935 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 5.19538 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 5.19012 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 5.18272 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 5.18236 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 5.17792 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 5.18468 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 5.18564 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 27.6924 bw: 16000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Request_Control: 616731 4933848 [ 616731 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 602394 43372368 [ 0 0 602394 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Data: 608430 43806960 [ 0 0 608430 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 1218487 9747896 [ 616538 601949 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Unblock_Control: 624427 4995416 [ 0 0 624427 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 75216 5415552 [ 0 0 75216 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 711 51192 [ 0 0 711 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 1083 77976 [ 0 0 1083 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 390 3120 [ 0 0 390 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Control: 76993 615944 [ 76993 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Forwarded_Control: 1033 8264 [ 1033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Invalidate_Control: 4 32 [ 4 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 75484 5434848 [ 0 0 75484 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 725 52200 [ 0 0 725 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 1041 74952 [ 0 0 1041 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 365 2920 [ 0 0 365 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Control: 77218 617744 [ 77218 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Forwarded_Control: 1065 8520 [ 1065 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 75407 5429304 [ 0 0 75407 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 713 51336 [ 0 0 713 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 1049 75528 [ 0 0 1049 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 370 2960 [ 0 0 370 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Control: 77154 617232 [ 77154 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Forwarded_Control: 1067 8536 [ 1067 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_3_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 75598 5443056 [ 0 0 75598 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 752 54144 [ 0 0 752 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 1051 75672 [ 0 0 1051 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 365 2920 [ 0 0 365 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Control: 77372 618976 [ 77372 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Forwarded_Control: 993 7944 [ 993 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 75875 5463000 [ 0 0 75875 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 732 52704 [ 0 0 732 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 1026 73872 [ 0 0 1026 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 360 2880 [ 0 0 360 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Writeback_Control: 77599 620792 [ 77599 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Forwarded_Control: 1085 8680 [ 1085 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 75864 5462208 [ 0 0 75864 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 725 52200 [ 0 0 725 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 986 70992 [ 0 0 986 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 324 2592 [ 0 0 324 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Writeback_Control: 77550 620400 [ 77550 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Forwarded_Control: 1024 8192 [ 1024 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 75843 5460696 [ 0 0 75843 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 744 53568 [ 0 0 744 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 1055 75960 [ 0 0 1055 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 375 3000 [ 0 0 375 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Writeback_Control: 77618 620944 [ 77618 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Forwarded_Control: 1020 8160 [ 1020 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Data: 75604 5443488 [ 0 0 75604 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_ResponseL2hit_Data: 750 54000 [ 0 0 750 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_ResponseLocal_Data: 1067 76824 [ 0 0 1067 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 368 2944 [ 0 0 368 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Writeback_Control: 77391 619128 [ 77391 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Forwarded_Control: 1023 8184 [ 1023 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 75239 5417208 [ 0 0 75239 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 723 52056 [ 0 0 723 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 1099 79128 [ 0 0 1099 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 398 3184 [ 0 0 398 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Control: 77028 616224 [ 77028 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Forwarded_Control: 1033 8264 [ 1033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Invalidate_Control: 4 32 [ 4 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 75271 5419512 [ 0 0 75271 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 752 54144 [ 0 0 752 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 1041 74952 [ 0 0 1041 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 369 2952 [ 0 0 369 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Control: 77044 616352 [ 77044 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Forwarded_Control: 970 7760 [ 970 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 75143 5410296 [ 0 0 75143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 757 54504 [ 0 0 757 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 1087 78264 [ 0 0 1087 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 374 2992 [ 0 0 374 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Control: 76964 615712 [ 76964 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Forwarded_Control: 1075 8600 [ 1075 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 75328 5423616 [ 0 0 75328 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 736 52992 [ 0 0 736 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 1022 73584 [ 0 0 1022 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 361 2888 [ 0 0 361 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Control: 77059 616472 [ 77059 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Forwarded_Control: 1108 8864 [ 1108 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Data: 75304 5421888 [ 0 0 75304 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_ResponseL2hit_Data: 771 55512 [ 0 0 771 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_ResponseLocal_Data: 1026 73872 [ 0 0 1026 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 362 2896 [ 0 0 362 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Control: 77078 616624 [ 77078 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Forwarded_Control: 1097 8776 [ 1097 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_8_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Request_Control: 606065 4848520 [ 0 606065 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Writeback_Data: 215707 15530904 [ 0 0 215707 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Writeback_Control: 995497 7963976 [ 0 605615 389882 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Unblock_Control: 606039 4848312 [ 0 0 606039 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Request_Control: 602395 4819160 [ 0 602395 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Data: 214541 15446952 [ 0 0 214541 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Control: 989387 7915096 [ 0 601979 387408 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Unblock_Control: 602382 4819056 [ 0 0 602382 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -395,155 +392,155 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory --- L1Cache --- - Event Counts - -Load [50279 50371 50348 50325 50378 50381 50577 50451 ] 403110 +Load [49770 50076 50036 49995 49923 50384 50100 50266 ] 400550 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [27380 27235 27318 27148 27044 27143 27279 26995 ] 217542 -L1_Replacement [9623981 9626726 9624121 9629754 9634121 9629103 9619343 9631030 ] 77018179 +Store [27320 26932 27081 27130 27138 26898 27097 26821 ] 216417 +L1_Replacement [9565020 9567341 9563044 9561060 9568995 9558998 9563001 9568538 ] 76515997 Own_GETX [0 0 0 0 0 0 0 0 ] 0 -Fwd_GETX [412 391 363 348 394 387 380 384 ] 3059 -Fwd_GETS [745 679 710 731 734 737 743 663 ] 5742 +Fwd_GETX [369 399 421 410 401 406 391 360 ] 3157 +Fwd_GETS [657 744 768 748 708 713 731 718 ] 5787 Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -Inv [2 3 1 1 2 5 3 3 ] 20 -Ack [360 324 375 368 368 424 349 365 ] 2933 -Data [700 699 709 719 696 730 696 713 ] 5662 -Exclusive_Data [76933 76876 76933 76702 76653 76758 77136 76688 ] 614679 -Writeback_Ack [621 611 637 645 610 643 600 639 ] 5006 -Writeback_Ack_Data [76943 76892 76938 76703 76672 76766 77171 76688 ] 614773 -Writeback_Nack [35 47 43 43 48 61 52 45 ] 374 -All_acks [27373 27222 27311 27124 27035 27129 27272 26983 ] 217449 -Use_Timeout [76932 76874 76931 76701 76652 76757 77134 76687 ] 614668 +Inv [0 1 2 1 4 1 3 4 ] 16 +Ack [369 374 361 362 390 365 370 398 ] 2989 +Data [690 729 687 695 723 700 689 719 ] 5632 +Exclusive_Data [76374 76258 76399 76406 76287 76550 76480 76342 ] 611096 +Writeback_Ack [632 655 612 620 636 623 616 647 ] 5041 +Writeback_Ack_Data [76367 76251 76395 76404 76303 76548 76488 76339 ] 611095 +Writeback_Nack [45 58 52 54 54 47 50 42 ] 402 +All_acks [27316 26920 27074 27118 27106 26889 27089 26810 ] 216322 +Use_Timeout [76373 76257 76397 76405 76285 76549 76479 76342 ] 611087 - Transitions - -I Load [50263 50353 50331 50299 50315 50362 50561 50420 ] 402904 +I Load [49751 50067 50013 49984 49905 50362 50082 50253 ] 400417 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [27373 27223 27313 27125 27037 27129 27273 26983 ] 217456 -I L1_Replacement [66 68 63 71 62 72 54 68 ] 524 +I Store [27316 26921 27075 27119 27107 26891 27089 26812 ] 216330 +I L1_Replacement [60 76 74 73 63 75 58 67 ] 546 I Inv [0 0 0 0 0 0 0 0 ] 0 -S Load [1 0 0 1 0 0 0 0 ] 2 +S Load [0 0 0 0 0 0 0 0 ] 0 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 0 0 0 0 0 0 ] 0 -S L1_Replacement [699 697 709 719 695 728 696 713 ] 5656 -S Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +S Store [0 0 0 0 0 0 1 0 ] 1 +S L1_Replacement [690 729 686 694 723 700 687 718 ] 5627 +S Fwd_GETS [0 0 0 0 0 0 1 0 ] 1 S Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -S Inv [1 2 0 0 1 2 0 0 ] 6 +S Inv [0 0 1 1 0 0 1 1 ] 4 -O Load [0 0 0 0 0 0 0 0 ] 0 +O Load [1 0 0 1 0 0 0 0 ] 2 O Ifetch [0 0 0 0 0 0 0 0 ] 0 O Store [0 0 0 0 0 0 0 0 ] 0 -O L1_Replacement [40 29 47 42 46 56 36 40 ] 336 -O Fwd_GETX [1 0 0 0 0 0 0 0 ] 1 -O Fwd_GETS [0 0 0 0 0 0 0 1 ] 1 +O L1_Replacement [30 53 58 50 38 41 46 39 ] 355 +O Fwd_GETX [0 0 0 0 0 1 0 1 ] 2 +O Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 O Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M Load [2 1 4 2 6 3 4 1 ] 23 +M Load [1 2 2 1 4 2 4 3 ] 19 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [1 4 1 3 2 4 0 0 ] 15 -M L1_Replacement [49489 49598 49552 49504 49544 49535 49802 49635 ] 396659 -M Fwd_GETX [26 18 18 23 23 29 20 24 ] 181 -M Fwd_GETS [41 29 47 42 46 56 36 40 ] 337 +M Store [0 0 1 1 2 1 2 1 ] 8 +M L1_Replacement [49016 49246 49238 49212 49115 49591 49321 49458 ] 394197 +M Fwd_GETX [10 33 25 21 23 23 20 28 ] 183 +M Fwd_GETS [30 53 58 50 38 42 46 40 ] 357 M Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M_W Load [5 9 6 4 9 9 5 9 ] 56 +M_W Load [5 4 7 4 9 9 6 9 ] 53 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_W Store [3 5 2 5 2 4 4 6 ] 31 -M_W L1_Replacement [894462 889018 893611 898273 897698 890953 899417 899197 ] 7162629 +M_W Store [2 5 2 4 2 3 2 5 ] 25 +M_W L1_Replacement [879356 891980 884264 882870 894333 888927 886375 893054 ] 7101159 M_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 -M_W Fwd_GETX [24 11 10 9 6 12 14 15 ] 101 -M_W Fwd_GETS [25 14 26 20 25 28 31 26 ] 195 +M_W Fwd_GETX [14 9 18 16 18 13 10 9 ] 107 +M_W Fwd_GETS [16 35 34 22 30 19 22 17 ] 195 M_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 M_W Inv [0 0 0 0 0 0 0 0 ] 0 -M_W Use_Timeout [49557 49649 49618 49572 49615 49624 49858 49699 ] 397192 +M_W Use_Timeout [49056 49333 49322 49284 49178 49657 49389 49527 ] 394746 -MM Load [1 2 0 3 4 2 0 2 ] 14 +MM Load [4 0 3 2 0 1 2 0 ] 12 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [0 0 2 0 1 0 0 1 ] 4 -MM L1_Replacement [27338 27180 27269 27084 27001 27096 27242 26943 ] 217153 -MM Fwd_GETX [14 15 16 19 14 14 12 14 ] 118 -MM Fwd_GETS [24 33 29 29 24 27 22 30 ] 218 +MM Store [1 1 1 2 2 0 0 0 ] 7 +MM L1_Replacement [27267 26880 27028 27070 27069 26842 27055 26779 ] 215990 +MM Fwd_GETX [19 16 16 9 19 17 12 11 ] 119 +MM Fwd_GETS [31 27 32 42 21 34 25 26 ] 238 MM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -MM_W Load [7 4 2 4 3 2 6 1 ] 29 +MM_W Load [7 3 6 0 3 6 5 1 ] 31 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_W Store [2 3 0 2 1 2 2 2 ] 14 -MM_W L1_Replacement [504094 507882 503326 499321 498779 504839 498457 496653 ] 4013351 +MM_W Store [1 3 2 2 2 2 3 0 ] 15 +MM_W L1_Replacement [506791 494093 502435 503049 491440 498201 501724 492398 ] 3990131 MM_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 -MM_W Fwd_GETX [6 9 3 7 2 8 4 6 ] 45 -MM_W Fwd_GETS [17 12 14 20 13 8 9 7 ] 100 +MM_W Fwd_GETX [13 11 17 5 12 12 6 1 ] 77 +MM_W Fwd_GETS [13 13 12 18 16 10 17 18 ] 117 MM_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 MM_W Inv [0 0 0 0 0 0 0 0 ] 0 -MM_W Use_Timeout [27375 27225 27313 27129 27037 27133 27276 26988 ] 217476 +MM_W Use_Timeout [27317 26924 27075 27121 27107 26892 27090 26815 ] 216341 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [2881506 2856621 2857427 2836942 2832999 2852554 2848576 2869997 ] 22836622 +IM L1_Replacement [2842304 2846239 2861579 2862293 2848813 2851758 2841919 2821666 ] 22776571 IM Inv [0 0 0 0 0 0 0 0 ] 0 -IM Ack [355 320 372 365 361 419 348 361 ] 2901 +IM Ack [367 371 358 355 389 362 365 398 ] 2965 IM Data [0 0 0 0 0 0 0 0 ] 0 -IM Exclusive_Data [27373 27222 27311 27124 27035 27129 27272 26983 ] 217449 +IM Exclusive_Data [27316 26920 27074 27118 27106 26889 27088 26810 ] 216321 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 -SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM L1_Replacement [0 0 0 0 0 0 26 0 ] 26 SM Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 SM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 SM Inv [0 0 0 0 0 0 0 0 ] 0 SM Ack [0 0 0 0 0 0 0 0 ] 0 SM Data [0 0 0 0 0 0 0 0 ] 0 -SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 +SM Exclusive_Data [0 0 0 0 0 0 1 0 ] 1 OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 -OM L1_Replacement [16457 15985 15692 15697 16186 16105 15720 15815 ] 127657 +OM L1_Replacement [16235 15679 16042 15896 15540 16161 15669 15763 ] 126985 OM Own_GETX [0 0 0 0 0 0 0 0 ] 0 OM Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 OM Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 OM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -OM Ack [5 4 3 3 7 5 1 4 ] 32 -OM All_acks [27373 27222 27311 27124 27035 27129 27272 26983 ] 217449 +OM Ack [2 3 3 7 1 3 5 0 ] 24 +OM All_acks [27316 26920 27074 27118 27106 26889 27089 26810 ] 216322 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 -IS L1_Replacement [5249830 5279648 5276425 5302101 5311111 5287165 5279343 5271969 ] 42257592 +IS L1_Replacement [5243271 5242366 5221640 5219853 5241861 5226702 5240121 5268596 ] 41904410 IS Inv [0 0 0 0 0 0 0 0 ] 0 -IS Data [700 699 709 719 696 730 696 713 ] 5662 -IS Exclusive_Data [49560 49654 49622 49578 49618 49629 49864 49705 ] 397230 +IS Data [690 729 687 695 723 700 689 719 ] 5632 +IS Exclusive_Data [49058 49338 49325 49288 49181 49661 49391 49532 ] 394774 SI Load [0 0 0 0 0 0 0 0 ] 0 SI Ifetch [0 0 0 0 0 0 0 0 ] 0 -SI Store [0 0 0 0 0 0 0 0 ] 0 +SI Store [0 1 0 0 0 0 0 0 ] 1 SI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SI Fwd_GETS [1 1 0 0 0 3 3 0 ] 8 +SI Fwd_GETS [0 1 0 0 0 0 0 0 ] 1 SI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -SI Inv [1 1 1 1 1 3 3 3 ] 14 -SI Writeback_Ack [621 611 637 645 610 643 600 639 ] 5006 -SI Writeback_Ack_Data [77 85 71 73 84 82 93 71 ] 636 +SI Inv [0 1 1 0 4 1 2 3 ] 12 +SI Writeback_Ack [632 655 612 620 636 623 616 647 ] 5041 +SI Writeback_Ack_Data [58 73 73 74 83 76 69 68 ] 574 SI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 OI Load [0 0 0 0 0 0 0 0 ] 0 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 OI Store [0 0 0 0 0 0 0 0 ] 0 OI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -OI Fwd_GETX [0 3 1 3 1 2 1 2 ] 13 -OI Fwd_GETS [2 2 2 3 2 0 3 2 ] 16 +OI Fwd_GETX [1 0 1 2 3 0 2 3 ] 12 +OI Fwd_GETS [4 1 6 3 3 2 2 2 ] 23 OI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack_Data [675 614 638 656 669 669 674 595 ] 5190 -OI Writeback_Nack [33 46 42 42 46 56 49 42 ] 356 +OI Writeback_Ack_Data [592 667 683 661 635 647 662 651 ] 5198 +OI Writeback_Nack [44 56 51 53 50 46 48 38 ] 386 -MI Load [0 2 5 12 41 3 1 18 ] 82 +MI Load [1 0 5 3 2 4 1 0 ] 16 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [1 0 0 13 1 4 0 3 ] 22 +MI Store [0 1 0 2 23 1 0 3 ] 30 MI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -MI Fwd_GETX [341 335 315 287 348 322 329 323 ] 2600 -MI Fwd_GETS [635 588 592 617 624 615 639 557 ] 4867 +MI Fwd_GETX [312 330 344 357 326 340 341 307 ] 2657 +MI Fwd_GETS [563 614 626 613 600 606 618 615 ] 4855 MI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack_Data [75851 75855 75913 75684 75571 75693 76074 75697 ] 606338 +MI Writeback_Ack_Data [75405 75182 75294 75311 75256 75485 75414 75311 ] 602658 MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 II Load [0 0 0 0 0 0 0 0 ] 0 @@ -552,8 +549,8 @@ II Store [0 0 0 0 0 0 0 0 ] 0 II L1_Replacement [0 0 0 0 0 0 0 0 ] 0 II Inv [0 0 0 0 0 0 0 0 ] 0 II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack_Data [340 338 316 290 348 322 330 325 ] 2609 -II Writeback_Nack [2 1 1 1 2 5 3 3 ] 18 +II Writeback_Ack_Data [312 329 345 358 329 340 343 309 ] 2665 +II Writeback_Nack [1 2 1 1 4 1 2 4 ] 16 Cache Stats: system.l1_cntrl1.L1IcacheMemory system.l1_cntrl1.L1IcacheMemory_total_misses: 0 @@ -677,12 +674,12 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - -L1_GETS [505974 ] 505974 -L1_GETX [272402 ] 272402 -L1_PUTO [1537 ] 1537 -L1_PUTX [699984 ] 699984 -L1_PUTS_only [21786 ] 21786 -L1_PUTS [392 ] 392 +L1_GETS [502599 ] 502599 +L1_GETX [269935 ] 269935 +L1_PUTO [1741 ] 1741 +L1_PUTX [698889 ] 698889 +L1_PUTS_only [21353 ] 21353 +L1_PUTS [345 ] 345 Fwd_GETX [0 ] 0 Fwd_GETS [0 ] 0 Fwd_DMA [0 ] 0 @@ -690,21 +687,21 @@ Own_GETX [0 ] 0 Inv [0 ] 0 IntAck [0 ] 0 ExtAck [0 ] 0 -All_Acks [212463 ] 212463 -Data [212873 ] 212873 -Data_Exclusive [393182 ] 393182 -L1_WBCLEANDATA [394367 ] 394367 -L1_WBDIRTYDATA [217797 ] 217797 -Writeback_Ack [605589 ] 605589 +All_Acks [211354 ] 211354 +Data [211730 ] 211730 +Data_Exclusive [390663 ] 390663 +L1_WBCLEANDATA [391743 ] 391743 +L1_WBDIRTYDATA [216687 ] 216687 +Writeback_Ack [601949 ] 601949 Writeback_Nack [0 ] 0 -Unblock [13277 ] 13277 -Exclusive_Unblock [614667 ] 614667 +Unblock [13338 ] 13338 +Exclusive_Unblock [611088 ] 611088 DmaAck [0 ] 0 -L2_Replacement [690963 ] 690963 +L2_Replacement [687834 ] 687834 - Transitions - -NP L1_GETS [393599 ] 393599 -NP L1_GETX [212460 ] 212460 +NP L1_GETS [391040 ] 391040 +NP L1_GETX [211352 ] 211352 NP L1_PUTO [0 ] 0 NP L1_PUTX [0 ] 0 NP L1_PUTS [0 ] 0 @@ -718,21 +715,21 @@ I L1_PUTS [0 ] 0 I Inv [0 ] 0 I L2_Replacement [0 ] 0 -ILS L1_GETS [8 ] 8 -ILS L1_GETX [4 ] 4 +ILS L1_GETS [2 ] 2 +ILS L1_GETX [1 ] 1 ILS L1_PUTO [0 ] 0 ILS L1_PUTX [0 ] 0 -ILS L1_PUTS_only [624 ] 624 -ILS L1_PUTS [12 ] 12 +ILS L1_PUTS_only [568 ] 568 +ILS L1_PUTS [6 ] 6 ILS Inv [0 ] 0 ILS L2_Replacement [0 ] 0 -ILX L1_GETS [5422 ] 5422 -ILX L1_GETX [2899 ] 2899 -ILX L1_PUTO [0 ] 0 -ILX L1_PUTX [608944 ] 608944 +ILX L1_GETS [5450 ] 5450 +ILX L1_GETX [2959 ] 2959 +ILX L1_PUTO [2 ] 2 +ILX L1_PUTX [605320 ] 605320 ILX L1_PUTS_only [0 ] 0 -ILX L1_PUTS [14 ] 14 +ILX L1_PUTS [12 ] 12 ILX Fwd_GETX [0 ] 0 ILX Fwd_GETS [0 ] 0 ILX Fwd_DMA [0 ] 0 @@ -752,10 +749,10 @@ ILO Inv [0 ] 0 ILO Data [0 ] 0 ILO L2_Replacement [0 ] 0 -ILOX L1_GETS [4 ] 4 +ILOX L1_GETS [6 ] 6 ILOX L1_GETX [3 ] 3 -ILOX L1_PUTO [523 ] 523 -ILOX L1_PUTX [356 ] 356 +ILOX L1_PUTO [552 ] 552 +ILOX L1_PUTX [386 ] 386 ILOX L1_PUTS [0 ] 0 ILOX Fwd_GETX [0 ] 0 ILOX Fwd_GETS [0 ] 0 @@ -774,11 +771,11 @@ ILOS Fwd_DMA [0 ] 0 ILOS Data [0 ] 0 ILOS L2_Replacement [0 ] 0 -ILOSX L1_GETS [13 ] 13 +ILOSX L1_GETS [17 ] 17 ILOSX L1_GETX [11 ] 11 -ILOSX L1_PUTO [169 ] 169 -ILOSX L1_PUTX [4501 ] 4501 -ILOSX L1_PUTS_only [530 ] 530 +ILOSX L1_PUTO [187 ] 187 +ILOSX L1_PUTX [4462 ] 4462 +ILOSX L1_PUTS_only [561 ] 561 ILOSX L1_PUTS [2 ] 2 ILOSX Fwd_GETX [0 ] 0 ILOSX Fwd_GETS [0 ] 0 @@ -790,7 +787,7 @@ S L1_GETX [2 ] 2 S L1_PUTX [0 ] 0 S L1_PUTS [0 ] 0 S Inv [0 ] 0 -S L2_Replacement [628 ] 628 +S L2_Replacement [567 ] 567 O L1_GETS [0 ] 0 O L1_GETX [0 ] 0 @@ -810,34 +807,34 @@ OLS Fwd_GETS [0 ] 0 OLS Fwd_DMA [0 ] 0 OLS L2_Replacement [0 ] 0 -OLSX L1_GETS [18 ] 18 +OLSX L1_GETS [14 ] 14 OLSX L1_GETX [5 ] 5 OLSX L1_PUTO [0 ] 0 OLSX L1_PUTX [1 ] 1 -OLSX L1_PUTS_only [4438 ] 4438 +OLSX L1_PUTS_only [4447 ] 4447 OLSX L1_PUTS [25 ] 25 OLSX Fwd_GETX [0 ] 0 OLSX Fwd_GETS [0 ] 0 OLSX Fwd_DMA [0 ] 0 -OLSX L2_Replacement [224 ] 224 +OLSX L2_Replacement [194 ] 194 SLS L1_GETS [0 ] 0 SLS L1_GETX [0 ] 0 SLS L1_PUTX [0 ] 0 -SLS L1_PUTS_only [11 ] 11 +SLS L1_PUTS_only [6 ] 6 SLS L1_PUTS [0 ] 0 SLS Inv [0 ] 0 -SLS L2_Replacement [6 ] 6 +SLS L2_Replacement [5 ] 5 -M L1_GETS [3831 ] 3831 -M L1_GETX [2069 ] 2069 +M L1_GETS [3874 ] 3874 +M L1_GETX [1990 ] 1990 M L1_PUTO [0 ] 0 -M L1_PUTX [3 ] 3 +M L1_PUTX [1 ] 1 M L1_PUTS [0 ] 0 M Fwd_GETX [0 ] 0 M Fwd_GETS [0 ] 0 M Fwd_DMA [0 ] 0 -M L2_Replacement [605391 ] 605391 +M L2_Replacement [601785 ] 601785 IFGX L1_GETS [0 ] 0 IFGX L1_GETX [0 ] 0 @@ -936,19 +933,19 @@ ILOW L1_WBDIRTYDATA [0 ] 0 ILOW Unblock [0 ] 0 ILOW L2_Replacement [0 ] 0 -ILOXW L1_GETS [53 ] 53 -ILOXW L1_GETX [29 ] 29 -ILOXW L1_PUTO [832 ] 832 -ILOXW L1_PUTX [5127 ] 5127 +ILOXW L1_GETS [92 ] 92 +ILOXW L1_GETX [44 ] 44 +ILOXW L1_PUTO [881 ] 881 +ILOXW L1_PUTX [5612 ] 5612 ILOXW L1_PUTS_only [0 ] 0 ILOXW L1_PUTS [0 ] 0 ILOXW Fwd_GETX [0 ] 0 ILOXW Fwd_GETS [0 ] 0 ILOXW Fwd_DMA [0 ] 0 ILOXW Inv [0 ] 0 -ILOXW L1_WBCLEANDATA [380 ] 380 -ILOXW L1_WBDIRTYDATA [143 ] 143 -ILOXW Unblock [530 ] 530 +ILOXW L1_WBCLEANDATA [445 ] 445 +ILOXW L1_WBDIRTYDATA [107 ] 107 +ILOXW Unblock [561 ] 561 ILOXW L2_Replacement [0 ] 0 ILOSW L1_GETS [0 ] 0 @@ -966,18 +963,18 @@ ILOSW L1_WBDIRTYDATA [0 ] 0 ILOSW Unblock [0 ] 0 ILOSW L2_Replacement [0 ] 0 -ILOSXW L1_GETS [138 ] 138 -ILOSXW L1_GETX [49 ] 49 -ILOSXW L1_PUTO [0 ] 0 -ILOSXW L1_PUTX [47 ] 47 -ILOSXW L1_PUTS_only [14733 ] 14733 -ILOSXW L1_PUTS [40 ] 40 +ILOSXW L1_GETS [137 ] 137 +ILOSXW L1_GETX [61 ] 61 +ILOSXW L1_PUTO [12 ] 12 +ILOSXW L1_PUTX [34 ] 34 +ILOSXW L1_PUTS_only [14614 ] 14614 +ILOSXW L1_PUTS [53 ] 53 ILOSXW Fwd_GETX [0 ] 0 ILOSXW Fwd_GETS [0 ] 0 ILOSXW Fwd_DMA [0 ] 0 ILOSXW Inv [0 ] 0 -ILOSXW L1_WBCLEANDATA [3108 ] 3108 -ILOSXW L1_WBDIRTYDATA [1559 ] 1559 +ILOSXW L1_WBCLEANDATA [3065 ] 3065 +ILOSXW L1_WBDIRTYDATA [1581 ] 1581 ILOSXW Unblock [5 ] 5 ILOSXW L2_Replacement [0 ] 0 @@ -1012,17 +1009,17 @@ ILSW L1_GETX [0 ] 0 ILSW L1_PUTO [0 ] 0 ILSW L1_PUTX [0 ] 0 ILSW L1_PUTS_only [0 ] 0 -ILSW L1_PUTS [53 ] 53 +ILSW L1_PUTS [32 ] 32 ILSW Fwd_GETX [0 ] 0 ILSW Fwd_GETS [0 ] 0 ILSW Fwd_DMA [0 ] 0 ILSW Inv [0 ] 0 -ILSW L1_WBCLEANDATA [12 ] 12 +ILSW L1_WBCLEANDATA [6 ] 6 ILSW Unblock [0 ] 0 ILSW L2_Replacement [0 ] 0 -IW L1_GETS [22 ] 22 -IW L1_GETX [25 ] 25 +IW L1_GETS [48 ] 48 +IW L1_GETX [5 ] 5 IW L1_PUTO [0 ] 0 IW L1_PUTX [0 ] 0 IW L1_PUTS_only [0 ] 0 @@ -1031,7 +1028,7 @@ IW Fwd_GETX [0 ] 0 IW Fwd_GETS [0 ] 0 IW Fwd_DMA [0 ] 0 IW Inv [0 ] 0 -IW L1_WBCLEANDATA [624 ] 624 +IW L1_WBCLEANDATA [568 ] 568 IW L2_Replacement [0 ] 0 OW L1_GETS [0 ] 0 @@ -1057,11 +1054,11 @@ SW Fwd_GETX [0 ] 0 SW Fwd_GETS [0 ] 0 SW Fwd_DMA [0 ] 0 SW Inv [0 ] 0 -SW Unblock [11 ] 11 -SW L2_Replacement [133 ] 133 +SW Unblock [6 ] 6 +SW L2_Replacement [179 ] 179 -OXW L1_GETS [117 ] 117 -OXW L1_GETX [45 ] 45 +OXW L1_GETS [131 ] 131 +OXW L1_GETX [92 ] 92 OXW L1_PUTO [0 ] 0 OXW L1_PUTX [0 ] 0 OXW L1_PUTS_only [0 ] 0 @@ -1070,49 +1067,49 @@ OXW Fwd_GETX [0 ] 0 OXW Fwd_GETS [0 ] 0 OXW Fwd_DMA [0 ] 0 OXW Inv [0 ] 0 -OXW Unblock [4438 ] 4438 -OXW L2_Replacement [32689 ] 32689 +OXW Unblock [4447 ] 4447 +OXW L2_Replacement [33156 ] 33156 OLSXW L1_GETS [0 ] 0 OLSXW L1_GETX [0 ] 0 OLSXW L1_PUTO [0 ] 0 OLSXW L1_PUTX [0 ] 0 OLSXW L1_PUTS_only [0 ] 0 -OLSXW L1_PUTS [95 ] 95 +OLSXW L1_PUTS [99 ] 99 OLSXW Fwd_GETX [0 ] 0 OLSXW Fwd_GETS [0 ] 0 OLSXW Fwd_DMA [0 ] 0 OLSXW Inv [0 ] 0 OLSXW Unblock [25 ] 25 -OLSXW L2_Replacement [129 ] 129 +OLSXW L2_Replacement [164 ] 164 -ILXW L1_GETS [23832 ] 23832 -ILXW L1_GETX [12720 ] 12720 +ILXW L1_GETS [24371 ] 24371 +ILXW L1_GETX [12212 ] 12212 ILXW L1_PUTO [0 ] 0 -ILXW L1_PUTX [5328 ] 5328 +ILXW L1_PUTX [5446 ] 5446 ILXW L1_PUTS_only [0 ] 0 -ILXW L1_PUTS [6 ] 6 +ILXW L1_PUTS [33 ] 33 ILXW Fwd_GETX [0 ] 0 ILXW Fwd_GETS [0 ] 0 ILXW Fwd_DMA [0 ] 0 ILXW Inv [0 ] 0 ILXW Data [0 ] 0 -ILXW L1_WBCLEANDATA [390243 ] 390243 -ILXW L1_WBDIRTYDATA [216095 ] 216095 -ILXW Unblock [2606 ] 2606 +ILXW L1_WBCLEANDATA [387659 ] 387659 +ILXW L1_WBDIRTYDATA [214999 ] 214999 +ILXW Unblock [2662 ] 2662 ILXW L2_Replacement [0 ] 0 IFLS L1_GETS [0 ] 0 IFLS L1_GETX [0 ] 0 IFLS L1_PUTO [0 ] 0 IFLS L1_PUTX [0 ] 0 -IFLS L1_PUTS_only [103 ] 103 +IFLS L1_PUTS_only [10 ] 10 IFLS L1_PUTS [0 ] 0 IFLS Fwd_GETX [0 ] 0 IFLS Fwd_GETS [0 ] 0 IFLS Fwd_DMA [0 ] 0 IFLS Inv [0 ] 0 -IFLS Unblock [8 ] 8 +IFLS Unblock [2 ] 2 IFLS L2_Replacement [0 ] 0 IFLO L1_GETS [0 ] 0 @@ -1130,51 +1127,51 @@ IFLO L2_Replacement [0 ] 0 IFLOX L1_GETS [0 ] 0 IFLOX L1_GETX [0 ] 0 -IFLOX L1_PUTO [0 ] 0 -IFLOX L1_PUTX [15 ] 15 -IFLOX L1_PUTS_only [54 ] 54 +IFLOX L1_PUTO [12 ] 12 +IFLOX L1_PUTX [9 ] 9 +IFLOX L1_PUTS_only [41 ] 41 IFLOX L1_PUTS [0 ] 0 IFLOX Fwd_GETX [0 ] 0 IFLOX Fwd_GETS [0 ] 0 IFLOX Fwd_DMA [0 ] 0 IFLOX Inv [0 ] 0 -IFLOX Unblock [4 ] 4 +IFLOX Unblock [6 ] 6 IFLOX Exclusive_Unblock [5 ] 5 IFLOX L2_Replacement [0 ] 0 -IFLOXX L1_GETS [442 ] 442 -IFLOXX L1_GETX [254 ] 254 -IFLOXX L1_PUTO [13 ] 13 -IFLOXX L1_PUTX [74766 ] 74766 +IFLOXX L1_GETS [582 ] 582 +IFLOXX L1_GETX [227 ] 227 +IFLOXX L1_PUTO [75 ] 75 +IFLOXX L1_PUTX [76657 ] 76657 IFLOXX L1_PUTS_only [0 ] 0 -IFLOXX L1_PUTS [81 ] 81 +IFLOXX L1_PUTS [44 ] 44 IFLOXX Fwd_GETX [0 ] 0 IFLOXX Fwd_GETS [0 ] 0 IFLOXX Fwd_DMA [0 ] 0 IFLOXX Inv [0 ] 0 -IFLOXX Unblock [5204 ] 5204 -IFLOXX Exclusive_Unblock [3120 ] 3120 +IFLOXX Unblock [5212 ] 5212 +IFLOXX Exclusive_Unblock [3200 ] 3200 IFLOXX L2_Replacement [0 ] 0 IFLOSX L1_GETS [0 ] 0 IFLOSX L1_GETX [0 ] 0 -IFLOSX L1_PUTO [0 ] 0 -IFLOSX L1_PUTX [153 ] 153 -IFLOSX L1_PUTS_only [73 ] 73 +IFLOSX L1_PUTO [3 ] 3 +IFLOSX L1_PUTX [165 ] 165 +IFLOSX L1_PUTS_only [48 ] 48 IFLOSX L1_PUTS [0 ] 0 IFLOSX Fwd_GETX [0 ] 0 IFLOSX Fwd_GETS [0 ] 0 IFLOSX Fwd_DMA [0 ] 0 IFLOSX Inv [0 ] 0 -IFLOSX Unblock [13 ] 13 +IFLOSX Unblock [17 ] 17 IFLOSX Exclusive_Unblock [0 ] 0 IFLOSX L2_Replacement [0 ] 0 IFLXO L1_GETS [0 ] 0 IFLXO L1_GETX [0 ] 0 -IFLXO L1_PUTO [0 ] 0 -IFLXO L1_PUTX [122 ] 122 -IFLXO L1_PUTS_only [24 ] 24 +IFLXO L1_PUTO [17 ] 17 +IFLXO L1_PUTX [99 ] 99 +IFLXO L1_PUTS_only [65 ] 65 IFLXO L1_PUTS [0 ] 0 IFLXO Fwd_GETX [0 ] 0 IFLXO Fwd_GETS [0 ] 0 @@ -1183,25 +1180,25 @@ IFLXO Inv [0 ] 0 IFLXO Exclusive_Unblock [11 ] 11 IFLXO L2_Replacement [0 ] 0 -IGS L1_GETS [49466 ] 49466 -IGS L1_GETX [26282 ] 26282 +IGS L1_GETS [48810 ] 48810 +IGS L1_GETX [25987 ] 25987 IGS L1_PUTO [0 ] 0 -IGS L1_PUTX [400 ] 400 +IGS L1_PUTX [487 ] 487 IGS L1_PUTS_only [0 ] 0 -IGS L1_PUTS [4 ] 4 +IGS L1_PUTS [11 ] 11 IGS Fwd_GETX [0 ] 0 IGS Fwd_GETS [0 ] 0 IGS Fwd_DMA [0 ] 0 IGS Own_GETX [0 ] 0 IGS Inv [0 ] 0 -IGS Data [410 ] 410 -IGS Data_Exclusive [393182 ] 393182 -IGS Unblock [410 ] 410 -IGS Exclusive_Unblock [393173 ] 393173 +IGS Data [376 ] 376 +IGS Data_Exclusive [390663 ] 390663 +IGS Unblock [376 ] 376 +IGS Exclusive_Unblock [390659 ] 390659 IGS L2_Replacement [0 ] 0 -IGM L1_GETS [21007 ] 21007 -IGM L1_GETX [11459 ] 11459 +IGM L1_GETS [20521 ] 20521 +IGM L1_GETX [10939 ] 10939 IGM L1_PUTO [0 ] 0 IGM L1_PUTX [0 ] 0 IGM L1_PUTS_only [0 ] 0 @@ -1212,7 +1209,7 @@ IGM Fwd_DMA [0 ] 0 IGM Own_GETX [0 ] 0 IGM Inv [0 ] 0 IGM ExtAck [0 ] 0 -IGM Data [212459 ] 212459 +IGM Data [211353 ] 211353 IGM Data_Exclusive [0 ] 0 IGM L2_Replacement [0 ] 0 @@ -1220,29 +1217,29 @@ IGMLS L1_GETS [0 ] 0 IGMLS L1_GETX [0 ] 0 IGMLS L1_PUTO [0 ] 0 IGMLS L1_PUTX [0 ] 0 -IGMLS L1_PUTS_only [60 ] 60 +IGMLS L1_PUTS_only [1 ] 1 IGMLS L1_PUTS [0 ] 0 IGMLS Inv [0 ] 0 IGMLS IntAck [0 ] 0 IGMLS ExtAck [0 ] 0 IGMLS All_Acks [0 ] 0 -IGMLS Data [4 ] 4 +IGMLS Data [1 ] 1 IGMLS Data_Exclusive [0 ] 0 IGMLS L2_Replacement [0 ] 0 -IGMO L1_GETS [5289 ] 5289 -IGMO L1_GETX [2901 ] 2901 +IGMO L1_GETS [5020 ] 5020 +IGMO L1_GETX [2732 ] 2732 IGMO L1_PUTO [0 ] 0 -IGMO L1_PUTX [190 ] 190 -IGMO L1_PUTS_only [27 ] 27 +IGMO L1_PUTX [196 ] 196 +IGMO L1_PUTS_only [17 ] 17 IGMO L1_PUTS [0 ] 0 IGMO Fwd_GETX [0 ] 0 IGMO Fwd_GETS [0 ] 0 IGMO Fwd_DMA [0 ] 0 IGMO Own_GETX [0 ] 0 IGMO ExtAck [0 ] 0 -IGMO All_Acks [212463 ] 212463 -IGMO Exclusive_Unblock [212458 ] 212458 +IGMO All_Acks [211354 ] 211354 +IGMO Exclusive_Unblock [211349 ] 211349 IGMO L2_Replacement [0 ] 0 IGMIO L1_GETS [0 ] 0 @@ -1312,17 +1309,17 @@ II L1_PUTS [0 ] 0 II IntAck [0 ] 0 II All_Acks [0 ] 0 -MM L1_GETS [57 ] 57 -MM L1_GETX [35 ] 35 +MM L1_GETS [52 ] 52 +MM L1_GETX [15 ] 15 MM L1_PUTO [0 ] 0 -MM L1_PUTX [14 ] 14 +MM L1_PUTX [4 ] 4 MM L1_PUTS_only [0 ] 0 MM L1_PUTS [0 ] 0 MM Fwd_GETX [0 ] 0 MM Fwd_GETS [0 ] 0 MM Fwd_DMA [0 ] 0 MM Inv [0 ] 0 -MM Exclusive_Unblock [2069 ] 2069 +MM Exclusive_Unblock [1990 ] 1990 MM L2_Replacement [0 ] 0 SS L1_GETS [0 ] 0 @@ -1336,12 +1333,12 @@ SS Fwd_GETS [0 ] 0 SS Fwd_DMA [0 ] 0 SS Inv [0 ] 0 SS Unblock [5 ] 5 -SS L2_Replacement [117 ] 117 +SS L2_Replacement [109 ] 109 -OO L1_GETS [82 ] 82 -OO L1_GETX [23 ] 23 +OO L1_GETS [104 ] 104 +OO L1_GETX [54 ] 54 OO L1_PUTO [0 ] 0 -OO L1_PUTX [17 ] 17 +OO L1_PUTX [10 ] 10 OO L1_PUTS_only [0 ] 0 OO L1_PUTS [0 ] 0 OO Fwd_GETX [0 ] 0 @@ -1349,8 +1346,8 @@ OO Fwd_GETS [0 ] 0 OO Fwd_DMA [0 ] 0 OO Inv [0 ] 0 OO Unblock [0 ] 0 -OO Exclusive_Unblock [3831 ] 3831 -OO L2_Replacement [51513 ] 51513 +OO Exclusive_Unblock [3874 ] 3874 +OO L2_Replacement [51617 ] 51617 OLSS L1_GETS [0 ] 0 OLSS L1_GETX [0 ] 0 @@ -1369,14 +1366,14 @@ OLSXS L1_GETS [0 ] 0 OLSXS L1_GETX [0 ] 0 OLSXS L1_PUTO [0 ] 0 OLSXS L1_PUTX [0 ] 0 -OLSXS L1_PUTS_only [76 ] 76 +OLSXS L1_PUTS_only [24 ] 24 OLSXS L1_PUTS [0 ] 0 OLSXS Fwd_GETX [0 ] 0 OLSXS Fwd_GETS [0 ] 0 OLSXS Fwd_DMA [0 ] 0 OLSXS Inv [0 ] 0 -OLSXS Unblock [18 ] 18 -OLSXS L2_Replacement [133 ] 133 +OLSXS Unblock [14 ] 14 +OLSXS L2_Replacement [58 ] 58 SLSS L1_GETS [0 ] 0 SLSS L1_GETX [0 ] 0 @@ -1404,8 +1401,8 @@ OI Writeback_Ack [0 ] 0 OI Writeback_Nack [0 ] 0 OI L2_Replacement [0 ] 0 -MI L1_GETS [2569 ] 2569 -MI L1_GETX [1127 ] 1127 +MI L1_GETS [2323 ] 2323 +MI L1_GETX [1244 ] 1244 MI L1_PUTO [0 ] 0 MI L1_PUTX [0 ] 0 MI L1_PUTS_only [0 ] 0 @@ -1413,7 +1410,7 @@ MI L1_PUTS [0 ] 0 MI Fwd_GETX [0 ] 0 MI Fwd_GETS [0 ] 0 MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [605365 ] 605365 +MI Writeback_Ack [601755 ] 601755 MI L2_Replacement [0 ] 0 MII L1_GETS [0 ] 0 @@ -1430,12 +1427,12 @@ OLSI L1_GETS [0 ] 0 OLSI L1_GETX [0 ] 0 OLSI L1_PUTO [0 ] 0 OLSI L1_PUTX [0 ] 0 -OLSI L1_PUTS_only [1033 ] 1033 -OLSI L1_PUTS [60 ] 60 +OLSI L1_PUTS_only [951 ] 951 +OLSI L1_PUTS [28 ] 28 OLSI Fwd_GETX [0 ] 0 OLSI Fwd_GETS [0 ] 0 OLSI Fwd_DMA [0 ] 0 -OLSI Writeback_Ack [224 ] 224 +OLSI Writeback_Ack [194 ] 194 OLSI L2_Replacement [0 ] 0 ILSI L1_GETS [0 ] 0 @@ -1520,60 +1517,60 @@ ILOXD DmaAck [0 ] 0 ILOXD L2_Replacement [0 ] 0 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 821772 - memory_reads: 606065 - memory_writes: 215707 - memory_refreshes: 52039 - memory_total_request_delays: 22424142 - memory_delays_per_request: 27.2875 - memory_delays_in_input_queue: 6964841 - memory_delays_behind_head_of_bank_queue: 3660974 - memory_delays_stalled_at_head_of_bank_queue: 11798327 - memory_stalls_for_bank_busy: 2081487 + memory_total_requests: 816936 + memory_reads: 602395 + memory_writes: 214541 + memory_refreshes: 51722 + memory_total_request_delays: 22342097 + memory_delays_per_request: 27.3487 + memory_delays_in_input_queue: 6936500 + memory_delays_behind_head_of_bank_queue: 3657957 + memory_delays_stalled_at_head_of_bank_queue: 11747640 + memory_stalls_for_bank_busy: 2071627 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 1350390 - memory_stalls_for_arbitration: 2933922 - memory_stalls_for_bus: 3903395 + memory_stalls_for_anti_starvation: 1343300 + memory_stalls_for_arbitration: 2923071 + memory_stalls_for_bus: 3887594 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 209449 - memory_stalls_for_read_read_turnaround: 1319684 - accesses_per_bank: 25864 25491 25592 25881 25881 25791 25975 25705 25887 25731 25699 25862 25496 25585 25671 25539 25640 25704 25722 25677 25725 25588 25755 25618 25553 25240 25653 25233 25561 25783 25986 25684 + memory_stalls_for_read_write_turnaround: 209035 + memory_stalls_for_read_read_turnaround: 1313013 + accesses_per_bank: 25645 25506 25688 25421 25710 25730 25445 25618 25564 25661 25458 25581 25419 25676 25266 25810 25879 25463 25473 25713 25644 25125 25421 25355 25459 25466 25459 25481 25240 25550 25475 25535 --- Directory --- - Event Counts - -GETX [212467 ] 212467 -GETS [393608 ] 393608 -PUTX [605391 ] 605391 +GETX [211356 ] 211356 +GETS [391044 ] 391044 +PUTX [601785 ] 601785 PUTO [0 ] 0 -PUTO_SHARERS [224 ] 224 +PUTO_SHARERS [194 ] 194 Unblock [0 ] 0 -Last_Unblock [410 ] 410 -Exclusive_Unblock [605629 ] 605629 -Clean_Writeback [389882 ] 389882 -Dirty_Writeback [215707 ] 215707 -Memory_Data [606062 ] 606062 -Memory_Ack [215706 ] 215706 +Last_Unblock [376 ] 376 +Exclusive_Unblock [602006 ] 602006 +Clean_Writeback [387408 ] 387408 +Dirty_Writeback [214541 ] 214541 +Memory_Data [602395 ] 602395 +Memory_Ack [214541 ] 214541 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 DMA_ACK [0 ] 0 Data [0 ] 0 - Transitions - -I GETX [212244 ] 212244 -I GETS [393189 ] 393189 +I GETX [211163 ] 211163 +I GETS [390664 ] 390664 I PUTX [0 ] 0 I PUTO [0 ] 0 I Memory_Data [0 ] 0 -I Memory_Ack [213990 ] 213990 +I Memory_Ack [212848 ] 212848 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 -S GETX [222 ] 222 -S GETS [410 ] 410 +S GETX [192 ] 192 +S GETS [376 ] 376 S PUTX [0 ] 0 S PUTO [0 ] 0 S Memory_Data [0 ] 0 -S Memory_Ack [67 ] 67 +S Memory_Ack [56 ] 56 S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 @@ -1589,9 +1586,9 @@ O DMA_WRITE [0 ] 0 M GETX [0 ] 0 M GETS [0 ] 0 -M PUTX [605391 ] 605391 +M PUTX [601785 ] 601785 M PUTO [0 ] 0 -M PUTO_SHARERS [224 ] 224 +M PUTO_SHARERS [194 ] 194 M Memory_Data [0 ] 0 M Memory_Ack [0 ] 0 M DMA_READ [0 ] 0 @@ -1603,9 +1600,9 @@ IS PUTX [0 ] 0 IS PUTO [0 ] 0 IS PUTO_SHARERS [0 ] 0 IS Unblock [0 ] 0 -IS Exclusive_Unblock [393172 ] 393172 -IS Memory_Data [393187 ] 393187 -IS Memory_Ack [1076 ] 1076 +IS Exclusive_Unblock [390658 ] 390658 +IS Memory_Data [390664 ] 390664 +IS Memory_Ack [1043 ] 1043 IS DMA_READ [0 ] 0 IS DMA_WRITE [0 ] 0 @@ -1615,8 +1612,8 @@ SS PUTX [0 ] 0 SS PUTO [0 ] 0 SS PUTO_SHARERS [0 ] 0 SS Unblock [0 ] 0 -SS Last_Unblock [410 ] 410 -SS Memory_Data [410 ] 410 +SS Last_Unblock [376 ] 376 +SS Memory_Data [376 ] 376 SS Memory_Ack [0 ] 0 SS DMA_READ [0 ] 0 SS DMA_WRITE [0 ] 0 @@ -1650,21 +1647,21 @@ MM GETS [0 ] 0 MM PUTX [0 ] 0 MM PUTO [0 ] 0 MM PUTO_SHARERS [0 ] 0 -MM Exclusive_Unblock [212457 ] 212457 -MM Memory_Data [212465 ] 212465 -MM Memory_Ack [573 ] 573 +MM Exclusive_Unblock [211348 ] 211348 +MM Memory_Data [211355 ] 211355 +MM Memory_Ack [594 ] 594 MM DMA_READ [0 ] 0 MM DMA_WRITE [0 ] 0 MI GETX [1 ] 1 -MI GETS [9 ] 9 +MI GETS [4 ] 4 MI PUTX [0 ] 0 MI PUTO [0 ] 0 MI PUTO_SHARERS [0 ] 0 MI Unblock [0 ] 0 -MI Clean_Writeback [389726 ] 389726 -MI Dirty_Writeback [215639 ] 215639 +MI Clean_Writeback [387270 ] 387270 +MI Dirty_Writeback [214485 ] 214485 MI Memory_Data [0 ] 0 MI Memory_Ack [0 ] 0 MI DMA_READ [0 ] 0 @@ -1676,8 +1673,8 @@ MIS PUTX [0 ] 0 MIS PUTO [0 ] 0 MIS PUTO_SHARERS [0 ] 0 MIS Unblock [0 ] 0 -MIS Clean_Writeback [156 ] 156 -MIS Dirty_Writeback [68 ] 68 +MIS Clean_Writeback [138 ] 138 +MIS Dirty_Writeback [56 ] 56 MIS Memory_Data [0 ] 0 MIS Memory_Ack [0 ] 0 MIS DMA_READ [0 ] 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr index 3b19f4e09..aba8d4e6f 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr @@ -1,74 +1,82 @@ -system.cpu4: completed 10000 read, 5361 write accesses @736700 -system.cpu2: completed 10000 read, 5258 write accesses @741379 -system.cpu3: completed 10000 read, 5403 write accesses @747863 -system.cpu1: completed 10000 read, 5292 write accesses @751357 -system.cpu6: completed 10000 read, 5451 write accesses @754502 -system.cpu7: completed 10000 read, 5438 write accesses @755068 -system.cpu5: completed 10000 read, 5557 write accesses @759525 -system.cpu0: completed 10000 read, 5442 write accesses @772965 -system.cpu4: completed 20000 read, 10700 write accesses @1474707 -system.cpu7: completed 20000 read, 10673 write accesses @1490391 -system.cpu2: completed 20000 read, 10490 write accesses @1492637 -system.cpu3: completed 20000 read, 10828 write accesses @1496240 -system.cpu1: completed 20000 read, 10531 write accesses @1496747 -system.cpu6: completed 20000 read, 10827 write accesses @1502187 -system.cpu5: completed 20000 read, 10968 write accesses @1509184 -system.cpu0: completed 20000 read, 10821 write accesses @1515170 -system.cpu4: completed 30000 read, 16140 write accesses @2234178 -system.cpu2: completed 30000 read, 15837 write accesses @2240133 -system.cpu1: completed 30000 read, 15925 write accesses @2244203 -system.cpu6: completed 30000 read, 16178 write accesses @2245026 -system.cpu0: completed 30000 read, 16116 write accesses @2252500 -system.cpu7: completed 30000 read, 16150 write accesses @2252680 -system.cpu5: completed 30000 read, 16546 write accesses @2254097 -system.cpu3: completed 30000 read, 16154 write accesses @2258292 -system.cpu2: completed 40000 read, 21131 write accesses @2982888 -system.cpu4: completed 40000 read, 21564 write accesses @2988433 -system.cpu6: completed 40000 read, 21517 write accesses @2995571 -system.cpu7: completed 40000 read, 21451 write accesses @3002984 -system.cpu0: completed 40000 read, 21558 write accesses @3005254 -system.cpu1: completed 40000 read, 21476 write accesses @3010475 -system.cpu3: completed 40000 read, 21590 write accesses @3015598 -system.cpu5: completed 40000 read, 21951 write accesses @3024338 -system.cpu2: completed 50000 read, 26563 write accesses @3740176 -system.cpu4: completed 50000 read, 27047 write accesses @3743329 -system.cpu7: completed 50000 read, 26749 write accesses @3757917 -system.cpu6: completed 50000 read, 26964 write accesses @3758280 -system.cpu0: completed 50000 read, 27012 write accesses @3762857 -system.cpu5: completed 50000 read, 27348 write accesses @3768681 -system.cpu1: completed 50000 read, 26902 write accesses @3773494 -system.cpu3: completed 50000 read, 27102 write accesses @3774586 -system.cpu2: completed 60000 read, 32068 write accesses @4487250 -system.cpu4: completed 60000 read, 32524 write accesses @4492613 -system.cpu7: completed 60000 read, 32123 write accesses @4501802 -system.cpu5: completed 60000 read, 32618 write accesses @4505087 -system.cpu6: completed 60000 read, 32304 write accesses @4507148 -system.cpu1: completed 60000 read, 32342 write accesses @4512477 -system.cpu0: completed 60000 read, 32196 write accesses @4513791 -system.cpu3: completed 60000 read, 32477 write accesses @4527938 -system.cpu4: completed 70000 read, 38050 write accesses @5246087 -system.cpu2: completed 70000 read, 37438 write accesses @5246857 -system.cpu6: completed 70000 read, 37522 write accesses @5247624 -system.cpu1: completed 70000 read, 37552 write accesses @5255630 -system.cpu7: completed 70000 read, 37454 write accesses @5256746 -system.cpu5: completed 70000 read, 37853 write accesses @5262449 -system.cpu3: completed 70000 read, 37751 write accesses @5263226 -system.cpu0: completed 70000 read, 37564 write accesses @5268794 -system.cpu6: completed 80000 read, 42984 write accesses @5994771 -system.cpu4: completed 80000 read, 43493 write accesses @5995916 -system.cpu5: completed 80000 read, 42965 write accesses @6000829 -system.cpu2: completed 80000 read, 42825 write accesses @6004649 -system.cpu0: completed 80000 read, 42741 write accesses @6006103 -system.cpu1: completed 80000 read, 42738 write accesses @6009758 -system.cpu7: completed 80000 read, 42872 write accesses @6009923 -system.cpu3: completed 80000 read, 43090 write accesses @6011644 -system.cpu6: completed 90000 read, 48315 write accesses @6743220 -system.cpu4: completed 90000 read, 48816 write accesses @6743546 -system.cpu1: completed 90000 read, 48145 write accesses @6749147 -system.cpu2: completed 90000 read, 48237 write accesses @6753252 -system.cpu5: completed 90000 read, 48465 write accesses @6756537 -system.cpu3: completed 90000 read, 48531 write accesses @6772036 -system.cpu0: completed 90000 read, 48152 write accesses @6774043 -system.cpu7: completed 90000 read, 48393 write accesses @6775135 -system.cpu4: completed 100000 read, 54127 write accesses @7493512 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +system.cpu4: completed 10000 read, 5367 write accesses @734529 +system.cpu2: completed 10000 read, 5411 write accesses @739034 +system.cpu3: completed 10000 read, 5397 write accesses @741278 +system.cpu6: completed 10000 read, 5401 write accesses @742830 +system.cpu1: completed 10000 read, 5459 write accesses @745510 +system.cpu7: completed 10000 read, 5449 write accesses @745578 +system.cpu5: completed 10000 read, 5460 write accesses @752999 +system.cpu0: completed 10000 read, 5374 write accesses @754640 +system.cpu4: completed 20000 read, 10811 write accesses @1483097 +system.cpu6: completed 20000 read, 10717 write accesses @1490444 +system.cpu3: completed 20000 read, 10857 write accesses @1492719 +system.cpu2: completed 20000 read, 10867 write accesses @1494524 +system.cpu5: completed 20000 read, 10900 write accesses @1496108 +system.cpu1: completed 20000 read, 10872 write accesses @1496903 +system.cpu0: completed 20000 read, 10931 write accesses @1504162 +system.cpu7: completed 20000 read, 11167 write accesses @1514664 +system.cpu4: completed 30000 read, 16318 write accesses @2226152 +system.cpu6: completed 30000 read, 16244 write accesses @2235778 +system.cpu1: completed 30000 read, 16305 write accesses @2241693 +system.cpu3: completed 30000 read, 16231 write accesses @2243127 +system.cpu5: completed 30000 read, 16446 write accesses @2247293 +system.cpu2: completed 30000 read, 16424 write accesses @2250994 +system.cpu0: completed 30000 read, 16501 write accesses @2260704 +system.cpu7: completed 30000 read, 16627 write accesses @2268008 +system.cpu4: completed 40000 read, 21749 write accesses @2962709 +system.cpu1: completed 40000 read, 21593 write accesses @2979076 +system.cpu6: completed 40000 read, 21829 write accesses @2993869 +system.cpu3: completed 40000 read, 21830 write accesses @2994935 +system.cpu0: completed 40000 read, 21924 write accesses @3006797 +system.cpu5: completed 40000 read, 22012 write accesses @3007541 +system.cpu2: completed 40000 read, 21921 write accesses @3009943 +system.cpu7: completed 40000 read, 22003 write accesses @3016612 +system.cpu1: completed 50000 read, 26824 write accesses @3710601 +system.cpu4: completed 50000 read, 27284 write accesses @3716733 +system.cpu5: completed 50000 read, 27307 write accesses @3743758 +system.cpu6: completed 50000 read, 27337 write accesses @3752012 +system.cpu2: completed 50000 read, 27397 write accesses @3754564 +system.cpu0: completed 50000 read, 27281 write accesses @3754969 +system.cpu7: completed 50000 read, 27533 write accesses @3759171 +system.cpu3: completed 50000 read, 27422 write accesses @3773312 +system.cpu1: completed 60000 read, 32296 write accesses @4453312 +system.cpu4: completed 60000 read, 32758 write accesses @4481325 +system.cpu5: completed 60000 read, 32870 write accesses @4492024 +system.cpu6: completed 60000 read, 32717 write accesses @4494308 +system.cpu2: completed 60000 read, 32692 write accesses @4496082 +system.cpu0: completed 60000 read, 32771 write accesses @4507003 +system.cpu3: completed 60000 read, 32841 write accesses @4507635 +system.cpu7: completed 60000 read, 32948 write accesses @4509464 +system.cpu1: completed 70000 read, 37680 write accesses @5196500 +system.cpu4: completed 70000 read, 38348 write accesses @5238038 +system.cpu6: completed 70000 read, 38163 write accesses @5248200 +system.cpu0: completed 70000 read, 38097 write accesses @5249364 +system.cpu2: completed 70000 read, 38107 write accesses @5253167 +system.cpu5: completed 70000 read, 38242 write accesses @5256208 +system.cpu3: completed 70000 read, 38223 write accesses @5263274 +system.cpu7: completed 70000 read, 38358 write accesses @5264096 +system.cpu1: completed 80000 read, 43090 write accesses @5938080 +system.cpu4: completed 80000 read, 43794 write accesses @5986228 +system.cpu2: completed 80000 read, 43534 write accesses @5995018 +system.cpu6: completed 80000 read, 43480 write accesses @5996319 +system.cpu0: completed 80000 read, 43647 write accesses @6010543 +system.cpu3: completed 80000 read, 43541 write accesses @6012821 +system.cpu5: completed 80000 read, 43618 write accesses @6013478 +system.cpu7: completed 80000 read, 43801 write accesses @6025753 +system.cpu1: completed 90000 read, 48545 write accesses @6687745 +system.cpu4: completed 90000 read, 49359 write accesses @6726890 +system.cpu5: completed 90000 read, 48916 write accesses @6741464 +system.cpu6: completed 90000 read, 49052 write accesses @6749326 +system.cpu0: completed 90000 read, 49060 write accesses @6762829 +system.cpu2: completed 90000 read, 49003 write accesses @6764022 +system.cpu3: completed 90000 read, 48925 write accesses @6765195 +system.cpu7: completed 90000 read, 49330 write accesses @6780434 +system.cpu1: completed 100000 read, 54091 write accesses @7447945 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 2a42b9411..915e01ac6 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007494 # Number of seconds simulated -sim_ticks 7493512 # Number of ticks simulated -final_tick 7493512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007448 # Number of seconds simulated +sim_ticks 7447945 # Number of ticks simulated +final_tick 7447945 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 42711 # Simulator tick rate (ticks/s) -host_mem_usage 410448 # Number of bytes of host memory used -host_seconds 175.45 # Real time elapsed on the host +host_tick_rate 25433 # Simulator tick rate (ticks/s) +host_mem_usage 418956 # Number of bytes of host memory used +host_seconds 292.84 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99629 # number of read accesses completed -system.cpu0.num_writes 53203 # number of write accesses completed +system.cpu0.num_reads 99070 # number of read accesses completed +system.cpu0.num_writes 53923 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99934 # number of read accesses completed -system.cpu1.num_writes 53556 # number of write accesses completed +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 54091 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99904 # number of read accesses completed -system.cpu2.num_writes 53683 # number of write accesses completed +system.cpu2.num_reads 99298 # number of read accesses completed +system.cpu2.num_writes 53915 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99658 # number of read accesses completed -system.cpu3.num_writes 53732 # number of write accesses completed +system.cpu3.num_reads 99379 # number of read accesses completed +system.cpu3.num_writes 53826 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 54127 # number of write accesses completed +system.cpu4.num_reads 99471 # number of read accesses completed +system.cpu4.num_writes 54600 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99924 # number of read accesses completed -system.cpu5.num_writes 53749 # number of write accesses completed +system.cpu5.num_reads 99375 # number of read accesses completed +system.cpu5.num_writes 54088 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99831 # number of read accesses completed -system.cpu6.num_writes 53726 # number of write accesses completed +system.cpu6.num_reads 99102 # number of read accesses completed +system.cpu6.num_writes 54167 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99585 # number of read accesses completed -system.cpu7.num_writes 53460 # number of write accesses completed +system.cpu7.num_reads 98852 # number of read accesses completed +system.cpu7.num_writes 54147 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index 94ef9f9e6..5242868ae 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -1,26 +1,26 @@ -Real time: Jul/10/2012 17:49:16 +Real time: Oct/08/2012 22:38:38 Profiler Stats -------------- -Elapsed_time_in_seconds: 176 -Elapsed_time_in_minutes: 2.93333 -Elapsed_time_in_hours: 0.0488889 -Elapsed_time_in_days: 0.00203704 +Elapsed_time_in_seconds: 197 +Elapsed_time_in_minutes: 3.28333 +Elapsed_time_in_hours: 0.0547222 +Elapsed_time_in_days: 0.00228009 -Virtual_time_in_seconds: 176.38 -Virtual_time_in_minutes: 2.93967 -Virtual_time_in_hours: 0.0489944 -Virtual_time_in_days: 0.00204144 +Virtual_time_in_seconds: 131.96 +Virtual_time_in_minutes: 2.19933 +Virtual_time_in_hours: 0.0366556 +Virtual_time_in_days: 0.00152731 -Ruby_current_time: 19665440 +Ruby_current_time: 6111458 Ruby_start_time: 0 -Ruby_cycles: 19665440 +Ruby_cycles: 6111458 -mbytes_resident: 59.5039 -mbytes_total: 371.051 -resident_ratio: 0.160376 +mbytes_resident: 66.5391 +mbytes_total: 409.094 +resident_ratio: 0.162659 -ruby_cycles_executed: [ 19665441 19665441 19665441 19665441 19665441 19665441 19665441 19665441 ] +ruby_cycles_executed: [ 6111459 6111459 6111459 6111459 6111459 6111459 6111459 6111459 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -31,35 +31,35 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615791 average: 15.9984 | standard deviation: 0.126916 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615671 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 613095 average: 15.9984 | standard deviation: 0.127195 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 612975 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 17950 count: 615663 average: 4087.9 | standard deviation: 2956.06 | 623 6672 13560 14818 14265 17966 19787 19525 17351 15783 16469 15505 13071 12320 10871 10722 9526 9130 8887 7565 7667 7466 7531 7035 6354 6785 6935 6505 6586 6197 6688 6288 6356 6714 5904 6537 6481 6912 6526 6034 6775 7081 6913 6760 6410 7338 6903 6984 7337 6740 7182 7215 7632 7074 6418 7159 7114 6737 6491 6024 6332 6004 5733 5688 4797 5051 4642 4682 4143 3530 3610 3411 3200 2859 2550 2444 2181 1984 1892 1560 1505 1322 1318 1079 894 847 816 664 565 542 483 377 337 330 279 261 213 201 124 131 124 110 84 81 66 54 56 46 35 30 30 26 23 19 17 15 11 7 6 5 9 9 2 2 3 2 1 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 128 max: 17950 count: 399929 average: 4087.58 | standard deviation: 2957.17 | 427 4346 8825 9550 9296 11679 12873 12593 11401 10212 10707 10147 8404 8073 7003 6964 6161 5868 5801 4897 4955 4924 4917 4586 4142 4464 4604 4193 4274 3952 4333 4116 4068 4378 3852 4207 4233 4508 4295 3961 4411 4535 4480 4361 4179 4757 4439 4506 4744 4400 4603 4692 4979 4557 4111 4623 4589 4415 4237 3907 4062 3885 3692 3767 3150 3284 2995 3038 2750 2299 2388 2194 2087 1839 1653 1583 1436 1307 1186 1037 994 869 861 691 593 539 560 428 376 343 295 247 213 228 183 160 141 135 75 92 76 69 49 47 48 30 35 26 24 18 20 18 12 17 9 11 7 7 6 4 5 8 2 2 3 2 0 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 128 max: 16140 count: 215734 average: 4088.48 | standard deviation: 2954.01 | 196 2326 4735 5268 4969 6287 6914 6932 5950 5571 5762 5358 4667 4247 3868 3758 3365 3262 3086 2668 2712 2542 2614 2449 2212 2321 2331 2312 2312 2245 2355 2172 2288 2336 2052 2330 2248 2404 2231 2073 2364 2546 2433 2399 2231 2581 2464 2478 2593 2340 2579 2523 2653 2517 2307 2536 2525 2322 2254 2117 2270 2119 2041 1921 1647 1767 1647 1644 1393 1231 1222 1217 1113 1020 897 861 745 677 706 523 511 453 457 388 301 308 256 236 189 199 188 130 124 102 96 101 72 66 49 39 48 41 35 34 18 24 21 20 11 12 10 8 11 2 8 4 4 0 0 1 4 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 160 average: 2 | standard deviation: 0 | 0 0 160 ] -miss_latency_L2Cache: [binsize: 128 max: 14287 count: 3749 average: 4006.09 | standard deviation: 3008.68 | 182 57 48 68 52 141 103 85 85 85 92 86 77 80 65 61 63 55 45 46 49 46 48 53 39 33 48 40 33 48 39 30 30 32 48 36 24 35 33 37 37 41 53 39 34 41 53 47 50 35 39 43 54 42 41 57 36 33 48 63 36 33 33 35 25 31 22 26 25 15 24 19 16 16 14 15 9 11 11 8 6 12 4 7 6 5 5 3 4 5 1 1 3 4 2 1 1 1 2 0 0 2 0 0 3 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Directory: [binsize: 128 max: 17950 count: 608537 average: 4091.83 | standard deviation: 2954.99 | 0 6545 13426 14647 14125 17700 19605 19380 17190 15625 16326 15351 12950 12192 10777 10598 9431 9049 8802 7478 7578 7387 7449 6948 6294 6721 6849 6431 6520 6110 6613 6225 6297 6648 5830 6473 6424 6847 6457 5970 6698 7009 6819 6700 6339 7258 6804 6902 7258 6665 7098 7139 7542 7010 6328 7074 7054 6671 6409 5933 6261 5945 5672 5631 4740 4993 4601 4639 4096 3494 3574 3375 3173 2833 2526 2418 2163 1954 1877 1545 1492 1309 1308 1069 886 842 809 658 559 536 482 374 334 325 277 260 210 199 121 131 124 107 84 81 63 54 56 45 35 29 29 25 23 19 17 15 11 7 6 5 9 9 2 2 3 2 1 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache_wCC: [binsize: 128 max: 13052 count: 3217 average: 3643.18 | standard deviation: 2994.23 | 281 70 86 103 88 125 79 60 76 73 51 68 44 48 29 63 32 26 40 41 40 33 34 34 21 31 38 34 33 39 36 33 29 34 26 28 33 30 36 27 40 31 41 21 37 39 46 35 29 40 45 33 36 22 49 28 24 33 34 28 35 26 28 22 32 27 19 17 22 21 12 17 11 10 10 11 9 19 4 7 7 1 6 3 2 0 2 3 2 1 0 2 0 1 0 0 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 32 max: 5200 count: 612967 average: 1276.02 | standard deviation: 879.819 | 345 167 5569 12569 12808 12397 15293 15782 14532 15221 14080 12213 12492 11485 9746 9998 9044 7841 8244 7648 6481 6892 6915 5861 6375 6095 5603 6321 5980 5313 6037 6163 5249 5759 5835 5233 5805 5703 5236 5762 5910 5254 5874 5794 5377 6025 5702 5216 5961 6121 5447 6015 5878 5580 6203 6218 5539 6412 6582 6020 6356 6370 6018 6766 6441 5778 6447 6690 5809 6302 6102 5573 5987 5753 4985 5521 5383 4531 4709 4510 4048 4242 3764 3367 3456 3314 2674 2696 2528 2235 2172 1982 1680 1619 1554 1189 1191 1105 881 895 747 646 663 607 464 448 383 366 345 265 249 210 240 163 193 157 119 117 78 71 70 67 48 56 48 37 40 29 27 22 16 15 13 14 15 9 4 6 3 7 4 4 1 6 4 7 2 4 1 3 2 2 0 3 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 5037 count: 398574 average: 1276.55 | standard deviation: 880.154 | 234 102 3672 8225 8364 8071 9931 10261 9429 9900 9128 7926 8077 7465 6358 6519 5896 4990 5314 5002 4206 4542 4515 3713 4123 3949 3638 4116 3846 3463 3855 4067 3349 3783 3725 3405 3807 3747 3392 3755 3828 3416 3852 3785 3439 3883 3665 3413 3878 4027 3609 3914 3831 3594 4006 4072 3638 4181 4290 3930 4154 4153 3905 4384 4182 3718 4175 4359 3793 4112 4016 3650 3859 3807 3220 3575 3486 2925 3088 2932 2664 2773 2472 2190 2261 2194 1718 1725 1639 1437 1425 1243 1086 1039 1018 783 766 752 574 563 465 406 438 406 285 304 258 234 231 169 170 127 168 107 136 99 82 81 51 50 42 45 35 30 29 28 21 22 20 15 12 10 6 10 10 5 2 3 2 5 4 2 0 3 4 4 1 4 0 1 0 1 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 32 max: 5200 count: 214393 average: 1275.04 | standard deviation: 879.196 | 111 65 1897 4344 4444 4326 5362 5521 5103 5321 4952 4287 4415 4020 3388 3479 3148 2851 2930 2646 2275 2350 2400 2148 2252 2146 1965 2205 2134 1850 2182 2096 1900 1976 2110 1828 1998 1956 1844 2007 2082 1838 2022 2009 1938 2142 2037 1803 2083 2094 1838 2101 2047 1986 2197 2146 1901 2231 2292 2090 2202 2217 2113 2382 2259 2060 2272 2331 2016 2190 2086 1923 2128 1946 1765 1946 1897 1606 1621 1578 1384 1469 1292 1177 1195 1120 956 971 889 798 747 739 594 580 536 406 425 353 307 332 282 240 225 201 179 144 125 132 114 96 79 83 72 56 57 58 37 36 27 21 28 22 13 26 19 9 19 7 7 7 4 5 7 4 5 4 2 3 1 2 0 2 1 3 0 3 1 0 1 2 2 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 165 average: 2 | standard deviation: 0 | 0 0 165 ] +miss_latency_L2Cache: [binsize: 32 max: 4097 count: 3396 average: 1257.08 | standard deviation: 892.965 | 76 109 66 48 37 32 26 35 52 106 96 72 59 48 67 71 49 40 36 45 37 28 27 43 40 31 29 32 31 31 30 37 30 32 33 27 29 31 29 37 29 39 29 35 32 39 31 35 34 35 31 37 28 33 31 35 41 34 27 40 33 31 31 44 38 34 31 35 32 31 22 33 25 34 24 24 25 21 18 25 19 30 29 19 13 17 19 11 14 10 17 9 15 12 9 8 5 6 7 4 3 7 5 1 3 2 3 4 1 2 3 0 2 1 0 1 1 2 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 32 max: 5200 count: 606864 average: 1276.85 | standard deviation: 879.632 | 0 0 5442 12478 12737 12341 15238 15721 14430 15046 13924 12099 12392 11390 9626 9890 8960 7771 8178 7564 6410 6836 6859 5783 6304 6038 5534 6259 5924 5262 5985 6095 5198 5703 5786 5177 5751 5647 5187 5696 5861 5188 5819 5737 5325 5960 5640 5160 5906 6063 5399 5954 5823 5524 6144 6167 5479 6350 6527 5952 6300 6312 5970 6698 6375 5728 6394 6633 5751 6247 6055 5519 5941 5697 4940 5472 5336 4490 4680 4476 4014 4195 3722 3339 3428 3284 2645 2674 2499 2216 2148 1966 1660 1606 1541 1175 1184 1096 872 888 740 636 655 605 460 445 379 362 344 260 245 210 238 162 192 155 118 114 78 70 70 67 48 56 48 37 40 29 26 22 16 15 12 14 15 9 4 6 3 7 4 4 1 6 4 7 2 4 1 3 2 2 0 3 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 32 max: 4240 count: 2542 average: 1187.17 | standard deviation: 870.908 | 104 58 61 43 34 24 29 26 50 69 60 42 41 47 53 37 35 30 30 39 34 28 29 35 31 26 40 30 25 20 22 31 21 24 16 29 25 25 20 29 20 27 26 22 20 26 31 21 21 23 17 24 27 23 28 16 19 28 28 28 23 27 17 24 28 16 22 22 26 24 25 21 21 22 21 25 22 20 11 9 15 17 13 9 15 13 10 11 15 9 7 7 5 1 4 6 2 3 2 3 4 3 3 1 1 1 1 0 0 3 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_wCC_Times: 3217 +imcomplete_wCC_Times: 2542 miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ] -miss_latency_dir_first_response_to_completion: [binsize: 4 max: 559 count: 7 average: 349 | standard deviation: 173.877 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -imcomplete_dir_Times: 608530 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 104 average: 2 | standard deviation: 0 | 0 0 104 ] -miss_latency_LD_L2Cache: [binsize: 128 max: 14136 count: 2421 average: 3972.56 | standard deviation: 2987.64 | 126 34 28 45 27 90 74 53 57 58 58 58 52 47 37 42 41 39 30 31 32 26 30 28 29 21 35 24 21 35 31 17 20 20 34 21 14 26 23 21 24 32 30 26 21 27 35 29 25 24 24 29 35 24 25 40 26 16 31 42 25 17 24 26 17 23 12 16 13 8 15 14 10 10 7 10 6 8 7 6 5 7 2 1 4 4 3 2 1 4 0 0 2 3 1 0 0 1 1 0 0 1 0 0 2 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_Directory: [binsize: 128 max: 17950 count: 395321 average: 4091.73 | standard deviation: 2956.13 | 0 4268 8739 9438 9215 11511 12748 12502 11295 10108 10609 10045 8324 7999 6946 6889 6101 5816 5746 4843 4896 4877 4863 4536 4101 4421 4544 4145 4236 3888 4283 4080 4032 4335 3797 4165 4196 4464 4244 3919 4359 4483 4421 4323 4131 4704 4374 4456 4701 4351 4553 4645 4920 4520 4057 4569 4546 4379 4184 3847 4019 3852 3648 3726 3116 3245 2966 3012 2721 2278 2364 2167 2067 1823 1637 1567 1424 1288 1179 1025 984 861 855 688 587 535 555 424 373 338 295 245 211 225 182 160 139 134 73 92 76 68 49 47 46 30 35 25 24 17 19 18 12 17 9 11 7 7 6 4 5 8 2 2 3 2 0 1 0 1 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 12658 count: 2083 average: 3638.66 | standard deviation: 3014.99 | 138 59 33 11 24 34 33 34 35 19 40 38 20 31 19 19 26 23 22 24 20 20 19 25 12 16 19 8 13 7 21 12 14 5 8 5 12 13 13 10 12 15 9 12 12 12 13 9 5 7 10 12 9 16 9 15 9 8 18 11 10 9 8 11 9 7 15 8 10 11 15 6 13 10 9 9 13 15 10 11 14 14 6 14 11 18 4 8 12 15 15 11 23 7 10 11 7 11 12 13 14 12 9 9 10 14 6 7 15 14 9 5 9 8 6 14 11 11 10 8 10 8 8 8 10 10 4 11 7 10 9 7 6 11 4 6 8 8 10 3 5 4 3 10 4 6 3 3 4 5 4 2 2 4 5 6 0 0 2 4 3 2 0 1 3 1 0 2 0 2 0 0 0 2 0 2 0 2 1 0 0 0 0 2 0 0 0 0 0 0 0 0 1 1 0 0 0 1 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 56 average: 2 | standard deviation: 0 | 0 0 56 ] -miss_latency_ST_L2Cache: [binsize: 128 max: 14287 count: 1328 average: 4067.22 | standard deviation: 3046.85 | 56 23 20 23 25 51 29 32 28 27 34 28 25 33 28 19 22 16 15 15 17 20 18 25 10 12 13 16 12 13 8 13 10 12 14 15 10 9 10 16 13 9 23 13 13 14 18 18 25 11 15 14 19 18 16 17 10 17 17 21 11 16 9 9 8 8 10 10 12 7 9 5 6 6 7 5 3 3 4 2 1 5 2 6 2 1 2 1 3 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_Directory: [binsize: 128 max: 16140 count: 213216 average: 4092.01 | standard deviation: 2952.9 | 0 2277 4687 5209 4910 6189 6857 6878 5895 5517 5717 5306 4626 4193 3831 3709 3330 3233 3056 2635 2682 2510 2586 2412 2193 2300 2305 2286 2284 2222 2330 2145 2265 2313 2033 2308 2228 2383 2213 2051 2339 2526 2398 2377 2208 2554 2430 2446 2557 2314 2545 2494 2622 2490 2271 2505 2508 2292 2225 2086 2242 2093 2024 1905 1624 1748 1635 1627 1375 1216 1210 1208 1106 1010 889 851 739 666 698 520 508 448 453 381 299 307 254 234 186 198 187 129 123 100 95 100 71 65 48 39 48 39 35 34 17 24 21 20 11 12 10 7 11 2 8 4 4 0 0 1 4 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 13052 count: 1134 average: 3651.49 | standard deviation: 2957.03 | 84 26 28 36 34 47 28 22 27 27 11 24 16 21 9 30 13 13 15 18 13 12 10 12 9 9 13 10 16 10 17 14 13 11 5 7 10 12 8 6 12 11 12 9 10 13 16 14 11 15 19 15 12 9 20 14 7 13 12 10 17 10 8 7 15 11 2 7 6 8 3 4 1 4 1 5 3 8 4 1 2 0 2 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 184 count: 7 average: 122.714 | standard deviation: 50.5833 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 606857 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 112 average: 2 | standard deviation: 0 | 0 0 112 ] +miss_latency_LD_L2Cache: [binsize: 32 max: 4097 count: 2198 average: 1266.23 | standard deviation: 900.086 | 56 72 46 34 22 19 12 24 31 69 60 45 37 31 44 42 30 27 25 30 20 13 17 29 29 21 18 19 21 25 17 25 21 19 21 16 19 17 18 25 18 24 23 21 17 22 22 26 18 18 22 22 16 19 14 26 26 23 19 30 19 23 16 31 26 27 23 24 19 20 18 20 17 21 12 15 20 12 12 21 16 17 21 10 7 14 12 6 10 7 13 5 15 8 7 4 2 4 5 4 2 1 3 0 2 2 2 1 1 1 1 0 2 0 0 1 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 32 max: 5037 count: 394663 average: 1277.34 | standard deviation: 879.942 | 0 0 3583 8165 8320 8031 9900 10221 9361 9784 9028 7859 8015 7404 6283 6453 5846 4949 5276 4949 4164 4514 4480 3665 4071 3910 3599 4079 3808 3427 3820 4020 3317 3753 3695 3373 3767 3712 3355 3716 3799 3373 3813 3754 3407 3842 3620 3374 3844 3997 3576 3878 3797 3562 3975 4035 3602 4138 4249 3879 4123 4111 3876 4340 4136 3683 4136 4321 3761 4073 3979 3620 3831 3768 3195 3547 3456 2905 3072 2903 2638 2744 2442 2172 2244 2172 1701 1715 1620 1424 1408 1235 1068 1030 1009 775 762 746 568 558 460 402 432 406 282 302 255 233 230 166 169 127 166 107 136 97 81 78 51 50 42 45 35 30 29 28 21 22 19 15 12 10 6 10 10 5 2 3 2 5 4 2 0 3 4 4 1 4 0 1 0 1 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 3748 count: 1601 average: 1185.29 | standard deviation: 866.448 | 66 30 43 26 22 21 19 16 37 47 40 22 25 30 31 24 20 14 13 23 22 15 18 19 23 18 21 18 17 11 18 22 11 11 9 16 21 18 19 14 11 19 16 10 15 19 23 13 16 12 11 14 18 13 17 11 10 20 22 21 12 19 13 13 20 8 16 14 13 19 19 10 11 18 13 13 10 8 4 8 10 12 9 8 10 8 5 4 9 6 4 3 3 1 2 4 2 2 1 1 3 3 3 0 1 0 1 0 0 2 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 53 average: 2 | standard deviation: 0 | 0 0 53 ] +miss_latency_ST_L2Cache: [binsize: 32 max: 3839 count: 1198 average: 1240.29 | standard deviation: 879.874 | 20 37 20 14 15 13 14 11 21 37 36 27 22 17 23 29 19 13 11 15 17 15 10 14 11 10 11 13 10 6 13 12 9 13 12 11 10 14 11 12 11 15 6 14 15 17 9 9 16 17 9 15 12 14 17 9 15 11 8 10 14 8 15 13 12 7 8 11 13 11 4 13 8 13 12 9 5 9 6 4 3 13 8 9 6 3 7 5 4 3 4 4 0 4 2 4 3 2 2 0 1 6 2 1 1 0 1 3 0 1 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 32 max: 5200 count: 212201 average: 1275.93 | standard deviation: 879.054 | 0 0 1859 4313 4417 4310 5338 5500 5069 5262 4896 4240 4377 3986 3343 3437 3114 2822 2902 2615 2246 2322 2379 2118 2233 2128 1935 2180 2116 1835 2165 2075 1881 1950 2091 1804 1984 1935 1832 1980 2062 1815 2006 1983 1918 2118 2020 1786 2062 2066 1823 2076 2026 1962 2169 2132 1877 2212 2278 2073 2177 2201 2094 2358 2239 2045 2258 2312 1990 2174 2076 1899 2110 1929 1745 1925 1880 1585 1608 1573 1376 1451 1280 1167 1184 1112 944 959 879 792 740 731 592 576 532 400 422 350 304 330 280 234 223 199 178 143 124 129 114 94 76 83 72 55 56 58 37 36 27 20 28 22 13 26 19 9 19 7 7 7 4 5 6 4 5 4 2 3 1 2 0 2 1 3 0 3 1 0 1 2 2 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 4240 count: 941 average: 1190.36 | standard deviation: 878.898 | 38 28 18 17 12 3 10 10 13 22 20 20 16 17 22 13 15 16 17 16 12 13 11 16 8 8 19 12 8 9 4 9 10 13 7 13 4 7 1 15 9 8 10 12 5 7 8 8 5 11 6 10 9 10 11 5 9 8 6 7 11 8 4 11 8 8 6 8 13 5 6 11 10 4 8 12 12 12 7 1 5 5 4 1 5 5 5 7 6 3 3 4 2 0 2 2 0 1 1 2 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -89,301 +89,316 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 176 +user_time: 131 system_time: 0 -page_reclaims: 16412 -page_faults: 0 +page_reclaims: 18250 +page_faults: 3 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 56 +block_outputs: 296 Network Stats ------------- -total_msg_count_Request_Control: 3688605 29508840 -total_msg_count_Response_Data: 1832376 131931072 -total_msg_count_ResponseL2hit_Data: 4557 328104 -total_msg_count_ResponseLocal_Data: 6807 490104 -total_msg_count_Response_Control: 5775 46200 -total_msg_count_Writeback_Data: 2490786 179336592 -total_msg_count_Writeback_Control: 1183890 9471120 -total_msg_count_Broadcast_Control: 9232905 73863240 -total_msg_count_Persistent_Control: 8183920 65471360 -total_msgs: 26629621 total_bytes: 490446632 +total_msg_count_Request_Control: 3671934 29375472 +total_msg_count_Response_Data: 1826802 131529744 +total_msg_count_ResponseL2hit_Data: 5034 362448 +total_msg_count_ResponseLocal_Data: 4665 335880 +total_msg_count_Response_Control: 4206 33648 +total_msg_count_Writeback_Data: 2626131 189081432 +total_msg_count_Writeback_Control: 1125534 9004272 +total_msg_count_Broadcast_Control: 9192345 73538760 +total_msg_count_Persistent_Control: 5159900 41279200 +total_msgs: 23616551 total_bytes: 474540856 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 3.24081 - links_utilized_percent_switch_0_link_0: 4.18124 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 2.30038 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 76922 5538384 [ 0 0 0 0 76922 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 186 13392 [ 0 0 0 0 186 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 277 19944 [ 0 0 0 0 277 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Data: 80 5760 [ 0 0 0 0 80 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Broadcast_Control: 538135 4305080 [ 0 538135 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 77392 619136 [ 0 77392 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 281 20232 [ 0 0 0 0 281 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 254 2032 [ 0 0 0 0 254 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 77209 5559048 [ 0 0 0 0 77209 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Broadcast_Control: 77392 619136 [ 0 77392 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 51231 409848 [ 0 0 0 51231 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 9.95537 + links_utilized_percent_switch_0_link_0: 12.4393 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 7.47147 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 76327 5495544 [ 0 0 0 0 76327 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 227 16344 [ 0 0 0 0 227 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 188 13536 [ 0 0 0 0 188 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 3967 285624 [ 0 0 0 0 3967 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 536064 4288512 [ 0 536064 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 76759 614072 [ 0 76759 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 86 6192 [ 0 0 0 0 86 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 208 14976 [ 0 0 0 0 208 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 184 1472 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 80520 5797440 [ 0 0 0 0 80520 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Broadcast_Control: 76759 614072 [ 0 76759 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 32186 257488 [ 0 0 0 32186 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 3.23201 - links_utilized_percent_switch_1_link_0: 4.17377 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 2.29025 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 187 13464 [ 0 0 0 0 187 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 309 22248 [ 0 0 0 0 309 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Broadcast_Control: 538503 4308024 [ 0 538503 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 77024 616192 [ 0 77024 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 122 8784 [ 0 0 0 0 122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 253 2024 [ 0 0 0 0 253 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 76843 5532696 [ 0 0 0 0 76843 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Broadcast_Control: 77024 616192 [ 0 77024 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Persistent_Control: 51043 408344 [ 0 0 0 51043 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 9.94302 + links_utilized_percent_switch_1_link_0: 12.4261 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 7.45997 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 76349 5497128 [ 0 0 0 0 76349 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 194 13968 [ 0 0 0 0 194 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 3794 273168 [ 0 0 0 0 3794 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 536034 4288272 [ 0 536034 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 76789 614312 [ 0 76789 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 106 7632 [ 0 0 0 0 106 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 174 12528 [ 0 0 0 0 174 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 168 1344 [ 0 0 0 0 168 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 80362 5786064 [ 0 0 0 0 80362 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Broadcast_Control: 76789 614312 [ 0 76789 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Persistent_Control: 32302 258416 [ 0 0 0 32302 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 3.22381 - links_utilized_percent_switch_2_link_0: 4.16688 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.28074 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 76167 5484024 [ 0 0 0 0 76167 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 178 12816 [ 0 0 0 0 178 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 282 20304 [ 0 0 0 0 282 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 133 9576 [ 0 0 0 0 133 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Broadcast_Control: 538834 4310672 [ 0 538834 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 76693 613544 [ 0 76693 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 129 9288 [ 0 0 0 0 129 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 299 21528 [ 0 0 0 0 299 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 255 2040 [ 0 0 0 0 255 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 76504 5508288 [ 0 0 0 0 76504 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Broadcast_Control: 76693 613544 [ 0 76693 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Persistent_Control: 51008 408064 [ 0 0 0 51008 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 9.93331 + links_utilized_percent_switch_2_link_0: 12.4175 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 7.44909 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 76117 5480424 [ 0 0 0 0 76117 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 195 14040 [ 0 0 0 0 195 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 209 15048 [ 0 0 0 0 209 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 3872 278784 [ 0 0 0 0 3872 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 536250 4290000 [ 0 536250 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 76573 612584 [ 0 76573 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 107 7704 [ 0 0 0 0 107 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseL2hit_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 192 13824 [ 0 0 0 0 192 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 176 1408 [ 0 0 0 0 176 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 80210 5775120 [ 0 0 0 0 80210 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Broadcast_Control: 76573 612584 [ 0 76573 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Persistent_Control: 32584 260672 [ 0 0 0 32584 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 3.2261 - links_utilized_percent_switch_3_link_0: 4.16925 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 2.28295 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 76263 5490936 [ 0 0 0 0 76263 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 190 13680 [ 0 0 0 0 190 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 283 20376 [ 0 0 0 0 283 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Data: 142 10224 [ 0 0 0 0 142 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Broadcast_Control: 538706 4309648 [ 0 538706 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 76821 614568 [ 0 76821 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 118 8496 [ 0 0 0 0 118 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 279 20088 [ 0 0 0 0 279 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 244 1952 [ 0 0 0 0 244 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 76634 5517648 [ 0 0 0 0 76634 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Broadcast_Control: 76821 614568 [ 0 76821 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 50741 405928 [ 0 0 0 50741 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 9.90406 + links_utilized_percent_switch_3_link_0: 12.3939 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 7.41425 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 75828 5459616 [ 0 0 0 0 75828 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 213 15336 [ 0 0 0 0 213 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 174 12528 [ 0 0 0 0 174 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 3826 275472 [ 0 0 0 0 3826 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 536530 4292240 [ 0 536530 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 76293 610344 [ 0 76293 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 112 8064 [ 0 0 0 0 112 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 205 14760 [ 0 0 0 0 205 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 181 1448 [ 0 0 0 0 181 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 79856 5749632 [ 0 0 0 0 79856 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Broadcast_Control: 76293 610344 [ 0 76293 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 31913 255304 [ 0 0 0 31913 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 3.22416 - links_utilized_percent_switch_4_link_0: 4.16711 bw: 16000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 2.28121 bw: 16000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Response_Data: 76124 5480928 [ 0 0 0 0 76124 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 189 13608 [ 0 0 0 0 189 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 255 18360 [ 0 0 0 0 255 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Data: 203 14616 [ 0 0 0 0 203 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Broadcast_Control: 538827 4310616 [ 0 538827 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 76700 613600 [ 0 76700 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 121 8712 [ 0 0 0 0 121 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 298 21456 [ 0 0 0 0 298 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 241 1928 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Data: 76528 5510016 [ 0 0 0 0 76528 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Broadcast_Control: 76700 613600 [ 0 76700 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Persistent_Control: 51053 408424 [ 0 0 0 51053 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 9.91583 + links_utilized_percent_switch_4_link_0: 12.4032 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 7.42849 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Response_Data: 75911 5465592 [ 0 0 0 0 75911 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 221 15912 [ 0 0 0 0 221 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 206 14832 [ 0 0 0 0 206 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Data: 3845 276840 [ 0 0 0 0 3845 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 536384 4291072 [ 0 536384 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 76439 611512 [ 0 76439 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 105 7560 [ 0 0 0 0 105 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseL2hit_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 189 13608 [ 0 0 0 0 189 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 171 1368 [ 0 0 0 0 171 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 80008 5760576 [ 0 0 0 0 80008 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Broadcast_Control: 76439 611512 [ 0 76439 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Persistent_Control: 32202 257616 [ 0 0 0 32202 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 3.22862 - links_utilized_percent_switch_5_link_0: 4.17097 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 2.28627 bw: 16000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Response_Data: 76217 5487624 [ 0 0 0 0 76217 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Data: 235 16920 [ 0 0 0 0 235 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Broadcast_Control: 538633 4309064 [ 0 538633 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 76894 615152 [ 0 76894 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 119 8568 [ 0 0 0 0 119 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 270 19440 [ 0 0 0 0 270 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 227 1816 [ 0 0 0 0 227 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Data: 76732 5524704 [ 0 0 0 0 76732 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Broadcast_Control: 76894 615152 [ 0 76894 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Persistent_Control: 51107 408856 [ 0 0 0 51107 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 9.9444 + links_utilized_percent_switch_5_link_0: 12.4262 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 7.46258 bw: 16000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Response_Data: 76240 5489280 [ 0 0 0 0 76240 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 221 15912 [ 0 0 0 0 221 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 192 13824 [ 0 0 0 0 192 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Data: 3879 279288 [ 0 0 0 0 3879 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 536061 4288488 [ 0 536061 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 76762 614096 [ 0 76762 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 111 7992 [ 0 0 0 0 111 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseL2hit_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 205 14760 [ 0 0 0 0 205 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 165 1320 [ 0 0 0 0 165 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 80360 5785920 [ 0 0 0 0 80360 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Broadcast_Control: 76762 614096 [ 0 76762 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Persistent_Control: 32354 258832 [ 0 0 0 32354 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 3.23111 - links_utilized_percent_switch_6_link_0: 4.17316 bw: 16000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 2.28907 bw: 16000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Response_Data: 76312 5494464 [ 0 0 0 0 76312 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 256 18432 [ 0 0 0 0 256 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Broadcast_Control: 538539 4308312 [ 0 538539 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 76988 615904 [ 0 76988 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 107 7704 [ 0 0 0 0 107 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 218 1744 [ 0 0 0 0 218 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Data: 76849 5533128 [ 0 0 0 0 76849 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Broadcast_Control: 76988 615904 [ 0 76988 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Persistent_Control: 51127 409016 [ 0 0 0 51127 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 9.94758 + links_utilized_percent_switch_6_link_0: 12.4303 bw: 16000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 7.4649 bw: 16000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Response_Data: 76309 5494248 [ 0 0 0 0 76309 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 185 13320 [ 0 0 0 0 185 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Data: 3913 281736 [ 0 0 0 0 3913 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 536022 4288176 [ 0 536022 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 76801 614408 [ 0 76801 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 112 8064 [ 0 0 0 0 112 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseL2hit_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 175 12600 [ 0 0 0 0 175 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 161 1288 [ 0 0 0 0 161 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 80428 5790816 [ 0 0 0 0 80428 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Broadcast_Control: 76801 614408 [ 0 76801 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Persistent_Control: 32222 257776 [ 0 0 0 32222 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 3.23256 - links_utilized_percent_switch_7_link_0: 4.17354 bw: 16000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 2.29158 bw: 16000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Response_Data: 76311 5494392 [ 0 0 0 0 76311 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 193 13896 [ 0 0 0 0 193 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 296 21312 [ 0 0 0 0 296 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Broadcast_Control: 538512 4308096 [ 0 538512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 77015 616120 [ 0 77015 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 111 7992 [ 0 0 0 0 111 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 272 19584 [ 0 0 0 0 272 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 231 1848 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Data: 76856 5533632 [ 0 0 0 0 76856 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Broadcast_Control: 77015 616120 [ 0 77015 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Persistent_Control: 51886 415088 [ 0 0 0 51886 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 9.91745 + links_utilized_percent_switch_7_link_0: 12.4048 bw: 16000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 7.43007 bw: 16000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Response_Data: 75830 5459760 [ 0 0 0 0 75830 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 214 15408 [ 0 0 0 0 214 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 207 14904 [ 0 0 0 0 207 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Data: 3951 284472 [ 0 0 0 0 3951 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 536416 4291328 [ 0 536416 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 76407 611256 [ 0 76407 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 110 7920 [ 0 0 0 0 110 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 207 14904 [ 0 0 0 0 207 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 191 1528 [ 0 0 0 0 191 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 80009 5760648 [ 0 0 0 0 80009 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Broadcast_Control: 76407 611256 [ 0 76407 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Persistent_Control: 32232 257856 [ 0 0 0 32232 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 12.1124 - links_utilized_percent_switch_8_link_0: 16.6506 bw: 16000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 7.57426 bw: 16000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Request_Control: 615527 4924216 [ 0 615527 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 1919 15352 [ 0 0 0 0 1919 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Data: 613576 44177472 [ 0 0 0 0 613576 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 614008 4912064 [ 0 0 614008 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 1331 95832 [ 0 0 0 0 1331 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 1519 109368 [ 0 0 0 0 1519 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Data: 216082 15557904 [ 0 0 0 0 216082 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 394626 3157008 [ 0 0 0 0 394626 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 38.8192 + links_utilized_percent_switch_8_link_0: 52.1552 bw: 16000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 25.4831 bw: 16000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 612823 4902584 [ 0 612823 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 1381 11048 [ 0 0 0 0 1381 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 611410 44021520 [ 0 0 0 0 611410 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 611155 4889240 [ 0 0 611155 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 1307 94104 [ 0 0 0 0 1307 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 1671 120312 [ 0 0 0 0 1671 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Data: 233516 16813152 [ 0 0 0 0 233516 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 375178 3001424 [ 0 0 0 0 375178 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 11.2269 - links_utilized_percent_switch_9_link_0: 8.52878 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 13.9251 bw: 16000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Request_Control: 614008 4912064 [ 0 0 614008 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Data: 215179 15492888 [ 0 0 0 0 215179 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 394628 3157024 [ 0 0 0 0 394628 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 608514 43813008 [ 0 0 0 0 608514 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Data: 25 1800 [ 0 0 0 0 25 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 36.0096 + links_utilized_percent_switch_9_link_0: 27.3329 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 44.6864 bw: 16000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 611155 4889240 [ 0 0 611155 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_ResponseL2hit_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Data: 232920 16770240 [ 0 0 0 0 232920 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 375178 3001424 [ 0 0 0 0 375178 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 606778 43688016 [ 0 0 0 0 606778 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Data: 108 7776 [ 0 0 0 0 108 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 5.75149 - links_utilized_percent_switch_10_link_0: 4.05098 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 4.04399 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 4.03719 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 4.04024 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 4.03732 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 4.04103 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 4.04317 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 4.04162 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 16.6506 bw: 16000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 8.52878 bw: 16000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Response_Data: 76922 5538384 [ 0 0 0 0 76922 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 186 13392 [ 0 0 0 0 186 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 277 19944 [ 0 0 0 0 277 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Data: 80 5760 [ 0 0 0 0 80 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Broadcast_Control: 538135 4305080 [ 0 538135 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Persistent_Control: 357965 2863720 [ 0 0 0 357965 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 187 13464 [ 0 0 0 0 187 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 309 22248 [ 0 0 0 0 309 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Broadcast_Control: 538503 4308024 [ 0 538503 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Persistent_Control: 358153 2865224 [ 0 0 0 358153 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 76167 5484024 [ 0 0 0 0 76167 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 178 12816 [ 0 0 0 0 178 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 282 20304 [ 0 0 0 0 282 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Writeback_Data: 133 9576 [ 0 0 0 0 133 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Broadcast_Control: 538834 4310672 [ 0 538834 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Persistent_Control: 358188 2865504 [ 0 0 0 358188 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 76263 5490936 [ 0 0 0 0 76263 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 190 13680 [ 0 0 0 0 190 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 283 20376 [ 0 0 0 0 283 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Writeback_Data: 142 10224 [ 0 0 0 0 142 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Broadcast_Control: 538706 4309648 [ 0 538706 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Persistent_Control: 358455 2867640 [ 0 0 0 358455 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 76124 5480928 [ 0 0 0 0 76124 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 189 13608 [ 0 0 0 0 189 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 255 18360 [ 0 0 0 0 255 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Data: 203 14616 [ 0 0 0 0 203 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Broadcast_Control: 538827 4310616 [ 0 538827 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Persistent_Control: 358143 2865144 [ 0 0 0 358143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 76217 5487624 [ 0 0 0 0 76217 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Writeback_Data: 235 16920 [ 0 0 0 0 235 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Broadcast_Control: 538633 4309064 [ 0 538633 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Persistent_Control: 358089 2864712 [ 0 0 0 358089 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 76312 5494464 [ 0 0 0 0 76312 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 198 14256 [ 0 0 0 0 198 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 256 18432 [ 0 0 0 0 256 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Writeback_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Broadcast_Control: 538539 4308312 [ 0 538539 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Persistent_Control: 358069 2864552 [ 0 0 0 358069 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 76311 5494392 [ 0 0 0 0 76311 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 193 13896 [ 0 0 0 0 193 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 296 21312 [ 0 0 0 0 296 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Writeback_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Broadcast_Control: 538512 4308096 [ 0 538512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Persistent_Control: 357310 2858480 [ 0 0 0 357310 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 615527 4924216 [ 0 615527 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 1919 15352 [ 0 0 0 0 1919 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Writeback_Data: 613576 44177472 [ 0 0 0 0 613576 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Request_Control: 614008 4912064 [ 0 0 614008 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Writeback_Data: 215179 15492888 [ 0 0 0 0 215179 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Writeback_Control: 394628 3157024 [ 0 0 0 0 394628 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Persistent_Control: 409196 3273568 [ 0 0 0 409196 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 17.6719 + links_utilized_percent_switch_10_link_0: 12.1759 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 12.1618 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 12.151 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 12.1328 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 12.1397 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 12.1615 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 12.1666 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 12.1411 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 52.1552 bw: 16000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 27.3329 bw: 16000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Response_Data: 76327 5495544 [ 0 0 0 0 76327 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 227 16344 [ 0 0 0 0 227 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 188 13536 [ 0 0 0 0 188 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Data: 3967 285624 [ 0 0 0 0 3967 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Broadcast_Control: 536064 4288512 [ 0 536064 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Persistent_Control: 225809 1806472 [ 0 0 0 225809 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 76349 5497128 [ 0 0 0 0 76349 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 194 13968 [ 0 0 0 0 194 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Data: 3794 273168 [ 0 0 0 0 3794 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Broadcast_Control: 536034 4288272 [ 0 536034 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Persistent_Control: 225693 1805544 [ 0 0 0 225693 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 76117 5480424 [ 0 0 0 0 76117 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 195 14040 [ 0 0 0 0 195 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 209 15048 [ 0 0 0 0 209 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Data: 3872 278784 [ 0 0 0 0 3872 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Broadcast_Control: 536250 4290000 [ 0 536250 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Persistent_Control: 225411 1803288 [ 0 0 0 225411 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 75828 5459616 [ 0 0 0 0 75828 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 213 15336 [ 0 0 0 0 213 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 174 12528 [ 0 0 0 0 174 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Data: 3826 275472 [ 0 0 0 0 3826 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Broadcast_Control: 536530 4292240 [ 0 536530 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Persistent_Control: 226082 1808656 [ 0 0 0 226082 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 75911 5465592 [ 0 0 0 0 75911 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 221 15912 [ 0 0 0 0 221 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 206 14832 [ 0 0 0 0 206 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Data: 3845 276840 [ 0 0 0 0 3845 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Broadcast_Control: 536384 4291072 [ 0 536384 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Persistent_Control: 225793 1806344 [ 0 0 0 225793 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 76240 5489280 [ 0 0 0 0 76240 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 221 15912 [ 0 0 0 0 221 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 192 13824 [ 0 0 0 0 192 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Data: 3879 279288 [ 0 0 0 0 3879 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Broadcast_Control: 536061 4288488 [ 0 536061 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Persistent_Control: 225641 1805128 [ 0 0 0 225641 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 76309 5494248 [ 0 0 0 0 76309 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 185 13320 [ 0 0 0 0 185 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Data: 3913 281736 [ 0 0 0 0 3913 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Broadcast_Control: 536022 4288176 [ 0 536022 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Persistent_Control: 225773 1806184 [ 0 0 0 225773 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 75830 5459760 [ 0 0 0 0 75830 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 214 15408 [ 0 0 0 0 214 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 207 14904 [ 0 0 0 0 207 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Data: 3951 284472 [ 0 0 0 0 3951 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Broadcast_Control: 536416 4291328 [ 0 536416 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Persistent_Control: 225763 1806104 [ 0 0 0 225763 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 612823 4902584 [ 0 612823 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 1381 11048 [ 0 0 0 0 1381 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Data: 611410 44021520 [ 0 0 0 0 611410 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Request_Control: 611155 4889240 [ 0 0 611155 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_ResponseL2hit_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Data: 232920 16770240 [ 0 0 0 0 232920 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Control: 375178 3001424 [ 0 0 0 0 375178 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Persistent_Control: 257995 2063960 [ 0 0 0 257995 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -394,203 +409,203 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 77392 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77392 + system.l1_cntrl0.L1DcacheMemory_total_misses: 76759 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76759 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.7535% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.2465% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.1168% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.8832% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 77392 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 76759 100% --- L1Cache --- - Event Counts - -Load [50067 49857 50011 50121 50120 50072 49850 49845 ] 399943 +Load [49698 49953 49812 49677 49996 49671 49941 49842 ] 398590 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26650 27053 27004 26916 27282 26976 26863 27000 ] 215744 +Store [26761 26834 27008 26751 26787 27135 26649 26474 ] 214399 Atomic [0 0 0 0 0 0 0 0 ] 0 -L1_Replacement [1283063 1285718 1284830 1287683 1292303 1287314 1281727 1284342 ] 10286980 -Data_Shared [248 259 233 244 221 248 232 234 ] 1919 -Data_Owner [38 49 40 55 56 61 50 38 ] 387 -Data_All_Tokens [76485 76653 76794 76788 77188 76789 76478 76606 ] 613781 -Ack [3 1 2 0 1 0 0 0 ] 7 -Ack_All_Tokens [0 0 1 0 0 0 0 0 ] 1 +L1_Replacement [1353719 1357069 1359945 1351684 1358948 1359334 1354916 1349659 ] 10845274 +Data_Shared [240 230 201 231 235 219 236 209 ] 1801 +Data_Owner [69 66 41 52 73 74 51 49 ] 475 +Data_All_Tokens [79874 80236 80349 79919 80401 80240 80106 79783 ] 640908 +Ack [3 2 4 1 1 0 3 0 ] 14 +Ack_All_Tokens [1 0 0 1 1 1 0 1 ] 5 Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETX [189041 188639 188690 188780 188410 188723 188833 188700 ] 1509816 +Transient_Local_GETX [187591 187523 187342 187600 187570 187216 187703 187877 ] 1500422 Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETS [349784 349993 349848 349731 349725 349779 350000 350006 ] 2798866 +Transient_Local_GETS [348793 348537 348680 348815 348492 348818 348546 348649 ] 2789330 Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETS_Last_Token [2 1 1 1 0 1 1 0 ] 7 -Persistent_GETX [63219 62991 63051 63029 63043 63030 63120 63186 ] 504669 -Persistent_GETS [116839 117030 116963 116632 116869 116995 116945 117021 ] 935294 -Persistent_GETS_Last_Token [0 1 0 0 1 0 1 0 ] 3 -Own_Lock_or_Unlock [229138 229174 229182 229535 229283 229171 229130 228989 ] 1833602 -Request_Timeout [493475 496675 494238 497044 493350 493296 492735 489501 ] 3950314 -Use_TimeoutStarverX [9 11 10 5 3 3 5 4 ] 50 -Use_TimeoutStarverS [14 12 13 14 1 7 20 7 ] 88 -Use_TimeoutNoStarvers [76389 76563 76693 76698 77115 76714 76389 76537 ] 613098 +Transient_Local_GETS_Last_Token [0 1 0 1 2 0 1 4 ] 9 +Persistent_GETX [39961 40047 40050 40024 39966 39968 39963 40176 ] 320155 +Persistent_GETS [73587 73442 73539 73544 73557 73492 73378 73509 ] 588048 +Persistent_GETS_Last_Token [1 0 0 0 0 0 1 1 ] 3 +Own_Lock_or_Unlock [144446 144506 144406 144427 144472 144535 144653 144309 ] 1155754 +Request_Timeout [59625 60184 59615 58605 59767 59230 59835 60464 ] 477325 +Use_TimeoutStarverX [13 10 17 16 5 4 12 11 ] 88 +Use_TimeoutStarverS [14 25 24 25 5 14 16 13 ] 136 +Use_TimeoutNoStarvers [76127 76451 76532 76100 76475 76497 76273 76023 ] 610478 Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load [49951 49739 49879 49987 50006 49959 49727 49727 ] 398975 +NP Load [49602 49873 49730 49574 49901 49582 49849 49761 ] 397872 NP Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP Store [26591 26993 26943 26840 27222 26901 26786 26933 ] 215209 +NP Store [26718 26789 26963 26717 26735 27097 26587 26434 ] 214040 NP Atomic [0 0 0 0 0 0 0 0 ] 0 -NP Data_Shared [0 0 0 0 0 0 0 0 ] 0 -NP Data_Owner [1 3 3 4 5 11 6 2 ] 35 -NP Data_All_Tokens [71 66 79 71 68 65 64 58 ] 542 -NP Ack [2 0 0 0 0 0 0 0 ] 2 +NP Data_Shared [10 6 6 5 15 7 5 4 ] 58 +NP Data_Owner [17 16 11 12 21 15 12 10 ] 114 +NP Data_All_Tokens [3701 3741 3769 3774 3875 3680 3781 3718 ] 30039 +NP Ack [0 0 1 0 0 0 1 0 ] 2 NP Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -NP Transient_Local_GETX [188319 187906 187930 188079 187687 187997 188114 188005 ] 1504037 +NP Transient_Local_GETX [186999 186907 186760 186962 186964 186616 187124 187265 ] 1495597 NP Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -NP Transient_Local_GETS [348384 348668 348524 348411 348418 348421 348646 348662 ] 2788134 +NP Transient_Local_GETS [347673 347393 347532 347735 347394 347712 347415 347504 ] 2780358 NP Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 NP Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 NP Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -NP Own_Lock_or_Unlock [198434 198575 198742 198423 198646 198582 198558 198633 ] 1588593 +NP Own_Lock_or_Unlock [126055 126045 126166 126126 126063 126054 125926 126082 ] 1008517 -I Load [0 0 0 0 1 0 0 0 ] 1 +I Load [0 0 1 0 0 0 0 0 ] 1 I Ifetch [0 0 0 0 0 0 0 0 ] 0 I Store [0 0 0 0 0 0 0 0 ] 0 I Atomic [0 0 0 0 0 0 0 0 ] 0 -I L1_Replacement [241 227 217 230 252 253 255 243 ] 1918 +I L1_Replacement [169 163 158 189 181 166 174 180 ] 1380 I Data_Shared [0 0 0 0 0 0 0 0 ] 0 I Data_Owner [0 0 0 0 0 0 0 0 ] 0 I Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 I Ack [0 0 0 0 0 0 0 0 ] 0 I Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -I Transient_Local_GETX [1 0 1 0 0 0 0 1 ] 3 +I Transient_Local_GETX [0 0 0 0 0 0 0 1 ] 1 I Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -I Transient_Local_GETS [0 1 1 0 1 0 1 1 ] 5 +I Transient_Local_GETS [0 1 0 0 0 0 0 2 ] 3 I Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 I Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -I Persistent_GETS [0 1 0 1 0 0 0 0 ] 2 +I Persistent_GETX [1 0 0 0 0 0 0 0 ] 1 +I Persistent_GETS [0 0 0 0 1 1 0 1 ] 3 I Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 +I Own_Lock_or_Unlock [1 0 0 0 0 1 0 0 ] 2 -S Load [0 0 0 0 0 0 0 0 ] 0 +S Load [0 0 0 0 0 0 1 0 ] 1 S Ifetch [0 0 0 0 0 0 0 0 ] 0 S Store [0 0 0 0 0 0 0 0 ] 0 S Atomic [0 0 0 0 0 0 0 0 ] 0 -S L1_Replacement [296 296 271 286 260 285 287 269 ] 2250 -S Data_Shared [0 1 0 1 0 0 0 0 ] 2 -S Data_Owner [1 0 0 0 1 1 0 0 ] 3 -S Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +S L1_Replacement [271 278 240 269 246 251 273 243 ] 2071 +S Data_Shared [1 0 0 1 1 0 2 0 ] 5 +S Data_Owner [0 0 0 0 0 0 0 0 ] 0 +S Data_All_Tokens [0 0 0 0 0 1 0 0 ] 1 S Ack [0 0 0 0 0 0 0 0 ] 0 S Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETX [0 0 1 0 1 0 0 0 ] 2 +S Transient_Local_GETX [2 0 0 1 1 2 1 1 ] 8 S Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETS [0 1 0 1 0 0 1 0 ] 3 +S Transient_Local_GETS [1 0 0 0 0 0 0 0 ] 1 S Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETS_Last_Token [2 1 1 1 0 1 1 0 ] 7 -S Persistent_GETX [0 0 0 1 0 0 0 1 ] 2 -S Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 -S Persistent_GETS_Last_Token [0 1 0 0 1 0 1 0 ] 3 +S Transient_Local_GETS_Last_Token [0 1 0 1 2 0 1 4 ] 9 +S Persistent_GETX [0 0 0 0 1 0 0 0 ] 1 +S Persistent_GETS [0 1 1 0 0 0 0 0 ] 2 +S Persistent_GETS_Last_Token [1 0 0 0 0 0 1 1 ] 3 S Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 O Load [0 0 0 0 0 0 0 0 ] 0 O Ifetch [0 0 0 0 0 0 0 0 ] 0 O Store [0 0 0 0 0 0 0 0 ] 0 O Atomic [0 0 0 0 0 0 0 0 ] 0 -O L1_Replacement [163 169 151 160 159 184 161 154 ] 1301 +O L1_Replacement [130 144 111 121 133 127 115 133 ] 1014 O Data_Shared [0 0 0 0 0 0 0 0 ] 0 -O Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +O Data_All_Tokens [0 0 0 1 1 0 0 0 ] 2 O Ack [0 0 0 0 0 0 0 0 ] 0 -O Ack_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +O Ack_All_Tokens [1 0 0 0 0 0 0 0 ] 1 O Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -O Transient_Local_GETX [2 0 0 0 0 0 0 0 ] 2 +O Transient_Local_GETX [0 1 0 0 0 1 0 0 ] 2 O Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -O Transient_Local_GETS [1 0 2 0 0 2 0 1 ] 6 +O Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 O Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 O Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 O Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -O Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETS [0 0 0 0 0 1 0 1 ] 2 O Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -O Own_Lock_or_Unlock [11 14 22 12 16 11 6 13 ] 105 +O Own_Lock_or_Unlock [12 13 10 6 12 15 17 13 ] 98 -M Load [6 7 10 9 4 8 7 7 ] 58 +M Load [5 3 8 10 5 2 3 5 ] 41 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [1 3 4 6 2 9 2 9 ] 36 +M Store [3 4 0 0 3 2 5 4 ] 21 M Atomic [0 0 0 0 0 0 0 0 ] 0 -M L1_Replacement [49496 49294 49471 49566 49592 49476 49288 49311 ] 395494 +M L1_Replacement [49204 49432 49380 49193 49516 49207 49462 49373 ] 394767 M Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -M Transient_Local_GETX [61 53 60 64 59 74 65 53 ] 489 +M Transient_Local_GETX [44 55 33 54 49 36 52 40 ] 363 M Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -M Transient_Local_GETS [128 123 115 109 108 134 117 118 ] 952 -M Persistent_GETX [24 22 23 19 35 25 27 32 ] 207 -M Persistent_GETS [40 32 30 34 41 35 42 33 ] 287 -M Own_Lock_or_Unlock [3047 2879 2828 3000 2831 2866 2941 2876 ] 23268 +M Transient_Local_GETS [79 95 81 84 83 71 76 96 ] 665 +M Persistent_GETX [20 12 18 11 25 25 14 21 ] 146 +M Persistent_GETS [36 38 28 29 26 31 33 32 ] 253 +M Own_Lock_or_Unlock [1214 1239 1124 1181 1182 1218 1284 1191 ] 9633 -MM Load [5 4 9 3 1 5 3 5 ] 35 +MM Load [3 2 3 1 1 5 2 7 ] 24 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [1 1 1 1 2 1 4 3 ] 14 +MM Store [0 3 1 3 5 1 1 1 ] 15 MM Atomic [0 0 0 0 0 0 0 0 ] 0 -MM L1_Replacement [26500 26904 26874 26769 27124 26822 26698 26840 ] 214531 +MM L1_Replacement [26661 26741 26907 26631 26679 27034 26545 26361 ] 213559 MM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -MM Transient_Local_GETX [31 32 38 35 41 40 40 28 ] 285 +MM Transient_Local_GETX [16 21 25 27 31 31 27 28 ] 206 MM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -MM Transient_Local_GETS [75 61 50 63 73 55 76 79 ] 532 -MM Persistent_GETX [10 17 13 9 15 11 12 13 ] 100 -MM Persistent_GETS [24 25 18 30 25 41 23 29 ] 215 -MM Own_Lock_or_Unlock [1583 1584 1504 1627 1576 1603 1541 1560 ] 12578 +MM Transient_Local_GETS [49 33 36 42 45 35 37 41 ] 318 +MM Persistent_GETX [10 10 8 7 10 11 10 17 ] 83 +MM Persistent_GETS [9 12 15 22 12 17 17 14 ] 118 +MM Own_Lock_or_Unlock [664 644 631 637 703 657 679 663 ] 5278 -M_W Load [1 1 1 1 0 0 2 0 ] 6 +M_W Load [3 4 3 4 2 4 5 3 ] 28 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_W Store [0 0 0 1 0 1 2 0 ] 4 +M_W Store [1 2 2 1 1 2 0 0 ] 9 M_W Atomic [0 0 0 0 0 0 0 0 ] 0 -M_W L1_Replacement [220446 219952 218923 221066 221838 221045 220014 221393 ] 1764677 +M_W L1_Replacement [286355 286462 286414 285896 289077 287916 287742 288002 ] 2297864 M_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -M_W Transient_Local_GETX [18 12 11 13 13 15 6 12 ] 100 +M_W Transient_Local_GETX [37 44 33 39 41 27 30 36 ] 287 M_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -M_W Transient_Local_GETS [12 20 17 17 22 21 15 22 ] 146 -M_W Persistent_GETX [7 5 6 1 3 2 3 2 ] 29 -M_W Persistent_GETS [9 6 7 9 0 3 13 2 ] 49 -M_W Own_Lock_or_Unlock [154 148 142 150 154 164 163 169 ] 1244 -M_W Use_TimeoutStarverX [8 8 6 2 3 2 3 2 ] 34 -M_W Use_TimeoutStarverS [9 6 9 10 0 3 13 3 ] 53 -M_W Use_TimeoutNoStarvers [49750 49527 49704 49798 49839 49754 49541 49556 ] 397469 +M_W Transient_Local_GETS [63 60 78 60 66 79 75 88 ] 569 +M_W Persistent_GETX [4 6 7 8 3 4 4 5 ] 41 +M_W Persistent_GETS [7 15 15 17 4 10 11 4 ] 83 +M_W Own_Lock_or_Unlock [493 460 481 456 466 475 510 486 ] 3827 +M_W Use_TimeoutStarverX [5 7 10 10 4 4 5 6 ] 51 +M_W Use_TimeoutStarverS [8 17 17 17 4 10 12 6 ] 91 +M_W Use_TimeoutNoStarvers [49385 49637 49540 49370 49701 49371 49642 49566 ] 396212 M_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 -MM_W Load [2 0 1 1 1 0 0 0 ] 5 +MM_W Load [3 5 1 1 5 1 0 2 ] 18 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_W Store [1 0 1 0 0 0 0 0 ] 2 +MM_W Store [2 2 1 1 2 0 0 0 ] 8 MM_W Atomic [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_Replacement [118638 120623 119771 118934 120300 120552 119544 120447 ] 958809 +MM_W L1_Replacement [157226 155993 156855 154820 154961 157053 152795 151802 ] 1241505 MM_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -MM_W Transient_Local_GETX [5 1 7 8 5 6 7 9 ] 48 +MM_W Transient_Local_GETX [23 20 20 27 23 18 18 26 ] 175 MM_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -MM_W Transient_Local_GETS [11 8 10 15 8 13 14 13 ] 92 -MM_W Persistent_GETX [1 3 3 3 0 1 1 2 ] 14 -MM_W Persistent_GETS [4 6 4 3 1 4 7 4 ] 33 -MM_W Own_Lock_or_Unlock [87 84 100 86 91 89 84 102 ] 723 -MM_W Use_TimeoutStarverX [1 3 4 3 0 1 2 2 ] 16 -MM_W Use_TimeoutStarverS [5 6 4 4 1 4 7 4 ] 35 -MM_W Use_TimeoutNoStarvers [26639 27036 26989 26900 27276 26960 26848 26981 ] 215629 +MM_W Transient_Local_GETS [33 40 44 42 30 45 31 43 ] 308 +MM_W Persistent_GETX [7 2 7 6 1 0 6 4 ] 33 +MM_W Persistent_GETS [6 7 7 8 1 3 3 7 ] 42 +MM_W Own_Lock_or_Unlock [267 268 274 234 289 268 251 230 ] 2081 +MM_W Use_TimeoutStarverX [8 3 7 6 1 0 7 5 ] 37 +MM_W Use_TimeoutStarverS [6 8 7 8 1 4 4 7 ] 45 +MM_W Use_TimeoutNoStarvers [26742 26814 26992 26730 26774 27126 26631 26457 ] 214266 MM_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM Atomic [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [298819 304518 304460 302190 305979 304258 303791 302725 ] 2426740 +IM L1_Replacement [293187 293593 294161 290660 291613 293697 289899 286384 ] 2333194 IM Data_Shared [0 0 0 0 0 0 0 0 ] 0 -IM Data_Owner [0 0 1 0 0 0 0 0 ] 1 -IM Data_All_Tokens [26645 27046 26995 26905 27277 26964 26854 26987 ] 215673 -IM Ack [1 1 2 0 1 0 0 0 ] 5 +IM Data_Owner [0 0 0 2 1 1 0 1 ] 5 +IM Data_All_Tokens [26754 26820 27004 26741 26774 27126 26637 26467 ] 214323 +IM Ack [2 2 3 1 1 0 1 0 ] 10 IM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IM Transient_Local_GETX [92 103 98 98 79 83 85 72 ] 710 +IM Transient_Local_GETX [93 86 89 96 90 84 89 94 ] 721 IM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IM Transient_Local_GETS [183 171 176 158 171 191 142 185 ] 1377 +IM Transient_Local_GETS [146 152 150 165 147 144 175 151 ] 1230 IM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM Persistent_GETX [46 55 43 42 33 40 48 33 ] 340 -IM Persistent_GETS [76 81 83 93 63 79 51 79 ] 605 +IM Persistent_GETX [25 32 22 19 29 27 22 27 ] 203 +IM Persistent_GETS [48 52 57 63 36 38 50 42 ] 386 IM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM Own_Lock_or_Unlock [8718 8931 8869 8889 8914 8908 8835 8741 ] 70805 -IM Request_Timeout [173130 177820 171948 172223 170303 169179 174498 173026 ] 1382127 +IM Own_Lock_or_Unlock [5459 5374 5367 5430 5451 5464 5493 5292 ] 43330 +IM Request_Timeout [21135 20900 20567 19941 20807 20872 21113 20567 ] 165902 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -617,11 +632,11 @@ OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 OM Atomic [0 0 0 0 0 0 0 0 ] 0 -OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +OM L1_Replacement [0 0 0 0 0 0 0 1 ] 1 OM Data_Shared [0 0 0 0 0 0 0 0 ] 0 -OM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +OM Data_All_Tokens [0 0 0 1 0 0 0 0 ] 1 OM Ack [0 0 0 0 0 0 0 0 ] 0 -OM Ack_All_Tokens [0 0 1 0 0 0 0 0 ] 1 +OM Ack_All_Tokens [0 0 0 1 1 1 0 1 ] 4 OM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 OM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 OM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 @@ -631,89 +646,89 @@ OM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 OM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 OM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 OM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -OM Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 -OM Request_Timeout [0 0 0 0 0 0 0 0 ] 0 +OM Own_Lock_or_Unlock [0 0 0 0 0 0 0 1 ] 1 +OM Request_Timeout [0 0 0 0 0 0 0 1 ] 1 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS Atomic [0 0 0 0 0 0 0 0 ] 0 -IS L1_Replacement [565054 560250 560752 564542 563977 561580 558502 560185 ] 4494842 -IS Data_Shared [248 258 233 243 221 248 232 234 ] 1917 -IS Data_Owner [36 46 36 51 50 49 44 36 ] 348 -IS Data_All_Tokens [49766 49538 49717 49809 49842 49760 49559 49560 ] 397551 -IS Ack [0 0 0 0 0 0 0 0 ] 0 +IS L1_Replacement [538071 541776 543065 540757 544335 541706 545395 544834 ] 4339939 +IS Data_Shared [229 223 195 224 218 212 229 205 ] 1735 +IS Data_Owner [52 50 30 38 51 58 39 38 ] 356 +IS Data_All_Tokens [49398 49661 49564 49396 49709 49388 49658 49576 ] 396350 +IS Ack [1 0 0 0 0 0 1 0 ] 2 IS Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Transient_Local_GETX [161 174 184 133 159 144 158 159 ] 1272 +IS Transient_Local_GETX [151 161 151 165 150 167 139 160 ] 1244 IS Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IS Transient_Local_GETS [316 275 309 312 280 284 305 264 ] 2345 +IS Transient_Local_GETS [320 311 300 269 284 296 299 288 ] 2367 IS Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IS Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS Persistent_GETX [70 82 101 76 68 77 75 70 ] 619 -IS Persistent_GETS [141 146 152 152 129 126 131 120 ] 1097 +IS Persistent_GETX [49 57 59 55 36 37 47 56 ] 396 +IS Persistent_GETS [104 99 102 96 85 111 92 93 ] 782 IS Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS Own_Lock_or_Unlock [16494 16315 16326 16687 16478 16340 16388 16314 ] 131342 -IS Request_Timeout [317408 315566 318533 322146 320140 320154 314719 313887 ] 2542553 +IS Own_Lock_or_Unlock [9835 10021 9900 9900 9914 9957 10049 9927 ] 79503 +IS Request_Timeout [37997 38857 38679 38267 38593 37966 38402 39503 ] 308264 -I_L Load [102 106 111 120 107 100 111 106 ] 863 +I_L Load [82 66 66 87 82 77 81 64 ] 605 I_L Ifetch [0 0 0 0 0 0 0 0 ] 0 -I_L Store [56 56 55 68 56 64 69 55 ] 479 +I_L Store [37 34 41 29 41 33 56 35 ] 306 I_L Atomic [0 0 0 0 0 0 0 0 ] 0 -I_L L1_Replacement [89 72 47 109 96 84 43 117 ] 657 +I_L L1_Replacement [247 203 249 317 197 148 234 329 ] 1924 I_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 I_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -I_L Data_All_Tokens [1 0 0 0 1 0 0 0 ] 2 +I_L Data_All_Tokens [18 8 7 4 40 44 23 18 ] 162 I_L Ack [0 0 0 0 0 0 0 0 ] 0 I_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -I_L Transient_Local_GETX [350 358 360 349 366 364 358 361 ] 2866 +I_L Transient_Local_GETX [225 228 230 227 221 233 222 225 ] 1811 I_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -I_L Transient_Local_GETS [673 663 642 644 642 658 683 660 ] 5265 +I_L Transient_Local_GETS [429 452 459 415 443 435 437 432 ] 3502 I_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 I_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I_L Persistent_GETX [63036 62768 62815 62839 62889 62863 62943 63016 ] 503169 -I_L Persistent_GETS [116485 116671 116569 116206 116607 116685 116643 116715 ] 932581 +I_L Persistent_GETX [39826 39905 39895 39887 39861 39859 39847 40028 ] 319108 +I_L Persistent_GETS [73335 73162 73245 73226 73392 73263 73153 73280 ] 586056 I_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I_L Own_Lock_or_Unlock [72 82 68 69 79 84 74 83 ] 611 +I_L Own_Lock_or_Unlock [59 53 65 65 56 62 57 71 ] 488 S_L Load [0 0 0 0 0 0 0 0 ] 0 S_L Ifetch [0 0 0 0 0 0 0 0 ] 0 S_L Store [0 0 0 0 0 0 0 0 ] 0 S_L Atomic [0 0 0 0 0 0 0 0 ] 0 -S_L L1_Replacement [3 16 7 0 8 10 1 10 ] 55 +S_L L1_Replacement [24 80 47 56 42 35 64 55 ] 403 S_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 S_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 S_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 S_L Ack [0 0 0 0 0 0 0 0 ] 0 S_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -S_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_Local_GETX [0 0 0 0 0 0 0 1 ] 1 S_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 S_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 S_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 S_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 S_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -S_L Persistent_GETS [7 4 7 8 0 3 6 1 ] 36 +S_L Persistent_GETS [5 17 10 14 0 4 7 6 ] 63 S_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -S_L Own_Lock_or_Unlock [49 39 39 44 42 38 56 36 ] 343 +S_L Own_Lock_or_Unlock [45 56 46 46 30 42 46 40 ] 351 IM_L Load [0 0 0 0 0 0 0 0 ] 0 IM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 IM_L Store [0 0 0 0 0 0 0 0 ] 0 IM_L Atomic [0 0 0 0 0 0 0 0 ] 0 -IM_L L1_Replacement [1075 981 1271 1397 864 1093 964 890 ] 8535 +IM_L L1_Replacement [691 828 843 772 616 625 788 576 ] 5739 IM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 IM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -IM_L Data_All_Tokens [1 0 1 1 0 0 1 0 ] 4 +IM_L Data_All_Tokens [1 3 0 0 1 1 5 1 ] 12 IM_L Ack [0 0 0 0 0 0 0 0 ] 0 IM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IM_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_Local_GETX [1 0 1 1 0 0 0 0 ] 3 IM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IM_L Transient_Local_GETS [0 0 0 0 0 0 0 1 ] 1 +IM_L Transient_Local_GETS [0 0 0 1 0 1 1 2 ] 5 IM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM_L Persistent_GETX [9 17 7 17 0 4 4 5 ] 63 -IM_L Persistent_GETS [19 15 32 38 0 6 12 15 ] 137 -IM_L Own_Lock_or_Unlock [177 192 180 202 152 183 167 167 ] 1420 -IM_L Request_Timeout [1324 944 1204 1019 734 1314 835 879 ] 8253 +IM_L Persistent_GETX [10 10 10 6 0 3 2 4 ] 45 +IM_L Persistent_GETS [13 15 23 29 0 2 7 11 ] 100 +IM_L Own_Lock_or_Unlock [109 115 120 111 105 97 123 103 ] 883 +IM_L Request_Timeout [152 194 147 151 92 152 130 128 ] 1146 SM_L Load [0 0 0 0 0 0 0 0 ] 0 SM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -740,21 +755,21 @@ IS_L Load [0 0 0 0 0 0 0 0 ] 0 IS_L Ifetch [0 0 0 0 0 0 0 0 ] 0 IS_L Store [0 0 0 0 0 0 0 0 ] 0 IS_L Atomic [0 0 0 0 0 0 0 0 ] 0 -IS_L L1_Replacement [2243 2416 2615 2434 1854 1672 2179 1758 ] 17171 -IS_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IS_L L1_Replacement [1483 1376 1515 2003 1352 1369 1430 1386 ] 11914 +IS_L Data_Shared [0 1 0 1 1 0 0 0 ] 3 IS_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -IS_L Data_All_Tokens [1 3 2 2 0 0 0 1 ] 9 +IS_L Data_All_Tokens [2 3 5 2 1 0 2 3 ] 18 IS_L Ack [0 0 0 0 0 0 0 0 ] 0 IS_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IS_L Transient_Local_GETX [1 0 0 1 0 0 0 0 ] 2 +IS_L Transient_Local_GETX [0 0 0 1 0 1 1 0 ] 3 IS_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IS_L Transient_Local_GETS [1 2 2 1 2 0 0 0 ] 8 +IS_L Transient_Local_GETS [0 0 0 2 0 0 0 2 ] 4 IS_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IS_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS_L Persistent_GETX [16 22 40 22 0 7 7 12 ] 126 -IS_L Persistent_GETS [34 43 61 58 3 13 17 23 ] 252 -IS_L Own_Lock_or_Unlock [312 331 362 346 304 303 317 295 ] 2570 -IS_L Request_Timeout [1613 2345 2553 1656 2173 2649 2683 1709 ] 17381 +IS_L Persistent_GETX [9 13 24 25 0 2 11 14 ] 98 +IS_L Persistent_GETS [24 24 36 40 0 11 5 18 ] 158 +IS_L Own_Lock_or_Unlock [233 218 222 235 201 225 218 210 ] 1762 +IS_L Request_Timeout [341 233 222 246 275 240 190 265 ] 2012 Cache Stats: system.l1_cntrl1.L1IcacheMemory system.l1_cntrl1.L1IcacheMemory_total_misses: 0 @@ -765,16 +780,16 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 77024 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 77024 + system.l1_cntrl1.L1DcacheMemory_total_misses: 76789 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76789 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.9914% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.0086% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.6694% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.3306% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 77024 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 76789 100% Cache Stats: system.l1_cntrl2.L1IcacheMemory system.l1_cntrl2.L1IcacheMemory_total_misses: 0 @@ -785,16 +800,16 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory Cache Stats: system.l1_cntrl2.L1DcacheMemory - system.l1_cntrl2.L1DcacheMemory_total_misses: 76693 - system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76693 + system.l1_cntrl2.L1DcacheMemory_total_misses: 76573 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76573 system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.9838% - system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.0162% + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 65.2058% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 34.7942% - system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76693 100% + system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76573 100% Cache Stats: system.l1_cntrl3.L1IcacheMemory system.l1_cntrl3.L1IcacheMemory_total_misses: 0 @@ -805,16 +820,16 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory Cache Stats: system.l1_cntrl3.L1DcacheMemory - system.l1_cntrl3.L1DcacheMemory_total_misses: 76821 - system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76821 + system.l1_cntrl3.L1DcacheMemory_total_misses: 76294 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76294 system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L1DcacheMemory_request_type_LD: 64.869% - system.l1_cntrl3.L1DcacheMemory_request_type_ST: 35.131% + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.3066% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.6934% - system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 76821 100% + system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 76294 100% Cache Stats: system.l1_cntrl4.L1IcacheMemory system.l1_cntrl4.L1IcacheMemory_total_misses: 0 @@ -825,16 +840,16 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory Cache Stats: system.l1_cntrl4.L1DcacheMemory - system.l1_cntrl4.L1DcacheMemory_total_misses: 76700 - system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76700 + system.l1_cntrl4.L1DcacheMemory_total_misses: 76439 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76439 system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L1DcacheMemory_request_type_LD: 65.2581% - system.l1_cntrl4.L1DcacheMemory_request_type_ST: 34.7419% + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.9982% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.0018% - system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76700 100% + system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76439 100% Cache Stats: system.l1_cntrl5.L1IcacheMemory system.l1_cntrl5.L1IcacheMemory_total_misses: 0 @@ -845,16 +860,16 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory Cache Stats: system.l1_cntrl5.L1DcacheMemory - system.l1_cntrl5.L1DcacheMemory_total_misses: 76894 - system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76894 + system.l1_cntrl5.L1DcacheMemory_total_misses: 76762 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76762 system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.823% - system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.177% + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.0569% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.9431% - system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 76894 100% + system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 76762 100% Cache Stats: system.l1_cntrl6.L1IcacheMemory system.l1_cntrl6.L1IcacheMemory_total_misses: 0 @@ -865,16 +880,16 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory Cache Stats: system.l1_cntrl6.L1DcacheMemory - system.l1_cntrl6.L1DcacheMemory_total_misses: 76988 - system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76988 + system.l1_cntrl6.L1DcacheMemory_total_misses: 76801 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76801 system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.9322% - system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.0678% + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.839% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.161% - system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76988 100% + system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76801 100% Cache Stats: system.l1_cntrl7.L1IcacheMemory system.l1_cntrl7.L1IcacheMemory_total_misses: 0 @@ -885,63 +900,63 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory Cache Stats: system.l1_cntrl7.L1DcacheMemory - system.l1_cntrl7.L1DcacheMemory_total_misses: 77015 - system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77015 + system.l1_cntrl7.L1DcacheMemory_total_misses: 76407 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76407 system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L1DcacheMemory_request_type_LD: 65.0614% - system.l1_cntrl7.L1DcacheMemory_request_type_ST: 34.9386% + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.9954% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.0046% - system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 77015 100% + system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 76407 100% Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 614008 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 614008 + system.l2_cntrl0.L2cacheMemory_total_misses: 611155 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 611155 system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_request_type_GETS: 64.9635% - system.l2_cntrl0.L2cacheMemory_request_type_GETX: 35.0365% + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 65.0234% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 34.9766% - system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 614008 100% + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 611155 100% --- L2Cache --- - Event Counts - -L1_GETS [399838 ] 399838 -L1_GETS_Last_Token [1 ] 1 -L1_GETX [215688 ] 215688 -L1_INV [1919 ] 1919 +L1_GETS [398474 ] 398474 +L1_GETS_Last_Token [3 ] 3 +L1_GETX [214346 ] 214346 +L1_INV [1381 ] 1381 Transient_GETX [0 ] 0 Transient_GETS [0 ] 0 Transient_GETS_Last_Token [0 ] 0 -L2_Replacement [610254 ] 610254 +L2_Replacement [579446 ] 579446 Writeback_Tokens [0 ] 0 -Writeback_Shared_Data [1540 ] 1540 -Writeback_All_Tokens [610986 ] 610986 -Writeback_Owned [1050 ] 1050 +Writeback_Shared_Data [1446 ] 1446 +Writeback_All_Tokens [609126 ] 609126 +Writeback_Owned [838 ] 838 Data_Shared [0 ] 0 Data_Owner [0 ] 0 Data_All_Tokens [0 ] 0 Ack [0 ] 0 Ack_All_Tokens [0 ] 0 -Persistent_GETX [72096 ] 72096 -Persistent_GETS [133613 ] 133613 -Persistent_GETS_Last_Token [1 ] 1 -Own_Lock_or_Unlock [203486 ] 203486 +Persistent_GETX [45737 ] 45737 +Persistent_GETS [84009 ] 84009 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [128249 ] 128249 - Transitions - -NP L1_GETS [398004 ] 398004 -NP L1_GETX [214650 ] 214650 -NP L1_INV [1310 ] 1310 +NP L1_GETS [396802 ] 396802 +NP L1_GETX [213453 ] 213453 +NP L1_INV [900 ] 900 NP Transient_GETX [0 ] 0 NP Transient_GETS [0 ] 0 NP Writeback_Tokens [0 ] 0 -NP Writeback_Shared_Data [1535 ] 1535 -NP Writeback_All_Tokens [607716 ] 607716 -NP Writeback_Owned [1011 ] 1011 +NP Writeback_Shared_Data [1382 ] 1382 +NP Writeback_All_Tokens [577342 ] 577342 +NP Writeback_Owned [730 ] 730 NP Data_Shared [0 ] 0 NP Data_Owner [0 ] 0 NP Data_All_Tokens [0 ] 0 @@ -949,20 +964,20 @@ NP Ack [0 ] 0 NP Persistent_GETX [0 ] 0 NP Persistent_GETS [0 ] 0 NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [202659 ] 202659 +NP Own_Lock_or_Unlock [127917 ] 127917 -I L1_GETS [0 ] 0 +I L1_GETS [2 ] 2 I L1_GETS_Last_Token [0 ] 0 I L1_GETX [0 ] 0 -I L1_INV [0 ] 0 +I L1_INV [2 ] 2 I Transient_GETX [0 ] 0 I Transient_GETS [0 ] 0 I Transient_GETS_Last_Token [0 ] 0 -I L2_Replacement [522 ] 522 +I L2_Replacement [553 ] 553 I Writeback_Tokens [0 ] 0 -I Writeback_Shared_Data [1 ] 1 -I Writeback_All_Tokens [864 ] 864 -I Writeback_Owned [0 ] 0 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [364 ] 364 +I Writeback_Owned [2 ] 2 I Data_Shared [0 ] 0 I Data_Owner [0 ] 0 I Data_All_Tokens [0 ] 0 @@ -972,75 +987,75 @@ I Persistent_GETS [0 ] 0 I Persistent_GETS_Last_Token [0 ] 0 I Own_Lock_or_Unlock [0 ] 0 -S L1_GETS [1 ] 1 -S L1_GETS_Last_Token [1 ] 1 +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [3 ] 3 S L1_GETX [1 ] 1 S L1_INV [0 ] 0 S Transient_GETX [0 ] 0 S Transient_GETS [0 ] 0 S Transient_GETS_Last_Token [0 ] 0 -S L2_Replacement [1281 ] 1281 +S L2_Replacement [1205 ] 1205 S Writeback_Tokens [0 ] 0 -S Writeback_Shared_Data [2 ] 2 -S Writeback_All_Tokens [251 ] 251 -S Writeback_Owned [4 ] 4 +S Writeback_Shared_Data [5 ] 5 +S Writeback_All_Tokens [176 ] 176 +S Writeback_Owned [0 ] 0 S Data_Shared [0 ] 0 S Data_Owner [0 ] 0 S Data_All_Tokens [0 ] 0 S Ack [0 ] 0 -S Persistent_GETX [0 ] 0 +S Persistent_GETX [2 ] 2 S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [1 ] 1 +S Persistent_GETS_Last_Token [0 ] 0 S Own_Lock_or_Unlock [0 ] 0 -O L1_GETS [2 ] 2 +O L1_GETS [13 ] 13 O L1_GETS_Last_Token [0 ] 0 -O L1_GETX [0 ] 0 +O L1_GETX [3 ] 3 O L1_INV [0 ] 0 O Transient_GETX [0 ] 0 O Transient_GETS [0 ] 0 O Transient_GETS_Last_Token [0 ] 0 -O L2_Replacement [1255 ] 1255 +O L2_Replacement [1164 ] 1164 O Writeback_Tokens [0 ] 0 -O Writeback_Shared_Data [2 ] 2 -O Writeback_All_Tokens [710 ] 710 +O Writeback_Shared_Data [7 ] 7 +O Writeback_All_Tokens [625 ] 625 O Data_Shared [0 ] 0 O Data_All_Tokens [0 ] 0 O Ack [0 ] 0 O Ack_All_Tokens [0 ] 0 O Persistent_GETX [1 ] 1 -O Persistent_GETS [3 ] 3 +O Persistent_GETS [6 ] 6 O Persistent_GETS_Last_Token [0 ] 0 O Own_Lock_or_Unlock [0 ] 0 -M L1_GETS [954 ] 954 -M L1_GETX [561 ] 561 +M L1_GETS [1067 ] 1067 +M L1_GETX [585 ] 585 M L1_INV [0 ] 0 M Transient_GETX [0 ] 0 M Transient_GETS [0 ] 0 -M L2_Replacement [606691 ] 606691 -M Persistent_GETX [443 ] 443 -M Persistent_GETS [884 ] 884 +M L2_Replacement [575547 ] 575547 +M Persistent_GETX [456 ] 456 +M Persistent_GETS [844 ] 844 M Own_Lock_or_Unlock [0 ] 0 -I_L L1_GETS [877 ] 877 -I_L L1_GETX [476 ] 476 -I_L L1_INV [609 ] 609 +I_L L1_GETS [590 ] 590 +I_L L1_GETX [304 ] 304 +I_L L1_INV [479 ] 479 I_L Transient_GETX [0 ] 0 I_L Transient_GETS [0 ] 0 I_L Transient_GETS_Last_Token [0 ] 0 -I_L L2_Replacement [504 ] 504 +I_L L2_Replacement [976 ] 976 I_L Writeback_Tokens [0 ] 0 -I_L Writeback_Shared_Data [0 ] 0 -I_L Writeback_All_Tokens [1445 ] 1445 -I_L Writeback_Owned [34 ] 34 +I_L Writeback_Shared_Data [52 ] 52 +I_L Writeback_All_Tokens [30619 ] 30619 +I_L Writeback_Owned [106 ] 106 I_L Data_Shared [0 ] 0 I_L Data_Owner [0 ] 0 I_L Data_All_Tokens [0 ] 0 I_L Ack [0 ] 0 -I_L Persistent_GETX [71652 ] 71652 -I_L Persistent_GETS [132726 ] 132726 -I_L Own_Lock_or_Unlock [824 ] 824 +I_L Persistent_GETX [45278 ] 45278 +I_L Persistent_GETS [83159 ] 83159 +I_L Own_Lock_or_Unlock [327 ] 327 S_L L1_GETS [0 ] 0 S_L L1_GETS_Last_Token [0 ] 0 @@ -1053,7 +1068,7 @@ S_L L2_Replacement [1 ] 1 S_L Writeback_Tokens [0 ] 0 S_L Writeback_Shared_Data [0 ] 0 S_L Writeback_All_Tokens [0 ] 0 -S_L Writeback_Owned [1 ] 1 +S_L Writeback_Owned [0 ] 0 S_L Data_Shared [0 ] 0 S_L Data_Owner [0 ] 0 S_L Data_All_Tokens [0 ] 0 @@ -1061,130 +1076,130 @@ S_L Ack [0 ] 0 S_L Persistent_GETX [0 ] 0 S_L Persistent_GETS [0 ] 0 S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [3 ] 3 +S_L Own_Lock_or_Unlock [5 ] 5 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 823669 - memory_reads: 608495 - memory_writes: 215141 - memory_refreshes: 40970 - memory_total_request_delays: 49399101 - memory_delays_per_request: 59.9745 - memory_delays_in_input_queue: 411894 - memory_delays_behind_head_of_bank_queue: 20188400 - memory_delays_stalled_at_head_of_bank_queue: 28798807 - memory_stalls_for_bank_busy: 4435508 + memory_total_requests: 839436 + memory_reads: 606633 + memory_writes: 232776 + memory_refreshes: 42441 + memory_total_request_delays: 42635771 + memory_delays_per_request: 50.791 + memory_delays_in_input_queue: 573691 + memory_delays_behind_head_of_bank_queue: 15655484 + memory_delays_stalled_at_head_of_bank_queue: 26406596 + memory_stalls_for_bank_busy: 4071407 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 6882411 - memory_stalls_for_arbitration: 5945554 - memory_stalls_for_bus: 8083401 + memory_stalls_for_anti_starvation: 6269256 + memory_stalls_for_arbitration: 5321089 + memory_stalls_for_bus: 7323994 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2055519 - memory_stalls_for_read_read_turnaround: 1396414 - accesses_per_bank: 25915 25519 25693 25866 25936 25821 26007 25777 25934 25745 25819 25922 25509 25555 25730 25568 25729 25737 25756 25703 25805 25671 25858 25625 25624 25316 25682 25315 25693 25911 26065 25863 + memory_stalls_for_read_write_turnaround: 2109198 + memory_stalls_for_read_read_turnaround: 1311652 + accesses_per_bank: 26436 25498 25466 25824 25753 25721 25819 25457 26092 25984 25792 26027 26244 26258 25879 26180 26072 26313 26023 26243 26185 26336 26214 26468 26428 26437 26867 26745 26755 27429 27532 26959 --- Directory --- - Event Counts - -GETX [396726 ] 396726 -GETS [740556 ] 740556 -Lockdown [205710 ] 205710 -Unlockdown [203486 ] 203486 +GETX [253842 ] 253842 +GETS [473790 ] 473790 +Lockdown [129746 ] 129746 +Unlockdown [128249 ] 128249 Own_Lock_or_Unlock [0 ] 0 Own_Lock_or_Unlock_Tokens [0 ] 0 -Data_Owner [205 ] 205 -Data_All_Tokens [214974 ] 214974 -Ack_Owner [695 ] 695 -Ack_Owner_All_Tokens [392649 ] 392649 -Tokens [449 ] 449 -Ack_All_Tokens [8751 ] 8751 +Data_Owner [342 ] 342 +Data_All_Tokens [233978 ] 233978 +Ack_Owner [692 ] 692 +Ack_Owner_All_Tokens [373280 ] 373280 +Tokens [455 ] 455 +Ack_All_Tokens [3706 ] 3706 Request_Timeout [0 ] 0 -Memory_Data [608491 ] 608491 -Memory_Ack [215141 ] 215141 +Memory_Data [606628 ] 606628 +Memory_Ack [232776 ] 232776 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX [211966 ] 211966 -O GETS [393002 ] 393002 -O Lockdown [1895 ] 1895 +O GETX [210720 ] 210720 +O GETS [391822 ] 391822 +O Lockdown [2450 ] 2450 O Unlockdown [0 ] 0 O Own_Lock_or_Unlock [0 ] 0 O Own_Lock_or_Unlock_Tokens [0 ] 0 O Data_Owner [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Tokens [1 ] 1 -O Ack_All_Tokens [889 ] 889 +O Data_All_Tokens [48 ] 48 +O Tokens [4 ] 4 +O Ack_All_Tokens [964 ] 964 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O DMA_WRITE_All_Tokens [0 ] 0 -NO GETX [1693 ] 1693 -NO GETS [3156 ] 3156 -NO Lockdown [8727 ] 8727 +NO GETX [2191 ] 2191 +NO GETS [3877 ] 3877 +NO Lockdown [20223 ] 20223 NO Unlockdown [0 ] 0 NO Own_Lock_or_Unlock [0 ] 0 NO Own_Lock_or_Unlock_Tokens [0 ] 0 -NO Data_Owner [205 ] 205 -NO Data_All_Tokens [214949 ] 214949 -NO Ack_Owner [695 ] 695 -NO Ack_Owner_All_Tokens [392626 ] 392626 -NO Tokens [392 ] 392 +NO Data_Owner [342 ] 342 +NO Data_All_Tokens [232445 ] 232445 +NO Ack_Owner [692 ] 692 +NO Ack_Owner_All_Tokens [373130 ] 373130 +NO Tokens [247 ] 247 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 -L GETX [1468 ] 1468 -L GETS [2722 ] 2722 -L Lockdown [1284 ] 1284 -L Unlockdown [203486 ] 203486 +L GETX [850 ] 850 +L GETS [1695 ] 1695 +L Lockdown [1073 ] 1073 +L Unlockdown [128249 ] 128249 L Own_Lock_or_Unlock [0 ] 0 L Own_Lock_or_Unlock_Tokens [0 ] 0 L Data_Owner [0 ] 0 -L Data_All_Tokens [25 ] 25 +L Data_All_Tokens [105 ] 105 L Ack_Owner [0 ] 0 -L Ack_Owner_All_Tokens [23 ] 23 -L Tokens [2 ] 2 +L Ack_Owner_All_Tokens [150 ] 150 +L Tokens [3 ] 3 L DMA_READ [0 ] 0 L DMA_WRITE [0 ] 0 L DMA_WRITE_All_Tokens [0 ] 0 -O_W GETX [48157 ] 48157 -O_W GETS [90657 ] 90657 -O_W Lockdown [1652 ] 1652 +O_W GETX [13245 ] 13245 +O_W GETS [26429 ] 26429 +O_W Lockdown [1657 ] 1657 O_W Unlockdown [0 ] 0 O_W Own_Lock_or_Unlock [0 ] 0 O_W Own_Lock_or_Unlock_Tokens [0 ] 0 O_W Data_Owner [0 ] 0 -O_W Data_All_Tokens [0 ] 0 +O_W Data_All_Tokens [1311 ] 1311 O_W Ack_Owner [0 ] 0 -O_W Tokens [54 ] 54 -O_W Ack_All_Tokens [7620 ] 7620 +O_W Tokens [201 ] 201 +O_W Ack_All_Tokens [2722 ] 2722 O_W Memory_Data [0 ] 0 -O_W Memory_Ack [213489 ] 213489 +O_W Memory_Ack [231119 ] 231119 O_W DMA_READ [0 ] 0 O_W DMA_WRITE [0 ] 0 O_W DMA_WRITE_All_Tokens [0 ] 0 -L_O_W GETX [41565 ] 41565 -L_O_W GETS [77934 ] 77934 -L_O_W Lockdown [23 ] 23 +L_O_W GETX [6131 ] 6131 +L_O_W GETS [13836 ] 13836 +L_O_W Lockdown [30 ] 30 L_O_W Unlockdown [0 ] 0 L_O_W Own_Lock_or_Unlock [0 ] 0 L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 L_O_W Data_Owner [0 ] 0 -L_O_W Data_All_Tokens [0 ] 0 +L_O_W Data_All_Tokens [69 ] 69 L_O_W Ack_Owner [0 ] 0 L_O_W Tokens [0 ] 0 -L_O_W Ack_All_Tokens [92 ] 92 -L_O_W Memory_Data [3546 ] 3546 -L_O_W Memory_Ack [1652 ] 1652 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [4107 ] 4107 +L_O_W Memory_Ack [1657 ] 1657 L_O_W DMA_READ [0 ] 0 L_O_W DMA_WRITE [0 ] 0 L_O_W DMA_WRITE_All_Tokens [0 ] 0 -L_NO_W GETX [43001 ] 43001 -L_NO_W GETS [81958 ] 81958 -L_NO_W Lockdown [911 ] 911 +L_NO_W GETX [5827 ] 5827 +L_NO_W GETS [10526 ] 10526 +L_NO_W Lockdown [393 ] 393 L_NO_W Unlockdown [0 ] 0 L_NO_W Own_Lock_or_Unlock [0 ] 0 L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 @@ -1192,8 +1207,8 @@ L_NO_W Data_Owner [0 ] 0 L_NO_W Data_All_Tokens [0 ] 0 L_NO_W Ack_Owner [0 ] 0 L_NO_W Tokens [0 ] 0 -L_NO_W Ack_All_Tokens [33 ] 33 -L_NO_W Memory_Data [191213 ] 191213 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [103920 ] 103920 L_NO_W DMA_READ [0 ] 0 L_NO_W DMA_WRITE [0 ] 0 L_NO_W DMA_WRITE_All_Tokens [0 ] 0 @@ -1232,9 +1247,9 @@ DW_L_W DMA_READ [0 ] 0 DW_L_W DMA_WRITE [0 ] 0 DW_L_W DMA_WRITE_All_Tokens [0 ] 0 -NO_W GETX [48876 ] 48876 -NO_W GETS [91127 ] 91127 -NO_W Lockdown [191218 ] 191218 +NO_W GETX [14878 ] 14878 +NO_W GETS [25605 ] 25605 +NO_W Lockdown [103920 ] 103920 NO_W Unlockdown [0 ] 0 NO_W Own_Lock_or_Unlock [0 ] 0 NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 @@ -1242,8 +1257,8 @@ NO_W Data_Owner [0 ] 0 NO_W Data_All_Tokens [0 ] 0 NO_W Ack_Owner [0 ] 0 NO_W Tokens [0 ] 0 -NO_W Ack_All_Tokens [117 ] 117 -NO_W Memory_Data [413732 ] 413732 +NO_W Ack_All_Tokens [20 ] 20 +NO_W Memory_Data [498601 ] 498601 NO_W DMA_READ [0 ] 0 NO_W DMA_WRITE [0 ] 0 NO_W DMA_WRITE_All_Tokens [0 ] 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr index 88920eb84..3706194a6 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr @@ -1,74 +1,82 @@ -system.cpu4: completed 10000 read, 5358 write accesses @1929263 -system.cpu0: completed 10000 read, 5517 write accesses @1938193 -system.cpu6: completed 10000 read, 5282 write accesses @1960370 -system.cpu2: completed 10000 read, 5370 write accesses @1983069 -system.cpu3: completed 10000 read, 5219 write accesses @1986540 -system.cpu5: completed 10000 read, 5534 write accesses @2010490 -system.cpu1: completed 10000 read, 5481 write accesses @2016799 -system.cpu7: completed 10000 read, 5483 write accesses @2027000 -system.cpu0: completed 20000 read, 10906 write accesses @3889460 -system.cpu6: completed 20000 read, 10539 write accesses @3890430 -system.cpu4: completed 20000 read, 10737 write accesses @3908329 -system.cpu2: completed 20000 read, 10719 write accesses @3939180 -system.cpu3: completed 20000 read, 10494 write accesses @3943600 -system.cpu5: completed 20000 read, 10848 write accesses @3948219 -system.cpu1: completed 20000 read, 10769 write accesses @4005719 -system.cpu7: completed 20000 read, 10891 write accesses @4012914 -system.cpu6: completed 30000 read, 15919 write accesses @5839330 -system.cpu4: completed 30000 read, 15999 write accesses @5874900 -system.cpu0: completed 30000 read, 16423 write accesses @5898830 -system.cpu5: completed 30000 read, 16404 write accesses @5936061 -system.cpu1: completed 30000 read, 16153 write accesses @5948410 -system.cpu7: completed 30000 read, 16256 write accesses @5950050 -system.cpu2: completed 30000 read, 16157 write accesses @5958790 -system.cpu3: completed 30000 read, 15885 write accesses @5959680 -system.cpu4: completed 40000 read, 21342 write accesses @7808600 -system.cpu6: completed 40000 read, 21196 write accesses @7836451 -system.cpu0: completed 40000 read, 21854 write accesses @7880130 -system.cpu1: completed 40000 read, 21631 write accesses @7920239 -system.cpu7: completed 40000 read, 21703 write accesses @7933959 -system.cpu5: completed 40000 read, 21772 write accesses @7955069 -system.cpu3: completed 40000 read, 21372 write accesses @7959100 -system.cpu2: completed 40000 read, 21557 write accesses @7981970 -system.cpu6: completed 50000 read, 26595 write accesses @9809169 -system.cpu4: completed 50000 read, 26864 write accesses @9817559 -system.cpu7: completed 50000 read, 27042 write accesses @9902500 -system.cpu0: completed 50000 read, 27271 write accesses @9906269 -system.cpu1: completed 50000 read, 27124 write accesses @9934930 -system.cpu3: completed 50000 read, 26755 write accesses @9946640 -system.cpu5: completed 50000 read, 27198 write accesses @9946679 -system.cpu2: completed 50000 read, 27060 write accesses @9974740 -system.cpu6: completed 60000 read, 32039 write accesses @11769919 -system.cpu4: completed 60000 read, 32173 write accesses @11822509 -system.cpu1: completed 60000 read, 32379 write accesses @11844429 -system.cpu0: completed 60000 read, 32699 write accesses @11852900 -system.cpu7: completed 60000 read, 32457 write accesses @11873181 -system.cpu5: completed 60000 read, 32557 write accesses @11887270 -system.cpu3: completed 60000 read, 32167 write accesses @11912630 -system.cpu2: completed 60000 read, 32437 write accesses @11967610 -system.cpu4: completed 70000 read, 37476 write accesses @13774590 -system.cpu1: completed 70000 read, 37764 write accesses @13776500 -system.cpu6: completed 70000 read, 37423 write accesses @13811110 -system.cpu0: completed 70000 read, 38112 write accesses @13822360 -system.cpu7: completed 70000 read, 37768 write accesses @13852100 -system.cpu3: completed 70000 read, 37356 write accesses @13890992 -system.cpu5: completed 70000 read, 38000 write accesses @13891330 -system.cpu2: completed 70000 read, 37653 write accesses @13903529 -system.cpu4: completed 80000 read, 42652 write accesses @15714260 -system.cpu1: completed 80000 read, 43161 write accesses @15743660 -system.cpu0: completed 80000 read, 43377 write accesses @15747360 -system.cpu6: completed 80000 read, 42650 write accesses @15761321 -system.cpu7: completed 80000 read, 43147 write accesses @15846829 -system.cpu2: completed 80000 read, 42984 write accesses @15878720 -system.cpu3: completed 80000 read, 42913 write accesses @15881610 -system.cpu5: completed 80000 read, 43333 write accesses @15910140 -system.cpu4: completed 90000 read, 48050 write accesses @17730480 -system.cpu1: completed 90000 read, 48527 write accesses @17731920 -system.cpu0: completed 90000 read, 48688 write accesses @17739870 -system.cpu6: completed 90000 read, 48114 write accesses @17751610 -system.cpu7: completed 90000 read, 48607 write accesses @17816041 -system.cpu2: completed 90000 read, 48386 write accesses @17847760 -system.cpu3: completed 90000 read, 48361 write accesses @17860389 -system.cpu5: completed 90000 read, 48782 write accesses @17871890 -system.cpu4: completed 100000 read, 53373 write accesses @19665440 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +system.cpu3: completed 10000 read, 5335 write accesses @606797 +system.cpu5: completed 10000 read, 5331 write accesses @607565 +system.cpu4: completed 10000 read, 5526 write accesses @608260 +system.cpu2: completed 10000 read, 5318 write accesses @614261 +system.cpu1: completed 10000 read, 5400 write accesses @614387 +system.cpu7: completed 10000 read, 5362 write accesses @615713 +system.cpu6: completed 10000 read, 5564 write accesses @615733 +system.cpu0: completed 10000 read, 5551 write accesses @616304 +system.cpu5: completed 20000 read, 10723 write accesses @1217974 +system.cpu0: completed 20000 read, 11047 write accesses @1228624 +system.cpu4: completed 20000 read, 10902 write accesses @1228676 +system.cpu1: completed 20000 read, 10777 write accesses @1228883 +system.cpu7: completed 20000 read, 10727 write accesses @1230451 +system.cpu3: completed 20000 read, 10656 write accesses @1231448 +system.cpu2: completed 20000 read, 10657 write accesses @1236334 +system.cpu6: completed 20000 read, 11082 write accesses @1236758 +system.cpu5: completed 30000 read, 15988 write accesses @1827079 +system.cpu1: completed 30000 read, 16124 write accesses @1833167 +system.cpu3: completed 30000 read, 15943 write accesses @1835575 +system.cpu6: completed 30000 read, 16327 write accesses @1840325 +system.cpu0: completed 30000 read, 16411 write accesses @1845820 +system.cpu7: completed 30000 read, 16138 write accesses @1851244 +system.cpu2: completed 30000 read, 16138 write accesses @1863740 +system.cpu4: completed 30000 read, 16319 write accesses @1864484 +system.cpu5: completed 40000 read, 21536 write accesses @2432906 +system.cpu1: completed 40000 read, 21516 write accesses @2445656 +system.cpu0: completed 40000 read, 21751 write accesses @2457852 +system.cpu3: completed 40000 read, 21310 write accesses @2457970 +system.cpu7: completed 40000 read, 21388 write accesses @2458337 +system.cpu6: completed 40000 read, 21741 write accesses @2459051 +system.cpu4: completed 40000 read, 21462 write accesses @2473826 +system.cpu2: completed 40000 read, 21429 write accesses @2476553 +system.cpu5: completed 50000 read, 27059 write accesses @3049178 +system.cpu7: completed 50000 read, 26653 write accesses @3064589 +system.cpu1: completed 50000 read, 26847 write accesses @3066332 +system.cpu3: completed 50000 read, 26520 write accesses @3067661 +system.cpu6: completed 50000 read, 27151 write accesses @3069278 +system.cpu4: completed 50000 read, 26852 write accesses @3080753 +system.cpu0: completed 50000 read, 27078 write accesses @3081059 +system.cpu2: completed 50000 read, 26858 write accesses @3093584 +system.cpu5: completed 60000 read, 32391 write accesses @3656779 +system.cpu1: completed 60000 read, 32290 write accesses @3669694 +system.cpu3: completed 60000 read, 31832 write accesses @3679631 +system.cpu0: completed 60000 read, 32411 write accesses @3682976 +system.cpu7: completed 60000 read, 31852 write accesses @3683261 +system.cpu6: completed 60000 read, 32690 write accesses @3693796 +system.cpu2: completed 60000 read, 32174 write accesses @3694259 +system.cpu4: completed 60000 read, 32211 write accesses @3697154 +system.cpu1: completed 70000 read, 37707 write accesses @4274498 +system.cpu3: completed 70000 read, 37255 write accesses @4279718 +system.cpu5: completed 70000 read, 37867 write accesses @4283684 +system.cpu0: completed 70000 read, 37805 write accesses @4287731 +system.cpu7: completed 70000 read, 37138 write accesses @4296794 +system.cpu2: completed 70000 read, 37605 write accesses @4304710 +system.cpu6: completed 70000 read, 38072 write accesses @4311342 +system.cpu4: completed 70000 read, 37624 write accesses @4316870 +system.cpu3: completed 80000 read, 42498 write accesses @4877336 +system.cpu0: completed 80000 read, 43132 write accesses @4889693 +system.cpu1: completed 80000 read, 43168 write accesses @4896265 +system.cpu5: completed 80000 read, 43273 write accesses @4899143 +system.cpu7: completed 80000 read, 42494 write accesses @4912991 +system.cpu2: completed 80000 read, 43018 write accesses @4921903 +system.cpu6: completed 80000 read, 43483 write accesses @4928537 +system.cpu4: completed 80000 read, 42951 write accesses @4931114 +system.cpu3: completed 90000 read, 47893 write accesses @5493844 +system.cpu1: completed 90000 read, 48591 write accesses @5495944 +system.cpu0: completed 90000 read, 48484 write accesses @5503496 +system.cpu5: completed 90000 read, 48798 write accesses @5509616 +system.cpu2: completed 90000 read, 48092 write accesses @5514734 +system.cpu7: completed 90000 read, 47926 write accesses @5524841 +system.cpu4: completed 90000 read, 48357 write accesses @5550818 +system.cpu6: completed 90000 read, 48791 write accesses @5555216 +system.cpu3: completed 100000 read, 53266 write accesses @6111458 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 9e326e98d..05221f315 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.006104 # Number of seconds simulated -sim_ticks 6103915 # Number of ticks simulated -final_tick 6103915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.006111 # Number of seconds simulated +sim_ticks 6111458 # Number of ticks simulated +final_tick 6111458 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 78453 # Simulator tick rate (ticks/s) -host_mem_usage 374396 # Number of bytes of host memory used -host_seconds 77.80 # Real time elapsed on the host +host_tick_rate 30926 # Simulator tick rate (ticks/s) +host_mem_usage 418916 # Number of bytes of host memory used +host_seconds 197.62 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99027 # number of read accesses completed -system.cpu0.num_writes 53493 # number of write accesses completed +system.cpu0.num_reads 99998 # number of read accesses completed +system.cpu0.num_writes 53877 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98254 # number of read accesses completed -system.cpu1.num_writes 52787 # number of write accesses completed +system.cpu1.num_reads 99919 # number of read accesses completed +system.cpu1.num_writes 53996 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99047 # number of read accesses completed -system.cpu2.num_writes 53306 # number of write accesses completed +system.cpu2.num_reads 99673 # number of read accesses completed +system.cpu2.num_writes 53416 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98414 # number of read accesses completed -system.cpu3.num_writes 53420 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53266 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53741 # number of write accesses completed +system.cpu4.num_reads 99266 # number of read accesses completed +system.cpu4.num_writes 53358 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98111 # number of read accesses completed -system.cpu5.num_writes 53002 # number of write accesses completed +system.cpu5.num_reads 99912 # number of read accesses completed +system.cpu5.num_writes 54055 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99154 # number of read accesses completed -system.cpu6.num_writes 52587 # number of write accesses completed +system.cpu6.num_reads 99083 # number of read accesses completed +system.cpu6.num_writes 53609 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99215 # number of read accesses completed -system.cpu7.num_writes 53364 # number of write accesses completed +system.cpu7.num_reads 99673 # number of read accesses completed +system.cpu7.num_writes 53053 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 0cd598762..e03b1349c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -1,26 +1,26 @@ -Real time: Sep/01/2012 13:56:48 +Real time: Oct/08/2012 22:26:45 Profiler Stats -------------- -Elapsed_time_in_seconds: 121 -Elapsed_time_in_minutes: 2.01667 -Elapsed_time_in_hours: 0.0336111 -Elapsed_time_in_days: 0.00140046 +Elapsed_time_in_seconds: 203 +Elapsed_time_in_minutes: 3.38333 +Elapsed_time_in_hours: 0.0563889 +Elapsed_time_in_days: 0.00234954 -Virtual_time_in_seconds: 120.93 -Virtual_time_in_minutes: 2.0155 -Virtual_time_in_hours: 0.0335917 -Virtual_time_in_days: 0.00139965 +Virtual_time_in_seconds: 129.97 +Virtual_time_in_minutes: 2.16617 +Virtual_time_in_hours: 0.0361028 +Virtual_time_in_days: 0.00150428 -Ruby_current_time: 5747338 +Ruby_current_time: 5753960 Ruby_start_time: 0 -Ruby_cycles: 5747338 +Ruby_cycles: 5753960 -mbytes_resident: 62.8672 -mbytes_total: 400.102 -resident_ratio: 0.157177 +mbytes_resident: 70.1953 +mbytes_total: 408.012 +resident_ratio: 0.172052 -ruby_cycles_executed: [ 5747339 5747339 5747339 5747339 5747339 5747339 5747339 5747339 ] +ruby_cycles_executed: [ 5753961 5753961 5753961 5753961 5753961 5753961 5753961 5753961 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -30,35 +30,35 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 612864 average: 15.9984 | standard deviation: 0.127219 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 612744 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 613792 average: 15.9984 | standard deviation: 0.127123 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 613672 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 5247 count: 612736 average: 1200.43 | standard deviation: 897.753 | 282 3145 8418 12081 13312 12877 15699 17671 17489 17880 16553 14660 15865 15185 12484 11889 11249 9697 9502 8356 7211 7587 7118 6059 5890 5701 5297 5572 5174 4606 4864 5141 4378 4820 4644 4486 4862 4750 4369 4793 4847 4353 4790 4617 4479 5013 4880 4480 4858 5377 4807 5191 5296 5178 5620 5684 5179 5970 6235 5389 5903 5837 5750 6222 6055 5471 5960 6002 5404 5648 5564 5253 5438 5123 4630 4978 4858 4210 4359 4067 3842 3853 3397 2967 3040 3101 2429 2500 2356 2111 2087 1852 1581 1543 1546 1203 1271 1119 1032 946 864 717 757 667 555 483 474 395 400 317 309 314 224 217 188 171 143 146 116 99 92 84 63 82 42 64 42 39 32 32 29 19 25 23 26 17 6 13 14 12 7 7 4 3 5 4 2 2 6 1 1 2 1 4 1 1 1 2 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 32 max: 5181 count: 398016 average: 1200.52 | standard deviation: 897.915 | 195 2039 5427 7772 8559 8297 10210 11611 11403 11656 10753 9510 10329 9903 8017 7771 7354 6268 6128 5474 4660 4962 4597 3957 3769 3759 3480 3668 3362 2976 3152 3344 2851 3119 3033 2929 3159 3115 2863 3116 3134 2832 3113 2900 2918 3250 3208 2932 3093 3541 3132 3336 3424 3400 3590 3760 3345 3921 4032 3435 3795 3790 3795 4111 3942 3482 3812 3907 3470 3625 3609 3400 3505 3350 3001 3212 3124 2698 2893 2670 2497 2525 2190 1960 1931 2053 1609 1623 1589 1360 1362 1203 998 980 1024 795 841 695 690 608 553 469 499 434 363 295 302 236 257 221 203 205 158 135 132 114 86 97 78 66 66 59 47 51 29 44 30 28 21 22 21 12 16 16 18 8 2 9 7 7 4 2 2 3 4 3 1 0 1 1 1 1 1 3 1 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 32 max: 5247 count: 214720 average: 1200.28 | standard deviation: 897.454 | 87 1106 2991 4309 4753 4580 5489 6060 6086 6224 5800 5150 5536 5282 4467 4118 3895 3429 3374 2882 2551 2625 2521 2102 2121 1942 1817 1904 1812 1630 1712 1797 1527 1701 1611 1557 1703 1635 1506 1677 1713 1521 1677 1717 1561 1763 1672 1548 1765 1836 1675 1855 1872 1778 2030 1924 1834 2049 2203 1954 2108 2047 1955 2111 2113 1989 2148 2095 1934 2023 1955 1853 1933 1773 1629 1766 1734 1512 1466 1397 1345 1328 1207 1007 1109 1048 820 877 767 751 725 649 583 563 522 408 430 424 342 338 311 248 258 233 192 188 172 159 143 96 106 109 66 82 56 57 57 49 38 33 26 25 16 31 13 20 12 11 11 10 8 7 9 7 8 9 4 4 7 5 3 5 2 0 1 1 1 2 5 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 127 average: 2 | standard deviation: 0 | 0 0 127 ] -miss_latency_L2Cache: [binsize: 8 max: 1479 count: 548 average: 160.54 | standard deviation: 182.654 | 0 123 13 19 16 8 9 19 9 16 7 8 7 11 11 14 6 5 16 15 10 17 13 15 9 5 3 10 10 6 7 2 4 3 7 4 6 11 3 7 1 1 3 3 1 0 4 1 3 0 2 1 1 1 4 1 4 3 0 1 1 2 3 1 1 1 0 1 0 4 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_Directory: [binsize: 32 max: 5247 count: 592233 average: 1206.06 | standard deviation: 897.258 | 0 1530 7779 11438 12663 12155 15071 17152 17006 17363 16106 14306 15569 14890 12190 11597 11031 9508 9267 8135 7013 7404 6950 5853 5745 5548 5152 5417 4995 4471 4724 4997 4255 4651 4515 4316 4706 4576 4212 4634 4706 4200 4634 4473 4318 4859 4719 4317 4704 5205 4631 5001 5137 5002 5422 5488 4992 5743 6052 5184 5726 5651 5592 6035 5879 5295 5791 5825 5210 5487 5420 5089 5293 4979 4503 4854 4727 4078 4250 3965 3741 3766 3305 2881 2979 3018 2354 2444 2286 2068 2038 1804 1534 1510 1510 1173 1240 1100 1015 923 847 704 748 658 549 475 466 387 392 312 300 306 218 212 185 170 140 144 114 96 89 82 61 82 41 63 41 35 32 31 29 18 25 23 26 16 6 13 14 12 7 7 3 3 5 4 2 2 6 1 1 2 1 4 1 1 1 2 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache_wCC: [binsize: 32 max: 4563 count: 19828 average: 1068.68 | standard deviation: 895.348 | 0 1563 599 600 607 667 601 494 465 490 439 348 290 288 286 285 215 184 234 220 198 183 167 204 144 153 143 155 179 134 140 144 123 167 128 170 156 174 157 158 141 153 156 144 161 154 160 163 154 172 176 190 159 176 198 196 187 227 183 205 177 186 158 187 176 176 169 177 194 161 144 164 145 144 127 124 131 132 109 102 101 87 92 86 61 83 75 56 70 43 49 48 47 33 36 30 31 19 17 23 17 13 9 9 6 8 8 8 8 5 9 8 6 5 3 1 3 2 2 3 3 2 2 0 1 1 1 4 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 32 max: 4528 count: 19420 average: 987.434 | standard deviation: 888.941 | 2163 647 674 653 701 578 458 422 470 395 253 231 234 252 194 182 144 193 195 142 169 172 151 133 132 131 163 164 120 153 125 135 166 141 159 150 172 144 157 151 143 148 162 158 156 170 147 158 160 179 192 164 182 206 191 204 210 189 180 173 182 140 174 187 164 170 168 173 180 132 156 138 138 118 116 118 111 93 93 97 76 84 66 64 77 53 49 55 33 44 32 34 27 25 28 18 21 9 17 14 11 8 10 6 5 6 7 6 2 7 7 2 3 2 1 4 1 6 2 1 0 1 0 0 1 2 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 8 max: 936 count: 19420 average: 54.8861 | standard deviation: 97.0355 | 0 13582 459 147 146 199 175 200 206 151 201 186 146 193 180 134 181 215 137 182 178 125 149 119 80 110 108 59 90 95 66 74 70 57 69 97 67 76 71 51 46 49 37 29 30 16 24 25 16 25 19 19 16 15 16 17 25 17 12 4 8 8 11 2 6 9 2 8 7 3 7 7 5 3 7 3 1 0 2 2 3 0 4 1 3 2 1 2 4 3 1 0 1 0 0 0 1 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 42 count: 19420 average: 25.99 | standard deviation: 2.25509 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7947 1317 3874 1481 2161 1246 554 392 201 97 48 43 30 16 8 2 1 1 1 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 17 count: 19420 average: 1.88208 | standard deviation: 1.88333 | 4513 4905 4990 2707 612 569 566 138 217 59 58 47 11 9 13 4 0 2 ] -imcomplete_wCC_Times: 408 -miss_latency_dir_issue_to_initial_request: [binsize: 32 max: 4891 count: 592233 average: 987.318 | standard deviation: 887.301 | 65817 19189 19432 19942 21301 19131 15185 12634 13918 11686 8195 7704 7460 6430 6088 5603 4998 5538 5218 4392 4711 4869 4514 4544 4509 4240 4627 4646 4028 4391 4474 4290 4546 4506 4143 4616 4738 4076 4513 4559 4582 4778 4781 4361 5241 5327 4768 5343 5467 5344 5708 5703 5207 5981 6074 5529 6008 5899 5704 5907 5830 5347 5825 5595 5001 5249 5278 4914 4951 4658 4218 4422 4206 3482 3642 3364 3132 2964 2812 2437 2440 2374 1911 1915 1804 1652 1497 1303 1189 1185 1096 912 872 820 691 678 599 511 471 456 363 330 293 281 267 252 178 163 171 120 125 96 85 84 69 60 63 41 39 41 25 32 36 26 18 16 26 15 17 10 11 6 9 6 6 5 3 2 3 4 0 6 0 1 4 1 2 0 1 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_dir_initial_forward_request: [binsize: 4 max: 770 count: 592233 average: 10.3682 | standard deviation: 16.3806 | 0 0 511555 57481 13102 3602 2037 784 430 181 68 91 47 46 87 43 38 64 35 41 63 34 31 50 43 25 49 27 29 52 21 33 52 25 21 58 26 39 65 29 35 68 37 57 79 40 35 56 30 31 50 25 25 62 29 28 35 24 27 43 12 33 40 28 20 18 21 21 29 11 15 28 22 22 31 14 18 37 13 21 29 7 14 20 9 13 14 13 6 13 9 7 12 4 8 13 4 9 17 7 4 7 6 6 8 8 6 11 3 5 14 4 3 10 3 4 10 7 8 10 4 1 4 4 3 6 1 1 1 3 2 3 0 5 4 1 0 1 2 2 4 1 2 1 1 1 6 4 1 1 0 1 4 0 0 1 1 3 0 0 1 3 1 0 0 0 0 0 0 0 1 1 2 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 2 1 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 47 count: 592233 average: 26.1316 | standard deviation: 2.23073 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 216897 30944 143220 42998 77618 37781 14675 13788 6518 3286 2007 1212 508 425 174 84 52 25 8 9 2 0 0 2 ] -miss_latency_dir_first_response_to_completion: [binsize: 8 max: 1428 count: 592233 average: 182.245 | standard deviation: 133.806 | 0 66 7772 29752 20627 19395 22229 19459 17771 19230 16337 14774 17199 15173 14685 15887 13921 12967 14150 12652 11608 12905 12160 11302 13182 12461 12007 13592 13111 12161 12971 11216 9479 9261 7560 6244 6554 5636 5125 5566 4922 4490 4859 4274 4049 4375 3992 3681 3901 3445 2838 3002 2387 2165 2203 1794 1561 1791 1520 1408 1494 1378 1247 1332 1174 1039 1195 982 879 871 764 604 660 553 434 489 466 432 421 380 380 362 330 287 286 266 216 214 182 158 163 133 134 123 101 91 105 86 92 83 69 61 76 48 45 51 41 33 30 25 22 39 32 19 19 17 9 21 18 8 14 17 7 13 9 12 6 5 10 3 9 10 6 5 3 4 4 1 2 3 1 2 1 0 1 2 0 2 0 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 32 max: 5202 count: 613664 average: 1200.01 | standard deviation: 895.83 | 310 3143 8082 11832 13251 12764 15678 17486 17568 18109 16688 14788 15903 15401 12287 11695 11313 10132 9781 8347 7359 7627 7125 5924 6016 5838 5439 5648 5080 4635 5191 5022 4494 4677 4612 4370 4952 4667 4256 4660 4822 4415 4570 4783 4438 4937 4855 4493 5056 5394 4843 5197 5461 5113 5694 5536 5181 5923 6015 5648 5978 6092 5565 6367 6003 5670 5859 6161 5450 5701 5525 5291 5629 5101 4645 4956 4827 4055 4157 4017 3747 3776 3369 3031 3201 3071 2515 2487 2384 2126 2027 1880 1629 1619 1520 1300 1239 1160 952 940 833 676 711 670 548 495 469 358 412 321 268 300 267 187 190 150 169 148 132 91 90 79 72 68 51 49 51 47 29 19 31 17 15 14 13 18 14 7 10 5 9 2 2 0 3 2 3 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 5202 count: 398481 average: 1200.19 | standard deviation: 896.119 | 211 2047 5278 7623 8631 8283 10182 11392 11413 11756 10890 9465 10364 10032 8054 7646 7388 6499 6371 5423 4795 4965 4577 3805 3874 3815 3533 3582 3291 3017 3356 3211 2925 2995 2975 2804 3210 3006 2773 2999 3119 2931 2985 3108 2910 3215 3122 2953 3289 3525 3180 3324 3529 3331 3730 3543 3376 3856 3890 3654 3870 3997 3626 4199 3918 3686 3805 4043 3541 3742 3578 3419 3611 3306 2944 3205 3063 2602 2763 2633 2479 2525 2173 1964 2127 1955 1610 1643 1516 1374 1296 1228 1073 1030 972 841 811 731 633 636 557 417 477 413 372 325 296 225 274 216 181 193 174 117 126 90 120 99 77 62 56 49 56 53 37 28 33 29 15 9 24 13 9 10 7 12 9 3 6 4 7 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 32 max: 4722 count: 215183 average: 1199.68 | standard deviation: 895.297 | 99 1096 2804 4209 4620 4481 5496 6094 6155 6353 5798 5323 5539 5369 4233 4049 3925 3633 3410 2924 2564 2662 2548 2119 2142 2023 1906 2066 1789 1618 1835 1811 1569 1682 1637 1566 1742 1661 1483 1661 1703 1484 1585 1675 1528 1722 1733 1540 1767 1869 1663 1873 1932 1782 1964 1993 1805 2067 2125 1994 2108 2095 1939 2168 2085 1984 2054 2118 1909 1959 1947 1872 2018 1795 1701 1751 1764 1453 1394 1384 1268 1251 1196 1067 1074 1116 905 844 868 752 731 652 556 589 548 459 428 429 319 304 276 259 234 257 176 170 173 133 138 105 87 107 93 70 64 60 49 49 55 29 34 30 16 15 14 21 18 18 14 10 7 4 6 4 6 6 5 4 4 1 2 1 1 0 2 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 137 average: 2 | standard deviation: 0 | 0 0 137 ] +miss_latency_L2Cache: [binsize: 16 max: 1794 count: 593 average: 164.138 | standard deviation: 183.747 | 139 34 32 25 21 15 23 19 24 27 20 19 20 12 8 18 14 7 27 9 7 7 3 11 5 2 7 5 1 2 1 1 1 0 2 0 3 1 1 3 0 1 3 0 3 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 32 max: 5202 count: 593182 average: 1205.69 | standard deviation: 895.367 | 0 1586 7504 11249 12628 11995 14978 16965 17041 17570 16228 14406 15580 15083 11992 11456 11087 9900 9569 8159 7159 7452 6961 5722 5873 5659 5286 5506 4956 4497 5046 4869 4338 4532 4474 4242 4806 4528 4123 4509 4680 4250 4422 4619 4292 4765 4660 4331 4890 5246 4654 5001 5271 4950 5511 5321 5017 5723 5820 5460 5783 5878 5367 6186 5842 5501 5682 5985 5257 5535 5351 5129 5490 4957 4515 4811 4691 3944 4044 3932 3645 3695 3281 2958 3138 3002 2441 2433 2315 2081 1986 1834 1579 1584 1491 1266 1218 1138 936 925 819 657 693 658 537 487 461 351 407 315 261 294 265 185 184 146 166 145 129 90 90 78 71 66 49 46 50 45 28 19 31 16 15 14 13 18 14 7 10 5 9 2 2 0 3 2 3 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 32 max: 4219 count: 19752 average: 1068.92 | standard deviation: 892.068 | 0 1500 542 541 572 730 668 495 506 503 446 368 316 306 292 237 225 230 208 184 199 172 160 201 143 177 152 141 123 137 145 153 156 144 138 128 146 139 133 151 142 165 148 164 146 172 195 162 166 148 189 196 190 163 183 215 163 200 195 188 195 214 198 181 161 169 177 176 193 166 174 162 139 144 130 145 136 111 113 85 102 81 88 73 63 69 74 54 69 45 41 46 50 35 29 34 21 22 16 15 14 19 18 12 11 8 8 7 5 6 7 6 2 2 6 4 3 3 3 1 0 1 1 2 2 3 1 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 32 max: 4183 count: 19313 average: 985.329 | standard deviation: 886.676 | 2149 579 634 628 719 645 524 428 495 368 272 253 238 218 191 183 206 151 160 162 149 152 157 142 146 132 117 136 128 144 143 138 153 148 114 145 160 109 161 149 145 158 143 143 190 197 146 178 173 172 195 195 168 204 219 169 185 194 164 187 196 189 170 166 163 173 172 168 178 154 144 152 127 109 131 120 92 97 78 86 84 73 59 46 59 60 49 57 31 36 44 38 25 27 22 22 19 13 15 13 11 11 11 6 8 7 10 4 5 3 3 1 2 5 3 1 2 0 1 2 2 0 1 3 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 8 max: 950 count: 19313 average: 56.7199 | standard deviation: 97.435 | 0 13310 442 114 161 233 154 184 212 147 214 216 161 167 179 156 163 226 158 197 188 128 165 138 92 100 101 81 110 110 60 93 104 62 85 79 58 67 61 37 60 31 27 26 33 21 26 33 17 21 28 22 20 21 12 19 14 13 10 14 10 12 11 8 9 2 4 8 7 4 10 3 5 7 1 0 3 2 3 1 2 2 3 3 1 1 1 0 3 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 41 count: 19313 average: 25.9263 | standard deviation: 2.21351 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8116 1323 3886 1441 1965 1234 559 398 187 86 47 25 19 17 5 1 3 1 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 17 count: 19313 average: 1.88257 | standard deviation: 1.91568 | 4546 4954 4784 2717 626 538 586 138 208 47 64 58 10 15 8 9 3 2 ] +imcomplete_wCC_Times: 439 +miss_latency_dir_issue_to_initial_request: [binsize: 32 max: 4586 count: 593182 average: 986.63 | standard deviation: 885.787 | 65189 19366 19340 19827 21303 19141 15526 12545 14038 11922 8356 7818 7511 6734 6275 5670 4950 5454 5387 4478 4655 4821 4584 4637 4510 4320 4645 4630 3947 4297 4379 4320 4472 4333 4154 4707 4562 4110 4471 4639 4646 4835 4683 4549 5116 5239 4743 5325 5492 5428 5740 5698 5149 6118 5985 5461 5917 6047 5873 5996 5964 5282 5825 5983 4980 5217 5296 4877 4856 4625 4100 4294 4131 3436 3605 3440 3083 3010 2731 2464 2626 2412 1867 1979 1840 1657 1563 1372 1199 1213 1093 870 833 779 707 687 588 466 457 444 313 343 303 266 282 198 169 190 148 134 113 108 95 82 61 57 56 50 39 34 35 22 31 13 16 20 14 16 10 13 8 6 3 2 5 3 2 2 1 2 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_initial_forward_request: [binsize: 8 max: 917 count: 593182 average: 10.3807 | standard deviation: 16.8035 | 0 569858 16907 2750 635 186 88 105 102 64 88 76 70 79 63 44 55 82 66 102 135 87 105 81 64 86 86 59 65 61 53 51 39 37 49 47 32 50 36 37 49 52 25 27 22 18 19 21 9 18 13 11 16 15 8 9 19 5 15 10 9 11 8 4 8 3 4 3 4 3 3 6 3 3 5 6 5 5 3 0 2 1 3 2 3 0 1 0 0 0 3 2 1 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 46 count: 593182 average: 26.1256 | standard deviation: 2.22568 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 218041 30550 143633 42965 77674 37667 14693 13940 6365 3242 1985 1159 495 418 183 84 51 23 5 5 3 0 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 8 max: 1271 count: 593182 average: 182.549 | standard deviation: 133.92 | 0 58 7895 29521 20408 19267 22130 19636 17656 19579 16143 14667 17121 15571 14699 16106 14005 13032 14137 12531 11638 12938 12000 11233 12963 12580 12165 13967 12888 11924 13132 11297 9628 9573 7312 6352 6752 5597 5093 5550 4926 4364 4897 4410 4126 4555 3972 3578 3907 3417 2888 2919 2386 2090 2178 1856 1618 1758 1579 1380 1554 1414 1251 1353 1150 1058 1119 1061 858 894 721 618 614 572 512 506 451 425 438 372 360 374 311 274 295 244 239 223 183 153 169 159 107 145 134 91 102 86 85 83 85 67 74 63 46 64 33 35 35 31 28 24 27 21 25 23 22 18 12 20 9 6 10 7 9 7 11 4 4 3 8 5 1 5 1 4 7 1 5 3 1 1 0 2 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 91 average: 2 | standard deviation: 0 | 0 0 91 ] -miss_latency_LD_L2Cache: [binsize: 8 max: 1248 count: 352 average: 161.239 | standard deviation: 178.299 | 0 83 9 12 10 4 6 11 5 9 4 6 2 8 6 7 6 5 7 9 8 8 12 9 4 2 3 9 7 5 4 0 2 1 6 4 2 7 1 6 1 1 1 2 0 0 4 1 2 0 2 1 0 1 3 0 2 1 0 1 1 2 2 1 0 1 0 0 0 2 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_Directory: [binsize: 32 max: 5181 count: 384716 average: 1206.09 | standard deviation: 897.485 | 0 991 5024 7375 8161 7819 9801 11271 11091 11317 10467 9288 10131 9720 7829 7579 7213 6144 5971 5326 4526 4844 4485 3829 3677 3666 3373 3559 3244 2891 3061 3250 2772 2999 2953 2823 3061 2996 2756 3012 3046 2737 3010 2811 2811 3150 3095 2811 2999 3430 3012 3222 3322 3281 3455 3638 3216 3779 3912 3306 3687 3660 3695 3984 3816 3369 3698 3789 3351 3523 3523 3299 3407 3265 2919 3133 3040 2611 2819 2603 2434 2478 2126 1912 1902 1998 1557 1582 1538 1328 1329 1171 966 960 998 779 819 684 678 597 545 458 493 429 361 290 296 232 254 217 196 199 153 133 130 114 85 95 77 63 63 57 45 51 28 43 29 25 21 22 21 11 16 16 18 7 2 9 7 7 4 2 2 3 4 3 1 0 1 1 1 1 1 3 1 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 4349 count: 12857 average: 1070.69 | standard deviation: 893.771 | 0 1017 379 374 371 441 391 324 299 323 281 217 193 179 184 186 140 121 156 147 134 118 111 127 91 93 105 109 118 84 91 94 79 120 79 106 98 119 107 103 88 95 103 89 107 100 113 121 94 111 120 114 102 119 135 122 129 142 120 129 108 130 100 127 126 113 114 118 119 102 86 101 98 85 82 79 84 87 74 67 63 47 64 48 29 55 52 41 51 32 33 32 32 20 26 16 22 11 12 11 8 11 6 5 2 5 6 4 3 4 7 6 5 2 2 0 1 2 1 3 3 2 2 0 1 1 1 3 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 36 average: 2 | standard deviation: 0 | 0 0 36 ] -miss_latency_ST_L2Cache: [binsize: 8 max: 1479 count: 196 average: 159.286 | standard deviation: 190.685 | 0 40 4 7 6 4 3 8 4 7 3 2 5 3 5 7 0 0 9 6 2 9 1 6 5 3 0 1 3 1 3 2 2 2 1 0 4 4 2 1 0 0 2 1 1 0 0 0 1 0 0 0 1 0 1 1 2 2 0 0 0 0 1 0 1 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_ST_Directory: [binsize: 32 max: 5247 count: 207517 average: 1206.02 | standard deviation: 896.84 | 0 539 2755 4063 4502 4336 5270 5881 5915 6046 5639 5018 5438 5170 4361 4018 3818 3364 3296 2809 2487 2560 2465 2024 2068 1882 1779 1858 1751 1580 1663 1747 1483 1652 1562 1493 1645 1580 1456 1622 1660 1463 1624 1662 1507 1709 1624 1506 1705 1775 1619 1779 1815 1721 1967 1850 1776 1964 2140 1878 2039 1991 1897 2051 2063 1926 2093 2036 1859 1964 1897 1790 1886 1714 1584 1721 1687 1467 1431 1362 1307 1288 1179 969 1077 1020 797 862 748 740 709 633 568 550 512 394 421 416 337 326 302 246 255 229 188 185 170 155 138 95 104 107 65 79 55 56 55 49 37 33 26 25 16 31 13 20 12 10 11 9 8 7 9 7 8 9 4 4 7 5 3 5 1 0 1 1 1 2 5 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 4563 count: 6971 average: 1064.97 | standard deviation: 898.304 | 0 546 220 226 236 226 210 170 166 167 158 131 97 109 102 99 75 63 78 73 64 65 56 77 53 60 38 46 61 50 49 50 44 47 49 64 58 55 50 55 53 58 53 55 54 54 47 42 60 61 56 76 57 57 63 74 58 85 63 76 69 56 58 60 50 63 55 59 75 59 58 63 47 59 45 45 47 45 35 35 38 40 28 38 32 28 23 15 19 11 16 16 15 13 10 14 9 8 5 12 9 2 3 4 4 3 2 4 5 1 2 2 1 3 1 1 2 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 87 average: 2 | standard deviation: 0 | 0 0 87 ] +miss_latency_LD_L2Cache: [binsize: 16 max: 1794 count: 404 average: 157.589 | standard deviation: 187.366 | 102 22 25 19 14 10 13 14 16 20 14 11 6 9 8 14 8 5 18 7 2 4 3 7 3 1 5 4 1 2 1 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 32 max: 5202 count: 385143 average: 1206.1 | standard deviation: 895.6 | 0 1010 4911 7231 8210 7778 9727 11044 11072 11412 10598 9217 10160 9822 7856 7489 7227 6355 6237 5307 4669 4846 4467 3681 3782 3692 3434 3492 3208 2931 3261 3106 2825 2910 2880 2720 3112 2922 2687 2903 3027 2818 2888 2998 2811 3105 3004 2849 3179 3420 3054 3203 3419 3226 3613 3404 3276 3728 3762 3524 3746 3858 3499 4083 3821 3576 3690 3936 3415 3630 3463 3315 3521 3208 2864 3117 2975 2530 2693 2578 2412 2461 2124 1917 2086 1909 1559 1609 1469 1347 1266 1194 1042 1007 952 827 799 717 623 625 546 404 465 406 365 321 291 223 269 211 174 190 173 117 124 87 117 96 76 61 56 48 55 51 35 26 33 27 15 9 24 12 9 10 7 12 9 3 6 4 7 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 4219 count: 12847 average: 1063.66 | standard deviation: 892.729 | 0 993 343 365 385 480 440 326 328 319 286 238 200 201 195 155 160 143 133 114 126 118 108 124 92 122 98 89 82 85 95 105 100 84 95 84 98 84 86 96 92 113 97 110 99 110 118 104 110 105 126 121 110 105 117 139 99 128 128 130 124 139 127 116 97 110 115 107 126 112 115 104 90 98 80 88 88 72 70 55 67 64 49 47 41 46 51 34 47 27 30 34 31 23 20 14 12 14 10 11 11 13 12 7 7 4 5 2 5 5 7 3 1 0 2 3 3 3 1 1 0 1 1 2 2 2 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 50 average: 2 | standard deviation: 0 | 0 0 50 ] +miss_latency_ST_L2Cache: [binsize: 8 max: 816 count: 189 average: 178.138 | standard deviation: 175.426 | 0 37 2 10 3 4 4 2 1 6 2 3 8 2 2 3 5 3 4 3 2 4 5 3 8 6 2 1 0 0 1 3 3 3 0 2 4 5 1 1 2 3 0 3 0 0 3 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 2 0 0 0 1 2 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 32 max: 4722 count: 208039 average: 1204.91 | standard deviation: 894.937 | 0 576 2593 4018 4418 4217 5251 5921 5969 6158 5630 5189 5420 5261 4136 3967 3860 3545 3332 2852 2490 2606 2494 2041 2091 1967 1852 2014 1748 1566 1785 1763 1513 1622 1594 1522 1694 1606 1436 1606 1653 1432 1534 1621 1481 1660 1656 1482 1711 1826 1600 1798 1852 1724 1898 1917 1741 1995 2058 1936 2037 2020 1868 2103 2021 1925 1992 2049 1842 1905 1888 1814 1969 1749 1651 1694 1716 1414 1351 1354 1233 1234 1157 1041 1052 1093 882 824 846 734 720 640 537 577 539 439 419 421 313 300 273 253 228 252 172 166 170 128 138 104 87 104 92 68 60 59 49 49 53 29 34 30 16 15 14 20 17 18 13 10 7 4 6 4 6 6 5 4 4 1 2 1 1 0 2 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 4104 count: 6905 average: 1078.69 | standard deviation: 890.819 | 0 507 199 176 187 250 228 169 178 184 160 130 116 105 97 82 65 87 75 70 73 54 52 77 51 55 54 52 41 52 50 48 56 60 43 44 48 55 47 55 50 52 51 54 47 62 77 58 56 43 63 75 80 58 66 76 64 72 67 58 71 75 71 65 64 59 62 69 67 54 59 58 49 46 50 57 48 39 43 30 35 17 39 26 22 23 23 20 22 18 11 12 19 12 9 20 9 8 6 4 3 6 6 5 4 4 3 5 0 1 0 3 1 2 4 1 0 0 2 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -88,242 +88,242 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 120 +user_time: 129 system_time: 0 -page_reclaims: 9010 +page_reclaims: 9989 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 240 +block_outputs: 304 Network Stats ------------- -total_msg_count_Request_Control: 1837479 14699832 -total_msg_count_Response_Data: 1836177 132204744 -total_msg_count_Response_Control: 12786852 102294816 -total_msg_count_Writeback_Data: 636269 45811368 -total_msg_count_Writeback_Control: 4557561 36460488 -total_msg_count_Broadcast_Control: 9175149 73401192 -total_msg_count_Unblock_Control: 1836832 14694656 -total_msgs: 32666319 total_bytes: 419567096 +total_msg_count_Request_Control: 1840181 14721448 +total_msg_count_Response_Data: 1838796 132393312 +total_msg_count_Response_Control: 12804776 102438208 +total_msg_count_Writeback_Data: 637479 45898488 +total_msg_count_Writeback_Control: 4564388 36515104 +total_msg_count_Broadcast_Control: 9187682 73501456 +total_msg_count_Unblock_Control: 1839451 14715608 +total_msgs: 32712753 total_bytes: 420183624 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 12.5722 - links_utilized_percent_switch_0_link_0: 15.8935 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 9.25087 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 35 280 [ 0 0 0 35 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 76393 5500296 [ 0 0 0 0 76393 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 531958 4255664 [ 0 0 0 0 531958 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 72037 576296 [ 0 0 0 72037 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Broadcast_Control: 535334 4282672 [ 0 0 0 535334 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 76397 611176 [ 0 0 76397 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 2477 178344 [ 0 0 0 0 2477 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 532890 4263120 [ 0 0 0 0 532890 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 26414 1901808 [ 0 0 0 0 0 26414 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 117622 940976 [ 0 0 72037 0 0 45585 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 76429 611432 [ 0 0 0 0 0 76429 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 12.5572 + links_utilized_percent_switch_0_link_0: 15.877 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 9.23753 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 67 536 [ 0 0 0 67 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 76342 5496624 [ 0 0 0 0 76342 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 531655 4253240 [ 0 0 0 0 531655 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 72091 576728 [ 0 0 0 72091 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 536217 4289736 [ 0 0 0 536217 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 76346 610768 [ 0 0 76346 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 2434 175248 [ 0 0 0 0 2434 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 533848 4270784 [ 0 0 0 0 533848 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 26303 1893816 [ 0 0 0 0 0 26303 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 117853 942824 [ 0 0 72091 0 0 45762 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 76368 610944 [ 0 0 0 0 0 76368 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 12.568 - links_utilized_percent_switch_1_link_0: 15.8915 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 9.24449 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 52 416 [ 0 0 0 52 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 76373 5498856 [ 0 0 0 0 76373 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 531841 4254728 [ 0 0 0 0 531841 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 72068 576544 [ 0 0 0 72068 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Broadcast_Control: 535355 4282840 [ 0 0 0 535355 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 76376 611008 [ 0 0 76376 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 2436 175392 [ 0 0 0 0 2436 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 532967 4263736 [ 0 0 0 0 532967 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 26356 1897632 [ 0 0 0 0 0 26356 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 117749 941992 [ 0 0 72068 0 0 45681 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 76404 611232 [ 0 0 0 0 0 76404 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 12.6101 + links_utilized_percent_switch_1_link_0: 15.9418 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 9.27836 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 47 376 [ 0 0 0 47 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 76812 5530464 [ 0 0 0 0 76812 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 534988 4279904 [ 0 0 0 0 534988 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 72482 579856 [ 0 0 0 72482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 535741 4285928 [ 0 0 0 535741 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 76815 614520 [ 0 0 76815 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 2487 179064 [ 0 0 0 0 2487 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 533299 4266392 [ 0 0 0 0 533299 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 26684 1921248 [ 0 0 0 0 0 26684 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 118248 945984 [ 0 0 72482 0 0 45766 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 76845 614760 [ 0 0 0 0 0 76845 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 12.5919 - links_utilized_percent_switch_2_link_0: 15.9195 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 9.26437 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 64 512 [ 0 0 0 64 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 76578 5513616 [ 0 0 0 0 76578 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 533340 4266720 [ 0 0 0 0 533340 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 72141 577128 [ 0 0 0 72141 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Broadcast_Control: 535143 4281144 [ 0 0 0 535143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 76582 612656 [ 0 0 76582 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 2491 179352 [ 0 0 0 0 2491 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 532712 4261696 [ 0 0 0 0 532712 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 26542 1911024 [ 0 0 0 0 0 26542 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 117716 941728 [ 0 0 72141 0 0 45575 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 76602 612816 [ 0 0 0 0 0 76602 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 12.593 + links_utilized_percent_switch_2_link_0: 15.9211 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 9.26484 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 56 448 [ 0 0 0 56 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 76669 5520168 [ 0 0 0 0 76669 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 533919 4271352 [ 0 0 0 0 533919 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 72300 578400 [ 0 0 0 72300 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 535894 4287152 [ 0 0 0 535894 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 76670 613360 [ 0 0 76670 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2480 178560 [ 0 0 0 0 2480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 533468 4267744 [ 0 0 0 0 533468 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 26558 1912176 [ 0 0 0 0 0 26558 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 118010 944080 [ 0 0 72300 0 0 45710 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 76700 613600 [ 0 0 0 0 0 76700 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 12.573 - links_utilized_percent_switch_3_link_0: 15.8996 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 9.24651 bw: 16000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 51 408 [ 0 0 0 51 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 76442 5503824 [ 0 0 0 0 76442 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 532240 4257920 [ 0 0 0 0 532240 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 72049 576392 [ 0 0 0 72049 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Broadcast_Control: 535287 4282296 [ 0 0 0 535287 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 76443 611544 [ 0 0 76443 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 2405 173160 [ 0 0 0 0 2405 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 532929 4263432 [ 0 0 0 0 532929 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 26413 1901736 [ 0 0 0 0 0 26413 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 117652 941216 [ 0 0 72049 0 0 45603 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 76474 611792 [ 0 0 0 0 0 76474 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 12.6046 + links_utilized_percent_switch_3_link_0: 15.9317 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 9.27746 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 60 480 [ 0 0 0 60 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 76743 5525496 [ 0 0 0 0 76743 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 534429 4275432 [ 0 0 0 0 534429 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 72404 579232 [ 0 0 0 72404 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 535830 4286640 [ 0 0 0 535830 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 76747 613976 [ 0 0 76747 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 2456 176832 [ 0 0 0 0 2456 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 533432 4267456 [ 0 0 0 0 533432 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 26726 1924272 [ 0 0 0 0 0 26726 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 118059 944472 [ 0 0 72406 0 0 45653 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 76767 614136 [ 0 0 0 0 0 76767 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 12.5812 - links_utilized_percent_switch_4_link_0: 15.8978 bw: 16000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 9.26465 bw: 16000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 45 360 [ 0 0 0 45 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 76416 5501952 [ 0 0 0 0 76416 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 532263 4258104 [ 0 0 0 0 532263 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 72051 576408 [ 0 0 0 72051 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Broadcast_Control: 535299 4282392 [ 0 0 0 535299 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 76419 611352 [ 0 0 76419 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 2481 178632 [ 0 0 0 0 2481 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 532859 4262872 [ 0 0 0 0 532859 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Data: 26602 1915344 [ 0 0 0 0 0 26602 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Control: 117475 939800 [ 0 0 72051 0 0 45424 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 76442 611536 [ 0 0 0 0 0 76442 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 12.5842 + links_utilized_percent_switch_4_link_0: 15.9128 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 9.25567 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 48 384 [ 0 0 0 48 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 76610 5515920 [ 0 0 0 0 76610 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 533452 4267616 [ 0 0 0 0 533452 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 72283 578264 [ 0 0 0 72283 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 535962 4287696 [ 0 0 0 535962 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 76613 612904 [ 0 0 76613 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 2461 177192 [ 0 0 0 0 2461 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 533547 4268376 [ 0 0 0 0 533547 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 26456 1904832 [ 0 0 0 0 0 26456 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 118081 944648 [ 0 0 72285 0 0 45796 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 76641 613128 [ 0 0 0 0 0 76641 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 12.5868 - links_utilized_percent_switch_5_link_0: 15.9069 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 9.26682 bw: 16000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Request_Control: 56 448 [ 0 0 0 56 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 76494 5507568 [ 0 0 0 0 76494 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 532599 4260792 [ 0 0 0 0 532599 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 72112 576896 [ 0 0 0 72112 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Broadcast_Control: 535231 4281848 [ 0 0 0 535231 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 76498 611984 [ 0 0 76498 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 2537 182664 [ 0 0 0 0 2537 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 532746 4261968 [ 0 0 0 0 532746 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Data: 26550 1911600 [ 0 0 0 0 0 26550 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Control: 117645 941160 [ 0 0 72112 0 0 45533 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 76522 612176 [ 0 0 0 0 0 76522 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 12.5724 + links_utilized_percent_switch_5_link_0: 15.8881 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 9.25681 bw: 16000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Request_Control: 51 408 [ 0 0 0 51 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 76439 5503608 [ 0 0 0 0 76439 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 532208 4257664 [ 0 0 0 0 532208 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 72039 576312 [ 0 0 0 72039 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 536137 4289096 [ 0 0 0 536137 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 76441 611528 [ 0 0 76441 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 2493 179496 [ 0 0 0 0 2493 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 533695 4269560 [ 0 0 0 0 533695 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 26522 1909584 [ 0 0 0 0 0 26522 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 117528 940224 [ 0 0 72040 0 0 45488 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 76467 611736 [ 0 0 0 0 0 76467 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 12.5735 - links_utilized_percent_switch_6_link_0: 15.8851 bw: 16000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 9.26202 bw: 16000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 51 408 [ 0 0 0 51 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 76327 5495544 [ 0 0 0 0 76327 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 531538 4252304 [ 0 0 0 0 531538 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 72005 576040 [ 0 0 0 72005 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Broadcast_Control: 535400 4283200 [ 0 0 0 535400 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 76333 610664 [ 0 0 76333 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 2495 179640 [ 0 0 0 0 2495 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 532954 4263632 [ 0 0 0 0 532954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Data: 26570 1913040 [ 0 0 0 0 0 26570 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Control: 117421 939368 [ 0 0 72005 0 0 45416 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 76346 610768 [ 0 0 0 0 0 76346 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 12.6244 + links_utilized_percent_switch_6_link_0: 15.9615 bw: 16000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 9.28737 bw: 16000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 52 416 [ 0 0 0 52 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 76957 5540904 [ 0 0 0 0 76957 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 535964 4287712 [ 0 0 0 0 535964 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 72613 580904 [ 0 0 0 72613 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 535597 4284776 [ 0 0 0 535597 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 76961 615688 [ 0 0 76961 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 2459 177048 [ 0 0 0 0 2459 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 533188 4265504 [ 0 0 0 0 533188 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 26790 1928880 [ 0 0 0 0 0 26790 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 118407 947256 [ 0 0 72613 0 0 45794 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 76986 615888 [ 0 0 0 0 0 76986 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 12.6348 - links_utilized_percent_switch_7_link_0: 15.9835 bw: 16000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 9.28599 bw: 16000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 54 432 [ 0 0 0 54 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 77035 5546520 [ 0 0 0 0 77035 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 536498 4291984 [ 0 0 0 0 536498 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 72704 581632 [ 0 0 0 72704 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Broadcast_Control: 534687 4277496 [ 0 0 0 534687 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 77037 616296 [ 0 0 77037 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 2504 180288 [ 0 0 0 0 2504 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 532236 4257888 [ 0 0 0 0 532236 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Data: 26643 1918296 [ 0 0 0 0 0 26643 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Control: 118740 949920 [ 0 0 72704 0 0 46036 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 77059 616472 [ 0 0 0 0 0 77059 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 12.5615 + links_utilized_percent_switch_7_link_0: 15.876 bw: 16000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 9.24708 bw: 16000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 58 464 [ 0 0 0 58 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 76360 5497920 [ 0 0 0 0 76360 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 531643 4253144 [ 0 0 0 0 531643 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 71845 574760 [ 0 0 0 71845 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 536206 4289648 [ 0 0 0 536206 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 76363 610904 [ 0 0 76363 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 2480 178560 [ 0 0 0 0 2480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 533782 4270256 [ 0 0 0 0 533782 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 26454 1904688 [ 0 0 0 0 0 26454 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 117219 937752 [ 0 0 71845 0 0 45374 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 76377 611016 [ 0 0 0 0 0 76377 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 46.0845 - links_utilized_percent_switch_8_link_0: 35.4528 bw: 16000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 56.7163 bw: 16000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Request_Control: 612085 4896680 [ 0 0 612085 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Data: 212089 15270408 [ 0 0 0 0 0 212089 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Control: 942020 7536160 [ 0 0 577167 0 0 364853 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 612277 4898216 [ 0 0 0 0 0 612277 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 408 3264 [ 0 0 0 408 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 592234 42640848 [ 0 0 0 0 592234 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 577167 4617336 [ 0 0 0 577167 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Broadcast_Control: 611677 4893416 [ 0 0 0 611677 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 46.1056 + links_utilized_percent_switch_8_link_0: 35.4707 bw: 16000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 56.7405 bw: 16000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 612953 4903624 [ 0 0 612953 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 212493 15299496 [ 0 0 0 0 0 212493 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 943403 7547224 [ 0 0 578060 0 0 365343 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 613150 4905200 [ 0 0 0 0 0 613150 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 439 3512 [ 0 0 0 439 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 593182 42709104 [ 0 0 0 0 593182 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 578060 4624480 [ 0 0 0 578060 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Broadcast_Control: 612514 4900112 [ 0 0 0 612514 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 18.0811 - links_utilized_percent_switch_9_link_0: 15.8935 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 15.8915 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 15.9195 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 15.8996 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 15.8978 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 15.9069 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 15.8851 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 15.9836 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 35.4528 bw: 16000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Request_Control: 35 280 [ 0 0 0 35 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Data: 76393 5500296 [ 0 0 0 0 76393 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 531958 4255664 [ 0 0 0 0 531958 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 72037 576296 [ 0 0 0 72037 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Broadcast_Control: 535334 4282672 [ 0 0 0 535334 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Request_Control: 52 416 [ 0 0 0 52 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 76373 5498856 [ 0 0 0 0 76373 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 531841 4254728 [ 0 0 0 0 531841 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 72068 576544 [ 0 0 0 72068 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Broadcast_Control: 535355 4282840 [ 0 0 0 535355 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Request_Control: 64 512 [ 0 0 0 64 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 76578 5513616 [ 0 0 0 0 76578 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Control: 533340 4266720 [ 0 0 0 0 533340 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Writeback_Control: 72141 577128 [ 0 0 0 72141 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Broadcast_Control: 535143 4281144 [ 0 0 0 535143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Request_Control: 51 408 [ 0 0 0 51 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 76442 5503824 [ 0 0 0 0 76442 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Control: 532240 4257920 [ 0 0 0 0 532240 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Writeback_Control: 72049 576392 [ 0 0 0 72049 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Broadcast_Control: 535287 4282296 [ 0 0 0 535287 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Request_Control: 45 360 [ 0 0 0 45 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 76416 5501952 [ 0 0 0 0 76416 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Control: 532263 4258104 [ 0 0 0 0 532263 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Writeback_Control: 72051 576408 [ 0 0 0 72051 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Broadcast_Control: 535299 4282392 [ 0 0 0 535299 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Request_Control: 56 448 [ 0 0 0 56 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 76494 5507568 [ 0 0 0 0 76494 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Control: 532603 4260824 [ 0 0 0 0 532603 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Writeback_Control: 72112 576896 [ 0 0 0 72112 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Broadcast_Control: 535231 4281848 [ 0 0 0 535231 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Request_Control: 51 408 [ 0 0 0 51 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 76328 5495616 [ 0 0 0 0 76328 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Control: 531538 4252304 [ 0 0 0 0 531538 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Writeback_Control: 72005 576040 [ 0 0 0 72005 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Broadcast_Control: 535400 4283200 [ 0 0 0 535400 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Request_Control: 54 432 [ 0 0 0 54 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 77035 5546520 [ 0 0 0 0 77035 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Control: 536499 4291992 [ 0 0 0 0 536499 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Writeback_Control: 72704 581632 [ 0 0 0 72704 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Broadcast_Control: 534687 4277496 [ 0 0 0 534687 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Request_Control: 612085 4896680 [ 0 0 612085 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Writeback_Data: 212090 15270480 [ 0 0 0 0 0 212090 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Writeback_Control: 942020 7536160 [ 0 0 577167 0 0 364853 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Unblock_Control: 612277 4898216 [ 0 0 0 0 0 612277 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 18.0867 + links_utilized_percent_switch_9_link_0: 15.877 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 15.9418 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 15.9211 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 15.9317 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 15.9128 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 15.8881 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 15.9615 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 15.876 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 35.4708 bw: 16000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 67 536 [ 0 0 0 67 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 76342 5496624 [ 0 0 0 0 76342 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 531655 4253240 [ 0 0 0 0 531655 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 72091 576728 [ 0 0 0 72091 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Broadcast_Control: 536217 4289736 [ 0 0 0 536217 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Request_Control: 47 376 [ 0 0 0 47 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 76812 5530464 [ 0 0 0 0 76812 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 534988 4279904 [ 0 0 0 0 534988 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 72482 579856 [ 0 0 0 72482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Broadcast_Control: 535741 4285928 [ 0 0 0 535741 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Request_Control: 56 448 [ 0 0 0 56 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 76669 5520168 [ 0 0 0 0 76669 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Control: 533919 4271352 [ 0 0 0 0 533919 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 72300 578400 [ 0 0 0 72300 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Broadcast_Control: 535894 4287152 [ 0 0 0 535894 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Request_Control: 60 480 [ 0 0 0 60 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 76743 5525496 [ 0 0 0 0 76743 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Control: 534430 4275440 [ 0 0 0 0 534430 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 72404 579232 [ 0 0 0 72404 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Broadcast_Control: 535830 4286640 [ 0 0 0 535830 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Request_Control: 48 384 [ 0 0 0 48 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 76610 5515920 [ 0 0 0 0 76610 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Control: 533452 4267616 [ 0 0 0 0 533452 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 72283 578264 [ 0 0 0 72283 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Broadcast_Control: 535962 4287696 [ 0 0 0 535962 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Request_Control: 51 408 [ 0 0 0 51 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 76439 5503608 [ 0 0 0 0 76439 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Control: 532208 4257664 [ 0 0 0 0 532208 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 72040 576320 [ 0 0 0 72040 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Broadcast_Control: 536137 4289096 [ 0 0 0 536137 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Request_Control: 52 416 [ 0 0 0 52 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 76957 5540904 [ 0 0 0 0 76957 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Control: 535964 4287712 [ 0 0 0 0 535964 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 72613 580904 [ 0 0 0 72613 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Broadcast_Control: 535597 4284776 [ 0 0 0 535597 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Request_Control: 58 464 [ 0 0 0 58 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 76360 5497920 [ 0 0 0 0 76360 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Control: 531643 4253144 [ 0 0 0 0 531643 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 71845 574760 [ 0 0 0 71845 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Broadcast_Control: 536206 4289648 [ 0 0 0 536206 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Request_Control: 612955 4903640 [ 0 0 612955 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Data: 212493 15299496 [ 0 0 0 0 0 212493 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Control: 943405 7547240 [ 0 0 578062 0 0 365343 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Unblock_Control: 613150 4905200 [ 0 0 0 0 0 613150 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -334,188 +334,188 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 76458 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76458 + system.l1_cntrl0.L1DcacheMemory_total_misses: 76421 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76421 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.9965% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.0035% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.2438% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.7562% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 76458 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 76421 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 76458 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 76458 + system.l1_cntrl0.L2cacheMemory_total_misses: 76421 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 76421 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 64.9965% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 35.0035% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 65.2438% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 34.7562% - system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 76458 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 76421 100% --- L1Cache --- - Event Counts - -Load [49581 49746 49565 50170 49738 49804 49853 49825 ] 398282 +Load [49924 49708 49939 49630 49901 49921 49906 49811 ] 398740 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26977 26862 26906 27016 26776 26709 26867 26746 ] 214859 -L2_Replacement [76406 76484 76318 77020 76385 76365 76568 76429 ] 611975 -L1_to_L2 [830481 839728 833985 838773 833522 835214 835808 839524 ] 6687035 -Trigger_L2_to_L1D [72 67 68 77 61 73 81 74 ] 573 +Store [26816 26890 27147 26856 26581 27032 26925 27089 ] 215336 +L2_Replacement [76603 76425 76947 76349 76332 76801 76659 76734 ] 612850 +L1_to_L2 [836567 835856 839100 833840 833623 837114 837261 834301 ] 6687662 +Trigger_L2_to_L1D [64 89 69 68 75 72 98 79 ] 614 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -Complete_L2_to_L1 [72 67 68 77 61 73 81 74 ] 573 -Other_GETX [187558 187679 187637 187547 187756 187844 187664 187793 ] 1501478 -Other_GETS [347741 347552 347763 347140 347578 347511 347479 347494 ] 2780258 -Merged_GETS [45 56 51 54 35 52 64 51 ] 408 +Complete_L2_to_L1 [64 89 69 68 75 72 98 79 ] 614 +Other_GETX [188192 188121 187843 188126 188416 187966 188072 187921 ] 1504657 +Other_GETS [347770 348016 347754 348080 347801 347775 347822 347909 ] 2782927 +Merged_GETS [48 51 52 58 67 47 56 60 ] 439 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 Invalidate [0 0 0 0 0 0 0 0 ] 0 -Ack [532196 532539 531481 536430 531897 531773 533288 532189 ] 4261793 -Shared_Ack [67 60 57 68 61 68 52 51 ] 484 -Data [2984 2981 2941 2905 2971 2905 3077 2981 ] 23745 -Shared_Data [1055 1081 1041 1041 1051 1083 1030 1103 ] 8485 -Exclusive_Data [72377 72432 72345 73089 72371 72385 72471 72358 ] 579828 -Writeback_Ack [72051 72112 72004 72704 72037 72068 72141 72049 ] 577166 +Ack [533401 532135 535914 531575 531594 534931 533858 534364 ] 4267772 +Shared_Ack [51 73 50 68 61 57 61 63 ] 484 +Data [2984 2975 2967 3052 2857 3025 2943 3007 ] 23810 +Shared_Data [1041 1088 1073 1118 1058 1035 1050 1044 ] 8507 +Exclusive_Data [72585 72376 72917 72190 72427 72752 72676 72692 ] 580615 +Writeback_Ack [72283 72039 72613 71845 72091 72482 72300 72404 ] 578057 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -All_acks [1109 1135 1090 1097 1106 1149 1076 1147 ] 8909 -All_acks_no_sharers [75308 75359 75239 75937 75287 75224 75502 75295 ] 603151 +All_acks [1087 1149 1115 1175 1112 1082 1103 1098 ] 8921 +All_acks_no_sharers [75523 75290 75842 75185 75231 75731 75566 75645 ] 604013 Flush_line [0 0 0 0 0 0 0 0 ] 0 Block_Ack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -I Load [49480 49679 49472 50084 49654 49723 49748 49737 ] 397577 +I Load [49854 49610 49852 49537 49810 49830 49791 49715 ] 397999 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [26936 26816 26856 26946 26741 26652 26830 26703 ] 214480 -I L2_Replacement [1453 1427 1415 1414 1414 1398 1444 1403 ] 11368 -I L1_to_L2 [261 273 272 283 269 270 273 278 ] 2179 -I Trigger_L2_to_L1D [1 1 1 5 2 0 2 2 ] 14 +I Store [26759 26826 27106 26822 26532 26982 26879 27030 ] 214936 +I L2_Replacement [1426 1428 1365 1470 1334 1391 1437 1401 ] 11252 +I L1_to_L2 [290 253 260 288 262 289 252 281 ] 2175 +I Trigger_L2_to_L1D [0 4 2 2 3 0 1 2 ] 14 I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -I Other_GETX [186606 186745 186735 186635 186843 186911 186691 186854 ] 1494020 -I Other_GETS [346094 345824 346024 345427 345870 345895 345835 345909 ] 2766878 +I Other_GETX [187247 187175 186978 187204 187508 187048 187132 186972 ] 1497264 +I Other_GETS [346139 346340 346035 346418 346178 346081 346161 346267 ] 2769619 I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 I NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 I Invalidate [0 0 0 0 0 0 0 0 ] 0 I Flush_line [0 0 0 0 0 0 0 0 ] 0 -S Load [0 1 1 1 0 0 1 1 ] 5 +S Load [0 0 1 1 1 1 2 0 ] 6 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 1 2 0 0 0 0 ] 3 -S L2_Replacement [2902 2945 2898 2902 2934 2899 2983 2977 ] 23440 -S L1_to_L2 [2927 2972 2928 2924 2964 2921 3012 3005 ] 23653 -S Trigger_L2_to_L1D [2 4 3 1 3 3 2 2 ] 20 +S Store [0 0 0 0 0 0 0 0 ] 0 +S L2_Replacement [2892 2957 2969 3034 2907 2928 2922 2927 ] 23536 +S L1_to_L2 [2915 2976 2991 3061 2935 2958 2958 2952 ] 23746 +S Trigger_L2_to_L1D [0 2 3 5 2 5 4 1 ] 22 S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -S Other_GETX [30 29 38 25 34 30 39 37 ] 262 -S Other_GETS [54 56 83 62 61 53 59 56 ] 484 +S Other_GETX [32 27 25 31 29 31 38 32 ] 245 +S Other_GETS [52 62 78 49 56 56 59 72 ] 484 S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 S NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 S Invalidate [0 0 0 0 0 0 0 0 ] 0 S Flush_line [0 0 0 0 0 0 0 0 ] 0 -O Load [0 0 0 0 0 0 0 1 ] 1 +O Load [0 0 0 0 0 0 0 0 ] 0 O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [0 0 0 0 0 0 0 0 ] 0 -O L2_Replacement [971 1036 1030 1010 978 973 982 937 ] 7917 -O L1_to_L2 [210 202 215 195 184 174 189 180 ] 1549 -O Trigger_L2_to_L1D [1 0 4 0 1 2 0 0 ] 8 +O Store [0 0 0 0 1 0 0 0 ] 1 +O L2_Replacement [969 992 1005 973 1032 1028 987 995 ] 7981 +O L1_to_L2 [189 216 217 196 203 188 202 198 ] 1609 +O Trigger_L2_to_L1D [0 1 0 2 0 2 0 1 ] 6 O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -O Other_GETX [10 4 3 8 7 1 5 7 ] 45 -O Other_GETS [6 12 14 10 9 10 12 8 ] 81 -O Merged_GETS [2 4 0 2 2 1 4 3 ] 18 +O Other_GETX [3 11 9 5 7 8 8 5 ] 56 +O Other_GETS [13 9 9 13 9 14 12 12 ] 91 +O Merged_GETS [3 1 1 1 4 3 2 6 ] 21 O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 O NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 O Invalidate [0 0 0 0 0 0 0 0 ] 0 O Flush_line [0 0 0 0 0 0 0 0 ] 0 -M Load [6 3 12 7 7 7 6 3 ] 51 +M Load [2 11 6 1 7 3 5 6 ] 41 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [4 3 2 4 1 3 2 3 ] 22 -M L2_Replacement [45001 45123 44967 45609 45188 45244 45184 45252 ] 361568 -M L1_to_L2 [46252 46425 46234 46881 46433 46549 46465 46457 ] 371696 -M Trigger_L2_to_L1D [34 32 39 42 40 50 41 38 ] 316 +M Store [2 9 1 2 5 5 2 5 ] 31 +M L2_Replacement [45430 45078 45347 44958 45304 45312 45295 45221 ] 361945 +M L1_to_L2 [46656 46363 46582 46203 46591 46595 46576 46486 ] 372052 +M Trigger_L2_to_L1D [39 55 37 39 49 40 59 51 ] 369 M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -M Other_GETX [560 537 525 518 509 561 566 519 ] 4295 -M Other_GETS [939 990 986 966 953 923 927 896 ] 7580 -M Merged_GETS [27 31 32 33 18 35 33 33 ] 242 +M Other_GETX [518 535 499 534 528 513 537 529 ] 4193 +M Other_GETS [927 954 964 921 978 994 941 946 ] 7625 +M Merged_GETS [27 27 29 42 39 27 33 31 ] 255 M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 M NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 M Invalidate [0 0 0 0 0 0 0 0 ] 0 M Flush_line [0 0 0 0 0 0 0 0 ] 0 -MM Load [10 1 5 5 4 5 1 3 ] 34 +MM Load [6 4 3 7 4 8 2 6 ] 40 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [0 3 2 1 2 4 1 1 ] 14 -MM L2_Replacement [26079 25953 26008 26085 25871 25851 25975 25860 ] 207682 -MM L1_to_L2 [26834 26685 26743 26820 26602 26530 26716 26590 ] 213520 -MM Trigger_L2_to_L1D [34 30 21 29 15 18 36 32 ] 215 +MM Store [4 4 1 2 0 5 1 2 ] 19 +MM L2_Replacement [25886 25970 26261 25914 25755 26142 26018 26190 ] 208136 +MM L1_to_L2 [26623 26713 26972 26675 26422 26849 26776 26903 ] 213933 +MM Trigger_L2_to_L1D [25 27 27 20 21 25 34 24 ] 203 MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -MM Other_GETX [304 297 296 303 301 282 315 312 ] 2410 -MM Other_GETS [550 562 554 565 565 524 521 531 ] 4372 -MM Merged_GETS [16 20 17 19 15 16 27 15 ] 145 +MM Other_GETX [332 308 279 307 294 297 298 320 ] 2435 +MM Other_GETS [542 551 556 595 479 543 557 517 ] 4340 +MM Merged_GETS [18 23 21 15 23 16 21 23 ] 160 MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MM Invalidate [0 0 0 0 0 0 0 0 ] 0 MM Flush_line [0 0 0 0 0 0 0 0 ] 0 -IR Load [0 1 1 4 2 0 1 2 ] 11 +IR Load [0 1 1 1 1 0 1 0 ] 5 IR Ifetch [0 0 0 0 0 0 0 0 ] 0 -IR Store [1 0 0 1 0 0 1 0 ] 3 -IR L1_to_L2 [4 0 0 4 0 0 3 1 ] 12 +IR Store [0 3 1 1 2 0 0 2 ] 9 +IR L1_to_L2 [0 11 0 0 0 0 0 0 ] 11 IR Flush_line [0 0 0 0 0 0 0 0 ] 0 -SR Load [1 2 2 1 3 2 0 1 ] 12 +SR Load [0 1 2 3 2 3 4 1 ] 16 SR Ifetch [0 0 0 0 0 0 0 0 ] 0 -SR Store [1 2 1 0 0 1 2 1 ] 8 -SR L1_to_L2 [4 4 0 1 9 0 12 17 ] 47 +SR Store [0 1 1 2 0 2 0 0 ] 6 +SR L1_to_L2 [0 0 0 12 0 3 0 0 ] 15 SR Flush_line [0 0 0 0 0 0 0 0 ] 0 -OR Load [0 0 2 0 1 2 0 0 ] 5 +OR Load [0 1 0 2 0 1 0 1 ] 5 OR Ifetch [0 0 0 0 0 0 0 0 ] 0 -OR Store [1 0 2 0 0 0 0 0 ] 3 -OR L1_to_L2 [3 0 3 0 0 0 0 0 ] 6 +OR Store [0 0 0 0 0 1 0 0 ] 1 +OR L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 OR Flush_line [0 0 0 0 0 0 0 0 ] 0 -MR Load [24 17 24 21 24 29 36 23 ] 198 +MR Load [19 37 27 31 32 27 41 33 ] 247 MR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MR Store [10 15 15 21 16 21 5 15 ] 118 -MR L1_to_L2 [62 40 78 110 59 85 67 53 ] 554 +MR Store [20 18 10 8 17 13 18 18 ] 122 +MR L1_to_L2 [80 89 59 56 91 56 102 86 ] 619 MR Flush_line [0 0 0 0 0 0 0 0 ] 0 -MMR Load [24 19 13 14 9 11 24 23 ] 137 +MMR Load [16 16 18 13 14 17 26 16 ] 136 MMR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMR Store [10 11 8 15 6 7 12 9 ] 78 -MMR L1_to_L2 [65 63 13 52 29 25 61 55 ] 363 +MMR Store [9 11 9 7 7 8 8 8 ] 67 +MMR L1_to_L2 [49 33 49 25 59 75 46 41 ] 377 MMR Flush_line [0 0 0 0 0 0 0 0 ] 0 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM L1_to_L2 [262856 266399 264252 266850 263777 263302 262648 267784 ] 2117868 -IM Other_GETX [9 15 13 10 4 7 9 6 ] 73 -IM Other_GETS [18 17 24 23 23 21 26 19 ] 171 +IM L1_to_L2 [266018 266623 267234 263614 262300 264612 266081 267986 ] 2124468 +IM Other_GETX [9 15 9 13 7 12 10 15 ] 90 +IM Other_GETS [14 14 22 16 21 19 20 24 ] 150 IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IM Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM Ack [185148 184284 184534 185252 183509 183194 184398 183334 ] 1473653 -IM Data [1105 1084 1042 1013 1054 1056 1081 1068 ] 8503 -IM Exclusive_Data [25831 25731 25813 25934 25683 25595 25749 25635 ] 205971 +IM Ack [183942 184444 186183 184251 182217 185388 184731 185996 ] 1477152 +IM Data [1100 1077 1044 1101 979 1096 1033 1092 ] 8522 +IM Exclusive_Data [25658 25751 26062 25721 25554 25884 25846 25938 ] 206414 IM Flush_line [0 0 0 0 0 0 0 0 ] 0 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM L1_to_L2 [0 2 8 5 0 0 43 10 ] 68 +SM L1_to_L2 [0 1 7 0 0 11 0 0 ] 19 SM Other_GETX [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 SM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 SM Invalidate [0 0 0 0 0 0 0 0 ] 0 -SM Ack [7 14 14 10 0 1 14 7 ] 67 -SM Data [1 2 2 2 0 1 2 1 ] 11 +SM Ack [0 7 7 14 0 14 0 0 ] 42 +SM Data [0 1 1 2 0 2 0 0 ] 6 SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 SM Flush_line [0 0 0 0 0 0 0 0 ] 0 @@ -523,99 +523,99 @@ OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 OM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OM L1_to_L2 [0 0 1 0 0 0 0 0 ] 1 +OM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 OM Other_GETX [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS [0 0 0 0 0 0 0 0 ] 0 OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OM Invalidate [0 0 0 0 0 0 0 0 ] 0 -OM Ack [7 0 14 0 0 0 0 0 ] 21 +OM Ack [0 0 0 0 7 7 0 0 ] 14 OM All_acks [0 0 0 0 0 0 0 0 ] 0 -OM All_acks_no_sharers [1 0 2 0 0 0 0 0 ] 3 +OM All_acks_no_sharers [0 0 0 0 1 1 0 0 ] 2 OM Flush_line [0 0 0 0 0 0 0 0 ] 0 ISM Load [0 0 0 0 0 0 0 0 ] 0 ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 ISM Store [0 0 0 0 0 0 0 0 ] 0 ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ISM L1_to_L2 [0 0 0 0 9 0 11 0 ] 20 -ISM Ack [142 75 85 118 105 63 101 92 ] 781 -ISM All_acks_no_sharers [1106 1086 1044 1015 1054 1057 1083 1069 ] 8514 +ISM L1_to_L2 [1 0 14 1 2 0 0 0 ] 18 +ISM Ack [100 106 115 87 104 73 108 112 ] 805 +ISM All_acks_no_sharers [1100 1078 1045 1103 979 1098 1033 1092 ] 8528 ISM Flush_line [0 0 0 0 0 0 0 0 ] 0 M_W Load [0 0 0 0 0 0 0 0 ] 0 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 M_W Store [0 0 0 0 0 0 0 0 ] 0 M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_W L1_to_L2 [480 569 456 535 595 415 562 468 ] 4080 -M_W Ack [1559 1775 1726 1563 1542 1584 1592 1645 ] 12986 -M_W All_acks_no_sharers [46546 46701 46532 47155 46688 46790 46722 46723 ] 373857 +M_W L1_to_L2 [478 492 525 412 539 542 404 528 ] 3920 +M_W Ack [1638 1621 1574 1544 1592 1693 1578 1594 ] 12834 +M_W All_acks_no_sharers [46927 46625 46855 46469 46873 46868 46830 46754 ] 374201 M_W Flush_line [0 0 0 0 0 0 0 0 ] 0 MM_W Load [0 0 0 0 0 0 0 0 ] 0 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 MM_W Store [0 0 0 0 0 0 0 0 ] 0 MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_to_L2 [744 911 918 569 890 918 922 734 ] 6606 -MM_W Ack [2419 2459 2528 2399 2664 2435 2455 2609 ] 19968 -MM_W All_acks_no_sharers [25831 25731 25813 25934 25683 25595 25749 25635 ] 205971 +MM_W L1_to_L2 [798 802 930 893 1079 874 817 808 ] 7001 +MM_W Ack [2421 2417 2567 2524 2555 2542 2445 2263 ] 19734 +MM_W All_acks_no_sharers [25658 25751 26062 25721 25554 25884 25846 25938 ] 206414 MM_W Flush_line [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS L1_to_L2 [488506 494237 490869 492304 490411 493050 493427 492592 ] 3935396 -IS Other_GETX [14 24 10 23 22 21 15 25 ] 154 -IS Other_GETS [38 40 29 32 35 33 42 27 ] 276 +IS L1_to_L2 [491513 490152 492188 490989 491749 492934 491610 486684 ] 3927819 +IS Other_GETX [20 22 15 15 18 25 17 23 ] 155 +IS Other_GETS [36 40 28 38 33 29 33 29 ] 266 IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IS NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IS Invalidate [0 0 0 0 0 0 0 0 ] 0 -IS Ack [339917 340869 339565 344213 341222 341342 341738 341391 ] 2730257 -IS Shared_Ack [61 55 54 65 59 67 51 48 ] 460 -IS Data [1878 1895 1897 1890 1917 1848 1994 1912 ] 15231 -IS Shared_Data [1055 1081 1041 1041 1051 1083 1030 1103 ] 8485 -IS Exclusive_Data [46546 46701 46532 47155 46688 46790 46722 46723 ] 373857 +IS Ack [342293 340559 342361 340012 342171 342186 342005 341426 ] 2733013 +IS Shared_Ack [48 67 45 64 57 53 57 59 ] 450 +IS Data [1884 1897 1922 1949 1878 1927 1910 1915 ] 15282 +IS Shared_Data [1041 1088 1073 1118 1058 1035 1050 1044 ] 8507 +IS Exclusive_Data [46927 46625 46855 46469 46873 46868 46830 46754 ] 374201 IS Flush_line [0 0 0 0 0 0 0 0 ] 0 SS Load [0 0 0 0 0 0 0 0 ] 0 SS Ifetch [0 0 0 0 0 0 0 0 ] 0 SS Store [0 0 0 0 0 0 0 0 ] 0 SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SS L1_to_L2 [1006 759 822 941 1103 760 1126 1027 ] 7544 -SS Ack [2997 3063 3015 2875 2855 3154 2990 3111 ] 24060 -SS Shared_Ack [6 5 3 3 2 1 1 3 ] 24 -SS All_acks [1109 1135 1090 1097 1106 1149 1076 1147 ] 8909 -SS All_acks_no_sharers [1824 1841 1848 1833 1862 1782 1948 1868 ] 14806 +SS L1_to_L2 [767 875 900 1161 1116 851 1181 1064 ] 7915 +SS Ack [3007 2981 3107 3143 2948 3028 2991 2973 ] 24178 +SS Shared_Ack [3 6 5 4 4 4 4 4 ] 34 +SS All_acks [1087 1149 1115 1175 1112 1082 1103 1098 ] 8921 +SS All_acks_no_sharers [1838 1836 1880 1892 1824 1880 1857 1861 ] 14868 SS Flush_line [0 0 0 0 0 0 0 0 ] 0 -OI Load [1 0 1 0 0 0 0 1 ] 3 +OI Load [0 0 0 0 0 1 2 0 ] 3 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 -OI Store [0 0 0 0 0 1 0 0 ] 1 +OI Store [0 0 0 0 0 0 0 0 ] 0 OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OI Other_GETX [0 0 0 1 1 1 0 0 ] 3 -OI Other_GETS [0 0 2 1 0 1 0 1 ] 5 -OI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Other_GETX [0 0 0 0 0 0 2 0 ] 2 +OI Other_GETS [0 0 0 1 1 0 0 1 ] 3 +OI Merged_GETS [0 0 1 0 0 0 0 0 ] 1 OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OI Invalidate [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack [1013 1088 1079 1063 1039 1023 1039 984 ] 8328 +OI Writeback_Ack [1016 1038 1067 1002 1079 1068 1024 1035 ] 8329 OI Flush_line [0 0 0 0 0 0 0 0 ] 0 -MI Load [6 4 17 12 17 12 10 6 ] 84 +MI Load [12 8 7 11 9 11 14 12 ] 84 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [4 1 5 5 2 4 6 5 ] 32 +MI Store [9 7 8 7 7 4 4 12 ] 58 MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MI Other_GETX [25 28 17 24 35 30 24 33 ] 216 -MI Other_GETS [42 51 47 54 62 51 57 47 ] 411 -MI Merged_GETS [0 1 2 0 0 0 0 0 ] 3 +MI Other_GETX [31 28 29 17 25 32 30 25 ] 217 +MI Other_GETS [47 46 62 29 46 39 39 41 ] 349 +MI Merged_GETS [0 0 0 0 1 1 0 0 ] 2 MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MI Invalidate [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [71013 70996 70908 71616 70962 71014 71078 71032 ] 568619 +MI Writeback_Ack [71236 70973 71517 70826 70987 71382 71244 71344 ] 569509 MI Flush_line [0 0 0 0 0 0 0 0 ] 0 II Load [0 0 0 0 0 0 0 0 ] 0 @@ -628,44 +628,44 @@ II Other_GETS [0 0 0 0 0 0 0 0 ] 0 II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 II NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 II Invalidate [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack [25 28 17 25 36 31 24 33 ] 219 +II Writeback_Ack [31 28 29 17 25 32 32 25 ] 219 II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 II Flush_line [0 0 0 0 0 0 0 0 ] 0 -IT Load [0 0 1 2 0 0 1 2 ] 6 +IT Load [0 0 0 1 0 0 1 0 ] 2 IT Ifetch [0 0 0 0 0 0 0 0 ] 0 -IT Store [1 0 0 0 0 0 0 0 ] 1 +IT Store [0 1 0 0 0 0 0 1 ] 2 IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IT L1_to_L2 [4 4 0 4 0 0 3 1 ] 16 -IT Complete_L2_to_L1 [1 1 1 5 2 0 2 2 ] 14 +IT L1_to_L2 [0 11 9 0 0 0 0 1 ] 21 +IT Complete_L2_to_L1 [0 4 2 2 3 0 1 2 ] 14 -ST Load [1 1 0 1 1 0 0 1 ] 5 +ST Load [0 1 0 2 0 1 0 0 ] 4 ST Ifetch [0 0 0 0 0 0 0 0 ] 0 -ST Store [1 0 0 0 0 0 1 1 ] 3 +ST Store [0 0 0 1 0 0 0 0 ] 1 ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ST L1_to_L2 [4 9 3 1 9 12 21 17 ] 76 -ST Complete_L2_to_L1 [2 4 3 1 3 3 2 2 ] 20 +ST L1_to_L2 [0 0 5 24 10 21 7 9 ] 76 +ST Complete_L2_to_L1 [0 2 3 5 2 5 4 1 ] 22 -OT Load [0 0 1 0 0 0 0 0 ] 1 +OT Load [0 0 0 2 0 0 0 0 ] 2 OT Ifetch [0 0 0 0 0 0 0 0 ] 0 -OT Store [1 0 1 0 0 0 0 0 ] 2 +OT Store [0 0 0 0 0 0 0 0 ] 0 OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OT L1_to_L2 [3 0 4 0 0 2 0 0 ] 9 -OT Complete_L2_to_L1 [1 0 4 0 1 2 0 0 ] 8 +OT L1_to_L2 [0 0 0 0 0 0 0 6 ] 6 +OT Complete_L2_to_L1 [0 1 0 2 0 2 0 1 ] 6 -MT Load [15 8 9 12 12 10 14 11 ] 91 +MT Load [9 14 13 15 13 7 10 13 ] 94 MT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MT Store [3 7 10 14 5 12 3 5 ] 59 +MT Store [8 7 5 2 6 9 9 9 ] 55 MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MT L1_to_L2 [142 84 115 158 118 139 129 113 ] 998 -MT Complete_L2_to_L1 [34 32 39 42 40 50 41 38 ] 316 +MT L1_to_L2 [100 155 80 156 179 117 164 171 ] 1122 +MT Complete_L2_to_L1 [39 55 37 39 49 40 59 51 ] 369 -MMT Load [13 10 4 6 4 3 11 10 ] 61 +MMT Load [6 4 9 3 8 11 7 8 ] 56 MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMT Store [4 4 3 7 3 4 4 3 ] 32 +MMT Store [5 3 5 2 4 3 4 2 ] 28 MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MMT L1_to_L2 [114 90 51 136 61 62 118 142 ] 774 -MMT Complete_L2_to_L1 [34 30 21 29 15 18 36 32 ] 215 +MMT L1_to_L2 [90 91 78 74 86 139 85 97 ] 740 +MMT Complete_L2_to_L1 [25 27 27 20 21 25 34 24 ] 203 MI_F Load [0 0 0 0 0 0 0 0 ] 0 MI_F Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -763,28 +763,28 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 76449 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76449 + system.l1_cntrl1.L1DcacheMemory_total_misses: 76887 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76887 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 65.0983% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 34.9017% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.8718% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.1282% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 76449 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 76887 100% Cache Stats: system.l1_cntrl1.L2cacheMemory - system.l1_cntrl1.L2cacheMemory_total_misses: 76449 - system.l1_cntrl1.L2cacheMemory_total_demand_misses: 76449 + system.l1_cntrl1.L2cacheMemory_total_misses: 76887 + system.l1_cntrl1.L2cacheMemory_total_demand_misses: 76887 system.l1_cntrl1.L2cacheMemory_total_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L2cacheMemory_request_type_LD: 65.0983% - system.l1_cntrl1.L2cacheMemory_request_type_ST: 34.9017% + system.l1_cntrl1.L2cacheMemory_request_type_LD: 64.8718% + system.l1_cntrl1.L2cacheMemory_request_type_ST: 35.1282% - system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor: 76449 100% + system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor: 76887 100% Cache Stats: system.l1_cntrl2.L1IcacheMemory system.l1_cntrl2.L1IcacheMemory_total_misses: 0 @@ -795,28 +795,28 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory Cache Stats: system.l1_cntrl2.L1DcacheMemory - system.l1_cntrl2.L1DcacheMemory_total_misses: 76663 - system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76663 + system.l1_cntrl2.L1DcacheMemory_total_misses: 76769 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76769 system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.9727% - system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.0273% + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.9533% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.0467% - system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76663 100% + system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76769 100% Cache Stats: system.l1_cntrl2.L2cacheMemory - system.l1_cntrl2.L2cacheMemory_total_misses: 76663 - system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76663 + system.l1_cntrl2.L2cacheMemory_total_misses: 76769 + system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76769 system.l1_cntrl2.L2cacheMemory_total_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L2cacheMemory_request_type_LD: 64.9727% - system.l1_cntrl2.L2cacheMemory_request_type_ST: 35.0273% + system.l1_cntrl2.L2cacheMemory_request_type_LD: 64.9533% + system.l1_cntrl2.L2cacheMemory_request_type_ST: 35.0467% - system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor: 76663 100% + system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor: 76769 100% Cache Stats: system.l1_cntrl3.L1IcacheMemory system.l1_cntrl3.L1IcacheMemory_total_misses: 0 @@ -827,28 +827,28 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory Cache Stats: system.l1_cntrl3.L1DcacheMemory - system.l1_cntrl3.L1DcacheMemory_total_misses: 76517 - system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76517 + system.l1_cntrl3.L1DcacheMemory_total_misses: 76826 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76826 system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.0679% - system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.9321% + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 64.7775% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 35.2225% - system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 76517 100% + system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 76826 100% Cache Stats: system.l1_cntrl3.L2cacheMemory - system.l1_cntrl3.L2cacheMemory_total_misses: 76517 - system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76517 + system.l1_cntrl3.L2cacheMemory_total_misses: 76826 + system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76826 system.l1_cntrl3.L2cacheMemory_total_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L2cacheMemory_request_type_LD: 65.0679% - system.l1_cntrl3.L2cacheMemory_request_type_ST: 34.9321% + system.l1_cntrl3.L2cacheMemory_request_type_LD: 64.7775% + system.l1_cntrl3.L2cacheMemory_request_type_ST: 35.2225% - system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor: 76517 100% + system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor: 76826 100% Cache Stats: system.l1_cntrl4.L1IcacheMemory system.l1_cntrl4.L1IcacheMemory_total_misses: 0 @@ -859,28 +859,28 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory Cache Stats: system.l1_cntrl4.L1DcacheMemory - system.l1_cntrl4.L1DcacheMemory_total_misses: 76491 - system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76491 + system.l1_cntrl4.L1DcacheMemory_total_misses: 76677 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76677 system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.7514% - system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.2486% + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 65.0638% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 34.9362% - system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76491 100% + system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76677 100% Cache Stats: system.l1_cntrl4.L2cacheMemory - system.l1_cntrl4.L2cacheMemory_total_misses: 76491 - system.l1_cntrl4.L2cacheMemory_total_demand_misses: 76491 + system.l1_cntrl4.L2cacheMemory_total_misses: 76677 + system.l1_cntrl4.L2cacheMemory_total_demand_misses: 76677 system.l1_cntrl4.L2cacheMemory_total_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L2cacheMemory_request_type_LD: 64.7514% - system.l1_cntrl4.L2cacheMemory_request_type_ST: 35.2486% + system.l1_cntrl4.L2cacheMemory_request_type_LD: 65.0638% + system.l1_cntrl4.L2cacheMemory_request_type_ST: 34.9362% - system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor: 76491 100% + system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor: 76677 100% Cache Stats: system.l1_cntrl5.L1IcacheMemory system.l1_cntrl5.L1IcacheMemory_total_misses: 0 @@ -891,28 +891,28 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory Cache Stats: system.l1_cntrl5.L1DcacheMemory - system.l1_cntrl5.L1DcacheMemory_total_misses: 76565 - system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76565 + system.l1_cntrl5.L1DcacheMemory_total_misses: 76530 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76530 system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.937% - system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.063% + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.8987% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.1013% - system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 76565 100% + system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 76530 100% Cache Stats: system.l1_cntrl5.L2cacheMemory - system.l1_cntrl5.L2cacheMemory_total_misses: 76565 - system.l1_cntrl5.L2cacheMemory_total_demand_misses: 76565 + system.l1_cntrl5.L2cacheMemory_total_misses: 76530 + system.l1_cntrl5.L2cacheMemory_total_demand_misses: 76530 system.l1_cntrl5.L2cacheMemory_total_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L2cacheMemory_request_type_LD: 64.937% - system.l1_cntrl5.L2cacheMemory_request_type_ST: 35.063% + system.l1_cntrl5.L2cacheMemory_request_type_LD: 64.8987% + system.l1_cntrl5.L2cacheMemory_request_type_ST: 35.1013% - system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor: 76565 100% + system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor: 76530 100% Cache Stats: system.l1_cntrl6.L1IcacheMemory system.l1_cntrl6.L1IcacheMemory_total_misses: 0 @@ -923,28 +923,28 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory Cache Stats: system.l1_cntrl6.L1DcacheMemory - system.l1_cntrl6.L1DcacheMemory_total_misses: 76401 - system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76401 + system.l1_cntrl6.L1DcacheMemory_total_misses: 77030 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 77030 system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.8094% - system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.1906% + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.7813% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.2187% - system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76401 100% + system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 77030 100% Cache Stats: system.l1_cntrl6.L2cacheMemory - system.l1_cntrl6.L2cacheMemory_total_misses: 76401 - system.l1_cntrl6.L2cacheMemory_total_demand_misses: 76401 + system.l1_cntrl6.L2cacheMemory_total_misses: 77030 + system.l1_cntrl6.L2cacheMemory_total_demand_misses: 77030 system.l1_cntrl6.L2cacheMemory_total_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L2cacheMemory_request_type_LD: 64.8094% - system.l1_cntrl6.L2cacheMemory_request_type_ST: 35.1906% + system.l1_cntrl6.L2cacheMemory_request_type_LD: 64.7813% + system.l1_cntrl6.L2cacheMemory_request_type_ST: 35.2187% - system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor: 76401 100% + system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor: 77030 100% Cache Stats: system.l1_cntrl7.L1IcacheMemory system.l1_cntrl7.L1IcacheMemory_total_misses: 0 @@ -955,28 +955,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory Cache Stats: system.l1_cntrl7.L1DcacheMemory - system.l1_cntrl7.L1DcacheMemory_total_misses: 77114 - system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77114 + system.l1_cntrl7.L1DcacheMemory_total_misses: 76431 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76431 system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L1DcacheMemory_request_type_LD: 65.0051% - system.l1_cntrl7.L1DcacheMemory_request_type_ST: 34.9949% + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.8794% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.1206% - system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 77114 100% + system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 76431 100% Cache Stats: system.l1_cntrl7.L2cacheMemory - system.l1_cntrl7.L2cacheMemory_total_misses: 77114 - system.l1_cntrl7.L2cacheMemory_total_demand_misses: 77114 + system.l1_cntrl7.L2cacheMemory_total_misses: 76431 + system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76431 system.l1_cntrl7.L2cacheMemory_total_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L2cacheMemory_request_type_LD: 65.0051% - system.l1_cntrl7.L2cacheMemory_request_type_ST: 34.9949% + system.l1_cntrl7.L2cacheMemory_request_type_LD: 64.8794% + system.l1_cntrl7.L2cacheMemory_request_type_ST: 35.1206% - system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor: 77114 100% + system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor: 76431 100% Cache Stats: system.dir_cntrl0.probeFilter system.dir_cntrl0.probeFilter_total_misses: 0 @@ -987,42 +987,42 @@ Cache Stats: system.dir_cntrl0.probeFilter Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 804345 - memory_reads: 592238 - memory_writes: 212082 - memory_refreshes: 39912 - memory_total_request_delays: 48631568 - memory_delays_per_request: 60.4611 - memory_delays_in_input_queue: 404227 - memory_delays_behind_head_of_bank_queue: 19355009 - memory_delays_stalled_at_head_of_bank_queue: 28872332 - memory_stalls_for_bank_busy: 4352151 + memory_total_requests: 805694 + memory_reads: 593184 + memory_writes: 212483 + memory_refreshes: 39958 + memory_total_request_delays: 48798556 + memory_delays_per_request: 60.5671 + memory_delays_in_input_queue: 405262 + memory_delays_behind_head_of_bank_queue: 19409751 + memory_delays_stalled_at_head_of_bank_queue: 28983543 + memory_stalls_for_bank_busy: 4365067 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 7096916 - memory_stalls_for_arbitration: 5949777 - memory_stalls_for_bus: 8066498 + memory_stalls_for_anti_starvation: 7130551 + memory_stalls_for_arbitration: 5967988 + memory_stalls_for_bus: 8097704 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2045376 - memory_stalls_for_read_read_turnaround: 1361614 - accesses_per_bank: 25291 24997 25118 25349 25409 25279 25436 25183 25382 25203 25226 25282 24957 25012 25140 25021 25042 25126 25142 25064 25144 25103 25220 25067 24976 24655 25089 24676 25014 25218 25321 25203 + memory_stalls_for_read_write_turnaround: 2054443 + memory_stalls_for_read_read_turnaround: 1367790 + accesses_per_bank: 25357 24861 25321 25431 25395 25323 25503 25257 25159 25315 25370 25222 25280 25113 25224 25165 25426 25242 24994 24993 25204 25332 24996 24908 24898 24906 24652 25426 25210 25129 25108 24974 --- Directory --- - Event Counts - -GETX [217953 ] 217953 -GETS [403510 ] 403510 -PUT [580089 ] 580089 +GETX [218472 ] 218472 +GETS [404033 ] 404033 +PUT [580822 ] 580822 Unblock [219 ] 219 -UnblockS [23715 ] 23715 -UnblockM [588343 ] 588343 -Writeback_Clean [7949 ] 7949 -Writeback_Dirty [379 ] 379 -Writeback_Exclusive_Clean [356904 ] 356904 -Writeback_Exclusive_Dirty [211710 ] 211710 +UnblockS [23789 ] 23789 +UnblockM [589142 ] 589142 +Writeback_Clean [7982 ] 7982 +Writeback_Dirty [347 ] 347 +Writeback_Exclusive_Clean [357361 ] 357361 +Writeback_Exclusive_Dirty [212146 ] 212146 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [592234 ] 592234 -Memory_Ack [212081 ] 212081 +Memory_Data [593182 ] 593182 +Memory_Ack [212480 ] 212480 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 @@ -1031,22 +1031,22 @@ Exclusive_Data [0 ] 0 All_acks_and_shared_data [0 ] 0 All_acks_and_owner_data [0 ] 0 All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [408 ] 408 +All_Unblocks [439 ] 439 GETF [0 ] 0 PUTF [0 ] 0 - Transitions - -NX GETX [55 ] 55 -NX GETS [91 ] 91 -NX PUT [8538 ] 8538 +NX GETX [61 ] 61 +NX GETS [97 ] 97 +NX PUT [8544 ] 8544 NX Pf_Replacement [0 ] 0 NX DMA_READ [0 ] 0 NX DMA_WRITE [0 ] 0 NX GETF [0 ] 0 -NO GETX [6917 ] 6917 -NO GETS [12358 ] 12358 -NO PUT [568629 ] 568629 +NO GETX [6844 ] 6844 +NO GETS [12311 ] 12311 +NO PUT [569516 ] 569516 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 @@ -1060,16 +1060,16 @@ S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 S GETF [0 ] 0 -O GETX [8251 ] 8251 -O GETS [15232 ] 15232 +O GETX [8254 ] 8254 +O GETS [15282 ] 15282 O PUT [0 ] 0 O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O GETF [0 ] 0 -E GETX [199274 ] 199274 -E GETS [369499 ] 369499 +E GETX [199792 ] 199792 +E GETS [369873 ] 369873 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 @@ -1108,11 +1108,11 @@ NO_R Exclusive_Data [0 ] 0 NO_R All_acks_and_data_no_sharers [0 ] 0 NO_R GETF [0 ] 0 -NO_B GETX [220 ] 220 -NO_B GETS [408 ] 408 -NO_B PUT [2898 ] 2898 -NO_B UnblockS [8053 ] 8053 -NO_B UnblockM [587738 ] 587738 +NO_B GETX [203 ] 203 +NO_B GETS [439 ] 439 +NO_B PUT [2749 ] 2749 +NO_B UnblockS [8042 ] 8042 +NO_B UnblockM [588526 ] 588526 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 @@ -1120,9 +1120,9 @@ NO_B GETF [0 ] 0 NO_B_X GETX [0 ] 0 NO_B_X GETS [0 ] 0 -NO_B_X PUT [2 ] 2 -NO_B_X UnblockS [5 ] 5 -NO_B_X UnblockM [215 ] 215 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [4 ] 4 +NO_B_X UnblockM [199 ] 199 NO_B_X Pf_Replacement [0 ] 0 NO_B_X DMA_READ [0 ] 0 NO_B_X DMA_WRITE [0 ] 0 @@ -1130,53 +1130,53 @@ NO_B_X GETF [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 -NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [18 ] 18 -NO_B_S UnblockM [390 ] 390 +NO_B_S PUT [2 ] 2 +NO_B_S UnblockS [22 ] 22 +NO_B_S UnblockM [417 ] 417 NO_B_S Pf_Replacement [0 ] 0 NO_B_S DMA_READ [0 ] 0 NO_B_S DMA_WRITE [0 ] 0 NO_B_S GETF [0 ] 0 -NO_B_S_W GETX [0 ] 0 -NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [14 ] 14 -NO_B_S_W UnblockS [408 ] 408 +NO_B_S_W GETX [1 ] 1 +NO_B_S_W GETS [1 ] 1 +NO_B_S_W PUT [7 ] 7 +NO_B_S_W UnblockS [439 ] 439 NO_B_S_W Pf_Replacement [0 ] 0 NO_B_S_W DMA_READ [0 ] 0 NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [408 ] 408 +NO_B_S_W All_Unblocks [439 ] 439 NO_B_S_W GETF [0 ] 0 -O_B GETX [5 ] 5 -O_B GETS [11 ] 11 +O_B GETX [9 ] 9 +O_B GETS [6 ] 6 O_B PUT [0 ] 0 -O_B UnblockS [15231 ] 15231 +O_B UnblockS [15282 ] 15282 O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 O_B GETF [0 ] 0 -NO_B_W GETX [1880 ] 1880 -NO_B_W GETS [3330 ] 3330 +NO_B_W GETX [1943 ] 1943 +NO_B_W GETS [3470 ] 3470 NO_B_W PUT [0 ] 0 NO_B_W UnblockS [0 ] 0 NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [577003 ] 577003 +NO_B_W Memory_Data [577900 ] 577900 NO_B_W GETF [0 ] 0 -O_B_W GETX [52 ] 52 -O_B_W GETS [105 ] 105 +O_B_W GETX [38 ] 38 +O_B_W GETS [102 ] 102 O_B_W PUT [0 ] 0 O_B_W UnblockS [0 ] 0 O_B_W Pf_Replacement [0 ] 0 O_B_W DMA_READ [0 ] 0 O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [15231 ] 15231 +O_B_W Memory_Data [15282 ] 15282 O_B_W GETF [0 ] 0 NO_W GETX [0 ] 0 @@ -1287,35 +1287,35 @@ O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 O_DR_B GETF [0 ] 0 -WB GETX [274 ] 274 -WB GETS [527 ] 527 -WB PUT [8 ] 8 +WB GETX [292 ] 292 +WB GETS [510 ] 510 +WB PUT [4 ] 4 WB Unblock [219 ] 219 -WB Writeback_Clean [7949 ] 7949 -WB Writeback_Dirty [379 ] 379 -WB Writeback_Exclusive_Clean [356904 ] 356904 -WB Writeback_Exclusive_Dirty [211710 ] 211710 +WB Writeback_Clean [7982 ] 7982 +WB Writeback_Dirty [347 ] 347 +WB Writeback_Exclusive_Clean [357361 ] 357361 +WB Writeback_Exclusive_Dirty [212146 ] 212146 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 WB GETF [0 ] 0 WB_O_W GETX [0 ] 0 -WB_O_W GETS [2 ] 2 +WB_O_W GETS [3 ] 3 WB_O_W PUT [0 ] 0 WB_O_W Pf_Replacement [0 ] 0 WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [379 ] 379 +WB_O_W Memory_Ack [347 ] 347 WB_O_W GETF [0 ] 0 -WB_E_W GETX [1025 ] 1025 -WB_E_W GETS [1947 ] 1947 +WB_E_W GETX [1035 ] 1035 +WB_E_W GETS [1939 ] 1939 WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [211702 ] 211702 +WB_E_W Memory_Ack [212133 ] 212133 WB_E_W GETF [0 ] 0 NO_F GETX [0 ] 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index 98c3bf402..6c9d43c8c 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -1,74 +1,82 @@ -system.cpu0: completed 10000 read, 5308 write accesses @570767 -system.cpu5: completed 10000 read, 5470 write accesses @573498 -system.cpu1: completed 10000 read, 5429 write accesses @573920 -system.cpu7: completed 10000 read, 5290 write accesses @575321 -system.cpu4: completed 10000 read, 5445 write accesses @585929 -system.cpu3: completed 10000 read, 5486 write accesses @586872 -system.cpu6: completed 10000 read, 5559 write accesses @588791 -system.cpu2: completed 10000 read, 5302 write accesses @590705 -system.cpu1: completed 20000 read, 10655 write accesses @1140898 -system.cpu7: completed 20000 read, 10580 write accesses @1148482 -system.cpu4: completed 20000 read, 10689 write accesses @1149967 -system.cpu0: completed 20000 read, 10632 write accesses @1151560 -system.cpu3: completed 20000 read, 10736 write accesses @1152482 -system.cpu5: completed 20000 read, 10944 write accesses @1160453 -system.cpu6: completed 20000 read, 10906 write accesses @1167829 -system.cpu2: completed 20000 read, 10785 write accesses @1181432 -system.cpu7: completed 30000 read, 15883 write accesses @1719841 -system.cpu1: completed 30000 read, 16166 write accesses @1721891 -system.cpu4: completed 30000 read, 16033 write accesses @1722326 -system.cpu3: completed 30000 read, 16219 write accesses @1736719 -system.cpu0: completed 30000 read, 16143 write accesses @1737446 -system.cpu5: completed 30000 read, 16313 write accesses @1738202 -system.cpu6: completed 30000 read, 16098 write accesses @1755658 -system.cpu2: completed 30000 read, 16394 write accesses @1762469 -system.cpu7: completed 40000 read, 21291 write accesses @2297271 -system.cpu1: completed 40000 read, 21590 write accesses @2298548 -system.cpu4: completed 40000 read, 21488 write accesses @2312342 -system.cpu6: completed 40000 read, 21332 write accesses @2321888 -system.cpu5: completed 40000 read, 21705 write accesses @2326997 -system.cpu3: completed 40000 read, 21707 write accesses @2330357 -system.cpu2: completed 40000 read, 21706 write accesses @2332615 -system.cpu0: completed 40000 read, 21524 write accesses @2334713 -system.cpu7: completed 50000 read, 26831 write accesses @2881244 -system.cpu1: completed 50000 read, 27020 write accesses @2890941 -system.cpu4: completed 50000 read, 27058 write accesses @2898430 -system.cpu3: completed 50000 read, 27008 write accesses @2902889 -system.cpu6: completed 50000 read, 26758 write accesses @2903882 -system.cpu5: completed 50000 read, 27004 write accesses @2909259 -system.cpu0: completed 50000 read, 27056 write accesses @2926100 -system.cpu2: completed 50000 read, 27098 write accesses @2926472 -system.cpu7: completed 60000 read, 32186 write accesses @3453644 -system.cpu4: completed 60000 read, 32482 write accesses @3465349 -system.cpu1: completed 60000 read, 32394 write accesses @3472313 -system.cpu5: completed 60000 read, 32325 write accesses @3483119 -system.cpu3: completed 60000 read, 32421 write accesses @3485537 -system.cpu6: completed 60000 read, 32185 write accesses @3493077 -system.cpu0: completed 60000 read, 32338 write accesses @3495286 -system.cpu2: completed 60000 read, 32370 write accesses @3496153 -system.cpu7: completed 70000 read, 37611 write accesses @4033523 -system.cpu4: completed 70000 read, 37774 write accesses @4042787 -system.cpu1: completed 70000 read, 37690 write accesses @4052999 -system.cpu3: completed 70000 read, 37732 write accesses @4060208 -system.cpu5: completed 70000 read, 37748 write accesses @4060547 -system.cpu2: completed 70000 read, 37645 write accesses @4064696 -system.cpu0: completed 70000 read, 37774 write accesses @4071656 -system.cpu6: completed 70000 read, 37516 write accesses @4081376 -system.cpu7: completed 80000 read, 43002 write accesses @4618082 -system.cpu4: completed 80000 read, 42974 write accesses @4622306 -system.cpu2: completed 80000 read, 43016 write accesses @4629591 -system.cpu3: completed 80000 read, 43060 write accesses @4631933 -system.cpu0: completed 80000 read, 42919 write accesses @4636700 -system.cpu5: completed 80000 read, 43162 write accesses @4639808 -system.cpu1: completed 80000 read, 42988 write accesses @4647998 -system.cpu6: completed 80000 read, 42866 write accesses @4656086 -system.cpu7: completed 90000 read, 48437 write accesses @5173289 -system.cpu4: completed 90000 read, 48464 write accesses @5207890 -system.cpu3: completed 90000 read, 48532 write accesses @5210569 -system.cpu2: completed 90000 read, 48392 write accesses @5213621 -system.cpu5: completed 90000 read, 48493 write accesses @5223220 -system.cpu0: completed 90000 read, 48496 write accesses @5233894 -system.cpu6: completed 90000 read, 48247 write accesses @5234744 -system.cpu1: completed 90000 read, 48380 write accesses @5239171 -system.cpu7: completed 100000 read, 53766 write accesses @5747338 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +system.cpu5: completed 10000 read, 5478 write accesses @567161 +system.cpu3: completed 10000 read, 5277 write accesses @567758 +system.cpu1: completed 10000 read, 5424 write accesses @571139 +system.cpu2: completed 10000 read, 5363 write accesses @576050 +system.cpu6: completed 10000 read, 5463 write accesses @585533 +system.cpu4: completed 10000 read, 5420 write accesses @589179 +system.cpu7: completed 10000 read, 5472 write accesses @590379 +system.cpu0: completed 10000 read, 5369 write accesses @590533 +system.cpu5: completed 20000 read, 10791 write accesses @1146089 +system.cpu3: completed 20000 read, 10874 write accesses @1153309 +system.cpu1: completed 20000 read, 10881 write accesses @1155896 +system.cpu2: completed 20000 read, 10800 write accesses @1162820 +system.cpu0: completed 20000 read, 10720 write accesses @1163331 +system.cpu4: completed 20000 read, 10833 write accesses @1163813 +system.cpu6: completed 20000 read, 10762 write accesses @1164662 +system.cpu7: completed 20000 read, 10940 write accesses @1175272 +system.cpu3: completed 30000 read, 16099 write accesses @1730233 +system.cpu5: completed 30000 read, 16356 write accesses @1731718 +system.cpu6: completed 30000 read, 16169 write accesses @1737322 +system.cpu0: completed 30000 read, 16008 write accesses @1738364 +system.cpu1: completed 30000 read, 16522 write accesses @1739971 +system.cpu2: completed 30000 read, 16224 write accesses @1741457 +system.cpu4: completed 30000 read, 16211 write accesses @1745036 +system.cpu7: completed 30000 read, 16445 write accesses @1750339 +system.cpu5: completed 40000 read, 21741 write accesses @2306008 +system.cpu6: completed 40000 read, 21530 write accesses @2310178 +system.cpu2: completed 40000 read, 21620 write accesses @2310592 +system.cpu4: completed 40000 read, 21531 write accesses @2315393 +system.cpu0: completed 40000 read, 21438 write accesses @2316997 +system.cpu3: completed 40000 read, 21653 write accesses @2317686 +system.cpu1: completed 40000 read, 21749 write accesses @2319017 +system.cpu7: completed 40000 read, 21844 write accesses @2338046 +system.cpu3: completed 50000 read, 27002 write accesses @2880938 +system.cpu2: completed 50000 read, 27054 write accesses @2886893 +system.cpu6: completed 50000 read, 26777 write accesses @2887224 +system.cpu5: completed 50000 read, 27071 write accesses @2894287 +system.cpu4: completed 50000 read, 26806 write accesses @2897144 +system.cpu0: completed 50000 read, 26853 write accesses @2903681 +system.cpu7: completed 50000 read, 27200 write accesses @2905958 +system.cpu1: completed 50000 read, 27246 write accesses @2906447 +system.cpu2: completed 60000 read, 32371 write accesses @3448040 +system.cpu6: completed 60000 read, 32232 write accesses @3458102 +system.cpu3: completed 60000 read, 32278 write accesses @3464050 +system.cpu0: completed 60000 read, 32186 write accesses @3466844 +system.cpu4: completed 60000 read, 31956 write accesses @3470756 +system.cpu5: completed 60000 read, 32561 write accesses @3476407 +system.cpu1: completed 60000 read, 32600 write accesses @3479914 +system.cpu7: completed 60000 read, 32524 write accesses @3491585 +system.cpu2: completed 70000 read, 37778 write accesses @4027715 +system.cpu3: completed 70000 read, 37641 write accesses @4032589 +system.cpu6: completed 70000 read, 37624 write accesses @4034915 +system.cpu4: completed 70000 read, 37315 write accesses @4048771 +system.cpu0: completed 70000 read, 37650 write accesses @4058138 +system.cpu1: completed 70000 read, 38210 write accesses @4062463 +system.cpu5: completed 70000 read, 37970 write accesses @4063291 +system.cpu7: completed 70000 read, 37837 write accesses @4069993 +system.cpu2: completed 80000 read, 43081 write accesses @4605440 +system.cpu6: completed 80000 read, 43005 write accesses @4612592 +system.cpu3: completed 80000 read, 43103 write accesses @4614137 +system.cpu5: completed 80000 read, 43266 write accesses @4625729 +system.cpu0: completed 80000 read, 42925 write accesses @4631387 +system.cpu4: completed 80000 read, 42800 write accesses @4633690 +system.cpu1: completed 80000 read, 43498 write accesses @4640305 +system.cpu7: completed 80000 read, 43249 write accesses @4647178 +system.cpu2: completed 90000 read, 48427 write accesses @5170760 +system.cpu3: completed 90000 read, 48430 write accesses @5181607 +system.cpu6: completed 90000 read, 48549 write accesses @5189137 +system.cpu5: completed 90000 read, 48576 write accesses @5206014 +system.cpu4: completed 90000 read, 48077 write accesses @5207168 +system.cpu1: completed 90000 read, 48840 write accesses @5207183 +system.cpu0: completed 90000 read, 48241 write accesses @5207339 +system.cpu7: completed 90000 read, 48589 write accesses @5224757 +system.cpu2: completed 100000 read, 53907 write accesses @5753960 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 61721f45b..df2112f9f 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.005747 # Number of seconds simulated -sim_ticks 5747338 # Number of ticks simulated -final_tick 5747338 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.005754 # Number of seconds simulated +sim_ticks 5753960 # Number of ticks simulated +final_tick 5753960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 47566 # Simulator tick rate (ticks/s) -host_mem_usage 409708 # Number of bytes of host memory used -host_seconds 120.83 # Real time elapsed on the host +host_tick_rate 28381 # Simulator tick rate (ticks/s) +host_mem_usage 417808 # Number of bytes of host memory used +host_seconds 202.74 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -157,29 +157,29 @@ system.dir_cntrl0.probeFilter.num_tag_array_reads 0 system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 98701 # number of read accesses completed -system.cpu0.num_writes 53180 # number of write accesses completed +system.cpu0.num_reads 99424 # number of read accesses completed +system.cpu0.num_writes 53376 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98822 # number of read accesses completed -system.cpu1.num_writes 52970 # number of write accesses completed +system.cpu1.num_reads 99626 # number of read accesses completed +system.cpu1.num_writes 54012 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99173 # number of read accesses completed -system.cpu2.num_writes 53394 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 53908 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99438 # number of read accesses completed -system.cpu3.num_writes 53653 # number of write accesses completed +system.cpu3.num_reads 99716 # number of read accesses completed +system.cpu3.num_writes 53812 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99047 # number of read accesses completed -system.cpu4.num_writes 53311 # number of write accesses completed +system.cpu4.num_reads 99512 # number of read accesses completed +system.cpu4.num_writes 53333 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99288 # number of read accesses completed -system.cpu5.num_writes 53451 # number of write accesses completed +system.cpu5.num_reads 99476 # number of read accesses completed +system.cpu5.num_writes 53666 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98768 # number of read accesses completed -system.cpu6.num_writes 53052 # number of write accesses completed +system.cpu6.num_reads 99747 # number of read accesses completed +system.cpu6.num_writes 53910 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 53766 # number of write accesses completed +system.cpu7.num_reads 99133 # number of read accesses completed +system.cpu7.num_writes 53472 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index fbb000400..b3b737726 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -1,26 +1,26 @@ -Real time: Sep/01/2012 13:48:23 +Real time: Oct/08/2012 22:20:34 Profiler Stats -------------- -Elapsed_time_in_seconds: 43 -Elapsed_time_in_minutes: 0.716667 -Elapsed_time_in_hours: 0.0119444 -Elapsed_time_in_days: 0.000497685 +Elapsed_time_in_seconds: 79 +Elapsed_time_in_minutes: 1.31667 +Elapsed_time_in_hours: 0.0219444 +Elapsed_time_in_days: 0.000914352 -Virtual_time_in_seconds: 43.31 -Virtual_time_in_minutes: 0.721833 -Virtual_time_in_hours: 0.0120306 -Virtual_time_in_days: 0.000501273 +Virtual_time_in_seconds: 48.17 +Virtual_time_in_minutes: 0.802833 +Virtual_time_in_hours: 0.0133806 +Virtual_time_in_days: 0.000557523 -Ruby_current_time: 8642753 +Ruby_current_time: 8594451 Ruby_start_time: 0 -Ruby_cycles: 8642753 +Ruby_cycles: 8594451 -mbytes_resident: 60.6562 -mbytes_total: 399.672 -resident_ratio: 0.151804 +mbytes_resident: 69.9141 +mbytes_total: 408.566 +resident_ratio: 0.17113 -ruby_cycles_executed: [ 8642754 8642754 8642754 8642754 8642754 8642754 8642754 8642754 ] +ruby_cycles_executed: [ 8594452 8594452 8594452 8594452 8594452 8594452 8594452 8594452 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -30,29 +30,29 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 616251 average: 15.9984 | standard deviation: 0.126869 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 616131 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 612679 average: 15.9984 | standard deviation: 0.127251 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 10 612557 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 4776 count: 616123 average: 1795.35 | standard deviation: 414.477 | 0 1 4 5 4 6 2 4 5 3 2 2 1 4 3 0 4 16 19 24 35 84 107 158 246 394 516 799 1053 1257 1834 2502 2826 3510 4476 5278 6753 7207 7603 9693 11698 11058 12663 14078 14754 17257 16918 15782 18905 20633 18435 19307 19900 19344 21176 19234 17152 19082 20051 16188 16264 15715 14908 15416 13291 11277 12219 11916 9452 9307 8556 7808 7864 6457 5309 5581 5515 4250 3842 3580 3265 3103 2466 1908 2073 1994 1517 1313 1242 1090 1028 790 677 670 662 435 413 368 358 318 235 216 208 174 141 115 105 85 103 63 53 50 50 35 26 25 21 27 14 16 14 4 12 10 6 9 5 5 1 3 2 1 3 1 2 2 2 0 0 0 0 4 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 32 max: 4737 count: 400262 average: 1795.26 | standard deviation: 414.645 | 0 1 4 2 4 4 1 2 3 2 2 0 0 3 2 0 3 10 13 11 23 53 66 110 159 266 334 537 699 799 1186 1637 1820 2298 2878 3407 4350 4680 4906 6373 7625 7226 8201 9120 9644 11229 10853 10342 12294 13400 12030 12512 12946 12569 13875 12476 11156 12382 13030 10587 10544 10172 9663 9945 8585 7315 7818 7765 6162 6022 5538 5088 5151 4134 3417 3701 3583 2767 2452 2314 2095 1997 1601 1255 1387 1294 988 884 833 737 684 490 452 419 436 288 285 220 225 214 149 143 140 122 94 73 73 51 66 34 32 32 31 24 15 10 10 18 7 11 9 3 5 7 6 7 4 2 0 3 0 1 3 1 2 1 2 0 0 0 0 4 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 32 max: 4776 count: 215861 average: 1795.51 | standard deviation: 414.166 | 0 0 0 3 0 2 1 2 2 1 0 2 1 1 1 0 1 6 6 13 12 31 41 48 87 128 182 262 354 458 648 865 1006 1212 1598 1871 2403 2527 2697 3320 4073 3832 4462 4958 5110 6028 6065 5440 6611 7233 6405 6795 6954 6775 7301 6758 5996 6700 7021 5601 5720 5543 5245 5471 4706 3962 4401 4151 3290 3285 3018 2720 2713 2323 1892 1880 1932 1483 1390 1266 1170 1106 865 653 686 700 529 429 409 353 344 300 225 251 226 147 128 148 133 104 86 73 68 52 47 42 32 34 37 29 21 18 19 11 11 15 11 9 7 5 5 1 7 3 0 2 1 3 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Directory: [binsize: 32 max: 4776 count: 607868 average: 1796.88 | standard deviation: 414.375 | 0 1 4 5 4 6 2 4 5 3 2 2 1 4 3 0 4 16 19 23 33 79 102 150 235 382 500 770 1020 1209 1785 2449 2745 3429 4369 5167 6620 7042 7423 9530 11521 10828 12435 13885 14505 16983 16670 15485 18664 20359 18181 19011 19634 19059 20930 19001 16911 18870 19850 15969 16076 15575 14760 15247 13149 11146 12125 11810 9354 9206 8478 7728 7786 6400 5234 5534 5471 4213 3806 3559 3230 3075 2450 1891 2058 1978 1499 1308 1237 1081 1020 780 667 662 659 434 408 362 357 314 235 214 208 174 140 113 104 84 103 63 53 50 50 35 26 25 21 26 14 16 14 4 12 10 6 9 5 5 1 3 2 1 3 1 2 2 2 0 0 0 0 4 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache_wCC: [binsize: 32 max: 3752 count: 8255 average: 1682.74 | standard deviation: 406.431 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 5 5 8 11 12 16 29 33 48 49 53 81 81 107 111 133 165 180 163 177 230 228 193 249 274 248 297 241 274 254 296 266 285 246 233 241 212 201 219 188 140 148 169 142 131 94 106 98 101 78 80 78 57 75 47 44 37 36 21 35 28 16 17 15 16 18 5 5 9 8 10 10 8 3 1 5 6 1 4 0 2 0 0 1 2 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 32 max: 4653 count: 612551 average: 1795.7 | standard deviation: 410.66 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 6 14 17 28 51 113 126 222 341 478 739 943 1172 1767 2399 2690 3474 4236 4975 6483 7278 7353 9544 11638 11194 12606 14095 14781 17182 16959 16021 18801 20784 18178 19118 19510 19480 21166 19191 16928 19138 19616 16277 16268 15657 15140 15502 13442 11313 12308 12228 9547 9169 8703 7770 7869 6263 5198 5485 5264 4033 3801 3587 3147 3163 2478 2078 2041 1979 1479 1363 1116 1041 1026 720 599 673 609 407 374 362 280 234 210 164 195 189 108 117 93 78 70 54 43 54 50 33 34 21 18 15 18 13 13 5 6 5 4 10 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 4653 count: 398259 average: 1796.14 | standard deviation: 410.545 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 4 9 13 19 34 69 77 142 213 312 496 634 789 1112 1557 1708 2226 2742 3251 4192 4713 4761 6194 7550 7329 8214 9166 9655 11143 11019 10418 12237 13560 11738 12340 12645 12602 13722 12490 11061 12504 12769 10620 10543 10215 9778 10113 8796 7377 7953 7936 6168 5941 5772 5011 5117 4169 3341 3601 3439 2674 2487 2285 2012 2017 1631 1369 1349 1275 989 894 721 679 658 468 412 453 398 269 258 217 175 160 142 102 128 123 67 76 57 44 47 33 26 32 31 19 17 11 12 10 11 10 10 3 2 4 3 7 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 32 max: 4626 count: 214292 average: 1794.89 | standard deviation: 410.873 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 9 17 44 49 80 128 166 243 309 383 655 842 982 1248 1494 1724 2291 2565 2592 3350 4088 3865 4392 4929 5126 6039 5940 5603 6564 7224 6440 6778 6865 6878 7444 6701 5867 6634 6847 5657 5725 5442 5362 5389 4646 3936 4355 4292 3379 3228 2931 2759 2752 2094 1857 1884 1825 1359 1314 1302 1135 1146 847 709 692 704 490 469 395 362 368 252 187 220 211 138 116 145 105 74 68 62 67 66 41 41 36 34 23 21 17 22 19 14 17 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 32 max: 4653 count: 604395 average: 1797.09 | standard deviation: 410.541 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 5 14 16 27 51 107 121 212 329 459 718 907 1137 1731 2346 2618 3386 4136 4857 6358 7136 7189 9366 11477 10968 12372 13884 14549 16941 16662 15768 18551 20542 17864 18850 19270 19247 20917 18940 16714 18905 19436 16065 16081 15483 14980 15328 13265 11178 12186 12123 9437 9093 8626 7689 7797 6193 5141 5442 5224 3985 3768 3556 3119 3142 2458 2058 2027 1963 1464 1353 1109 1034 1018 712 590 667 604 406 370 361 279 234 209 164 191 188 105 115 92 77 68 54 43 53 50 33 33 21 17 15 18 13 13 5 6 5 4 9 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 32 max: 4002 count: 8156 average: 1692.69 | standard deviation: 406.323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 6 5 10 12 19 21 36 35 36 53 72 88 100 118 125 142 164 178 161 226 234 211 232 241 297 253 250 242 314 268 240 233 249 251 214 233 180 212 187 174 160 174 177 135 122 105 110 76 77 81 72 70 57 43 40 48 33 31 28 21 20 20 14 16 15 10 7 7 8 8 9 6 5 1 4 1 1 0 1 0 4 1 3 2 1 1 2 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_wCC_Times: 8255 +imcomplete_wCC_Times: 8156 miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 175 count: 7 average: 113.714 | standard deviation: 50.5833 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] -imcomplete_dir_Times: 607861 -miss_latency_LD_Directory: [binsize: 32 max: 4737 count: 394885 average: 1796.82 | standard deviation: 414.485 | 0 1 4 2 4 4 1 2 3 2 2 0 0 3 2 0 3 10 13 11 21 49 64 105 152 257 322 518 679 769 1153 1596 1772 2247 2811 3334 4264 4563 4792 6261 7499 7072 8051 8990 9488 11054 10677 10152 12134 13228 11861 12318 12772 12386 13725 12331 11008 12241 12895 10439 10424 10080 9578 9838 8498 7238 7755 7697 6105 5957 5481 5033 5099 4100 3368 3668 3554 2742 2429 2302 2071 1979 1590 1241 1375 1283 979 882 829 732 677 483 443 413 433 287 283 216 225 211 149 141 140 122 93 72 72 50 66 34 32 32 31 24 15 10 10 17 7 11 9 3 5 7 6 7 4 2 0 3 0 1 3 1 2 1 2 0 0 0 0 4 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 3752 count: 5377 average: 1681.26 | standard deviation: 410.533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 2 5 7 9 12 19 20 30 33 41 48 51 67 73 86 117 114 112 126 154 150 130 156 175 176 190 160 172 169 194 174 183 150 145 148 141 135 148 120 92 85 107 87 77 63 68 57 65 57 55 52 34 49 33 29 25 23 12 24 18 11 14 12 11 9 2 4 5 7 7 9 6 3 1 2 4 0 3 0 2 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_Directory: [binsize: 32 max: 4776 count: 212983 average: 1797 | standard deviation: 414.172 | 0 0 0 3 0 2 1 2 2 1 0 2 1 1 1 0 1 6 6 12 12 30 38 45 83 125 178 252 341 440 632 853 973 1182 1558 1833 2356 2479 2631 3269 4022 3756 4384 4895 5017 5929 5993 5333 6530 7131 6320 6693 6862 6673 7205 6670 5903 6629 6955 5530 5652 5495 5182 5409 4651 3908 4370 4113 3249 3249 2997 2695 2687 2300 1866 1866 1917 1471 1377 1257 1159 1096 860 650 683 695 520 426 408 349 343 297 224 249 226 147 125 146 132 103 86 73 68 52 47 41 32 34 37 29 21 18 19 11 11 15 11 9 7 5 5 1 7 3 0 2 1 3 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 3360 count: 2878 average: 1685.51 | standard deviation: 398.712 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 3 3 4 3 4 10 13 18 16 12 33 30 40 38 47 48 66 51 51 76 78 63 93 99 72 107 81 102 85 102 92 102 96 88 93 71 66 71 68 48 63 62 55 54 31 38 41 36 21 25 26 23 26 14 15 12 13 9 11 10 5 3 3 5 9 3 1 4 1 3 1 2 0 0 3 2 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_dir_Times: 604388 +miss_latency_LD_Directory: [binsize: 32 max: 4653 count: 392936 average: 1797.52 | standard deviation: 410.479 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 3 9 12 19 34 66 75 136 203 303 482 609 767 1090 1519 1664 2178 2685 3176 4112 4612 4654 6074 7444 7169 8063 9044 9500 10991 10831 10240 12073 13400 11535 12164 12489 12466 13560 12328 10926 12344 12645 10474 10409 10101 9677 9992 8674 7283 7879 7873 6097 5889 5722 4966 5062 4125 3303 3568 3414 2646 2464 2266 1993 2001 1620 1355 1343 1263 982 889 716 673 654 464 405 451 396 269 255 217 174 160 142 102 125 123 65 76 56 43 45 33 26 31 31 19 17 11 11 10 11 10 10 3 2 4 3 6 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 4002 count: 5323 average: 1694.26 | standard deviation: 402.526 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 3 2 6 10 9 14 25 22 22 38 44 48 57 75 80 101 107 120 106 160 151 122 155 152 188 178 164 160 203 176 156 136 162 162 135 160 124 146 134 114 101 121 122 94 74 63 71 52 50 45 55 44 38 33 25 28 23 19 19 16 11 14 6 12 7 5 5 6 4 4 7 2 2 0 3 0 1 0 0 0 3 0 2 0 1 1 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 32 max: 4626 count: 211459 average: 1796.3 | standard deviation: 410.657 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 8 17 41 46 76 126 156 236 298 370 641 827 954 1208 1451 1681 2246 2524 2535 3292 4033 3799 4309 4840 5049 5950 5831 5528 6478 7142 6329 6686 6781 6781 7357 6612 5788 6561 6791 5591 5672 5382 5303 5336 4591 3895 4307 4250 3340 3204 2904 2723 2735 2068 1838 1874 1810 1339 1304 1290 1126 1141 838 703 684 700 482 464 393 361 364 248 185 216 208 137 115 144 105 74 67 62 66 65 40 39 36 34 23 21 17 22 19 14 16 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 3670 count: 2833 average: 1689.73 | standard deviation: 413.417 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 3 4 2 10 7 11 13 14 15 28 40 43 43 45 41 57 58 55 66 83 89 77 89 109 75 86 82 111 92 84 97 87 89 79 73 56 66 53 60 59 53 55 41 48 42 39 24 27 36 17 26 19 10 15 20 10 12 9 5 9 6 8 4 8 5 2 1 4 4 2 4 3 1 1 1 0 0 1 0 1 1 1 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -66,11 +66,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619 | standard deviation: 0.155601 | 1231314 951 818 846 872 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619 | standard deviation: 0.155601 | 1231314 951 818 846 872 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ] +Total_delay_cycles: [binsize: 1 max: 22 count: 1227672 average: 0.0072389 | standard deviation: 0.160195 | 1224232 923 774 826 891 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1227672 average: 0.0072389 | standard deviation: 0.160195 | 1224232 923 774 826 891 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 616123 average: 0.000835872 | standard deviation: 0.0469998 | 615902 40 84 81 16 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 21 count: 618697 average: 0.01353 | standard deviation: 0.214574 | 615412 911 734 765 856 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 612551 average: 0.00100726 | standard deviation: 0.0517903 | 612293 37 99 106 16 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 22 count: 615121 average: 0.0134445 | standard deviation: 0.22016 | 611939 886 675 720 875 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -82,337 +82,337 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619 Resource Usage -------------- page_size: 4096 -user_time: 43 +user_time: 48 system_time: 0 -page_reclaims: 11522 -page_faults: 0 +page_reclaims: 10401 +page_faults: 3 swaps: 0 -block_inputs: 0 -block_outputs: 184 +block_inputs: 480 +block_outputs: 232 Network Stats ------------- -total_msg_count_Control: 1848417 14787336 -total_msg_count_Data: 1831398 131860656 -total_msg_count_Response_Data: 1848370 133082640 -total_msg_count_Writeback_Control: 1856091 14848728 -total_msgs: 7384276 total_bytes: 294579360 +total_msg_count_Control: 1837698 14701584 +total_msg_count_Data: 1820943 131107896 +total_msg_count_Response_Data: 1837653 132311016 +total_msg_count_Writeback_Control: 1845363 14762904 +total_msgs: 7341657 total_bytes: 292883400 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 4.48511 - links_utilized_percent_switch_0_link_0: 4.47733 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 4.49289 bw: 16000 base_latency: 1 +links_utilized_percent_switch_0: 4.4737 + links_utilized_percent_switch_0_link_0: 4.46588 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 4.48153 bw: 16000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 77689 621512 [ 0 0 0 77689 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 77364 618912 [ 0 0 77364 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 76700 5522400 [ 0 0 76700 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 995 71640 [ 0 0 0 0 995 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 77065 616520 [ 0 0 0 77065 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 76731 613848 [ 0 0 76731 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 76026 5473872 [ 0 0 76026 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 1040 74880 [ 0 0 0 0 1040 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 4.47412 - links_utilized_percent_switch_1_link_0: 4.46635 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 4.48189 bw: 16000 base_latency: 1 +links_utilized_percent_switch_1: 4.46364 + links_utilized_percent_switch_1_link_0: 4.45628 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 4.471 bw: 16000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 77170 5556240 [ 0 0 0 0 77170 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 77501 620008 [ 0 0 0 77501 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 77173 617384 [ 0 0 77173 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Data: 76458 5504976 [ 0 0 76458 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1047 75384 [ 0 0 0 0 1047 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 76567 5512824 [ 0 0 0 0 76567 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 76882 615056 [ 0 0 0 76882 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 76569 612552 [ 0 0 76569 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 75853 5461416 [ 0 0 75853 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1030 74160 [ 0 0 0 0 1030 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 4.45232 - links_utilized_percent_switch_2_link_0: 4.44489 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 4.45975 bw: 16000 base_latency: 1 +links_utilized_percent_switch_2: 4.44318 + links_utilized_percent_switch_2_link_0: 4.43569 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 4.45067 bw: 16000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 77121 616968 [ 0 0 0 77121 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 76801 614408 [ 0 0 76801 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 76122 5480784 [ 0 0 76122 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 999 71928 [ 0 0 0 0 999 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 76213 5487336 [ 0 0 0 0 76213 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 76529 612232 [ 0 0 0 76529 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 76216 609728 [ 0 0 76216 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 75497 5435784 [ 0 0 75497 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1037 74664 [ 0 0 0 0 1037 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 4.4511 - links_utilized_percent_switch_3_link_0: 4.44343 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 4.45876 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 4.44459 + links_utilized_percent_switch_3_link_0: 4.43679 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 4.45238 bw: 16000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 76774 5527728 [ 0 0 0 0 76774 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 77103 616824 [ 0 0 0 77103 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 76775 614200 [ 0 0 76775 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 76039 5474808 [ 0 0 76039 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 1066 76752 [ 0 0 0 0 1066 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 76230 5488560 [ 0 0 0 0 76230 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 76565 612520 [ 0 0 0 76565 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 76231 609848 [ 0 0 76231 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 75505 5436360 [ 0 0 75505 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 1060 76320 [ 0 0 0 0 1060 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 4.47992 - links_utilized_percent_switch_4_link_0: 4.47268 bw: 16000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 4.48716 bw: 16000 base_latency: 1 +links_utilized_percent_switch_4: 4.47109 + links_utilized_percent_switch_4_link_0: 4.46353 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 4.47864 bw: 16000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 77282 5564304 [ 0 0 0 0 77282 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 77591 620728 [ 0 0 0 77591 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 77282 618256 [ 0 0 77282 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Data: 76562 5512464 [ 0 0 76562 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 1032 74304 [ 0 0 0 0 1032 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 76691 5521752 [ 0 0 0 0 76691 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 77013 616104 [ 0 0 0 77013 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 76694 613552 [ 0 0 76694 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Data: 76026 5473872 [ 0 0 76026 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 989 71208 [ 0 0 0 0 989 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 4.45778 - links_utilized_percent_switch_5_link_0: 4.44972 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 4.46585 bw: 16000 base_latency: 1 +links_utilized_percent_switch_5: 4.47561 + links_utilized_percent_switch_5_link_0: 4.46773 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 4.4835 bw: 16000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 77228 617824 [ 0 0 0 77228 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 76883 615064 [ 0 0 76883 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Data: 76151 5482872 [ 0 0 76151 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 1078 77616 [ 0 0 0 0 1078 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 76762 5526864 [ 0 0 0 0 76762 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 77096 616768 [ 0 0 0 77096 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 76764 614112 [ 0 0 76764 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Data: 76109 5479848 [ 0 0 76109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 991 71352 [ 0 0 0 0 991 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 4.46993 - links_utilized_percent_switch_6_link_0: 4.46316 bw: 16000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 4.4767 bw: 16000 base_latency: 1 +links_utilized_percent_switch_6: 4.47463 + links_utilized_percent_switch_6_link_0: 4.46749 bw: 16000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 4.48176 bw: 16000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 77119 5552568 [ 0 0 0 0 77119 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 77408 619264 [ 0 0 0 77408 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 77121 616968 [ 0 0 77121 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Data: 76391 5500152 [ 0 0 76391 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 1020 73440 [ 0 0 0 0 1020 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 77064 616512 [ 0 0 0 77064 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 76763 614104 [ 0 0 76763 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Data: 76075 5477400 [ 0 0 76075 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 992 71424 [ 0 0 0 0 992 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 4.44875 - links_utilized_percent_switch_7_link_0: 4.44123 bw: 16000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 4.45627 bw: 16000 base_latency: 1 +links_utilized_percent_switch_7: 4.46521 + links_utilized_percent_switch_7_link_0: 4.45799 bw: 16000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 4.47243 bw: 16000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 76737 5525064 [ 0 0 0 0 76737 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 77056 616448 [ 0 0 0 77056 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 76740 613920 [ 0 0 76740 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Data: 76043 5475096 [ 0 0 76043 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 76597 5514984 [ 0 0 0 0 76597 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 76907 615256 [ 0 0 0 76907 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 76598 612784 [ 0 0 76598 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Data: 75890 5464080 [ 0 0 75890 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 1017 73224 [ 0 0 0 0 1017 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 35.2892 - links_utilized_percent_switch_8_link_0: 35.3495 bw: 16000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 35.229 bw: 16000 base_latency: 1 +links_utilized_percent_switch_8: 35.2846 + links_utilized_percent_switch_8_link_0: 35.3449 bw: 16000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 35.2243 bw: 16000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 616139 4929112 [ 0 0 616139 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Data: 610466 43953552 [ 0 0 610466 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 607869 43766568 [ 0 0 0 0 607869 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 618697 4949576 [ 0 0 0 618697 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 612566 4900528 [ 0 0 612566 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 606981 43702632 [ 0 0 606981 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 604395 43516440 [ 0 0 0 0 604395 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 615121 4920968 [ 0 0 0 615121 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 7.88981 - links_utilized_percent_switch_9_link_0: 4.47733 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 4.46635 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 4.44489 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 4.44343 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 4.4727 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 4.44972 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 4.46316 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 4.44123 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 35.3495 bw: 16000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 77689 621512 [ 0 0 0 77689 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 77170 5556240 [ 0 0 0 0 77170 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 77501 620008 [ 0 0 0 77501 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Writeback_Control: 77121 616968 [ 0 0 0 77121 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 76774 5527728 [ 0 0 0 0 76774 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Writeback_Control: 77103 616824 [ 0 0 0 77103 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 77282 5564304 [ 0 0 0 0 77282 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Writeback_Control: 77591 620728 [ 0 0 0 77591 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Writeback_Control: 77228 617824 [ 0 0 0 77228 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 77119 5552568 [ 0 0 0 0 77119 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Writeback_Control: 77408 619264 [ 0 0 0 77408 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 76737 5525064 [ 0 0 0 0 76737 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Writeback_Control: 77056 616448 [ 0 0 0 77056 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Control: 616139 4929112 [ 0 0 616139 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Data: 610466 43953552 [ 0 0 610466 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 7.88847 + links_utilized_percent_switch_9_link_0: 4.46588 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 4.45628 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 4.43569 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 4.43679 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 4.46353 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 4.46773 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 4.46749 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 4.45799 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 35.3449 bw: 16000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 77065 616520 [ 0 0 0 77065 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 76567 5512824 [ 0 0 0 0 76567 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 76882 615056 [ 0 0 0 76882 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 76213 5487336 [ 0 0 0 0 76213 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 76529 612232 [ 0 0 0 76529 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 76230 5488560 [ 0 0 0 0 76230 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 76565 612520 [ 0 0 0 76565 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 76691 5521752 [ 0 0 0 0 76691 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 77013 616104 [ 0 0 0 77013 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 76762 5526864 [ 0 0 0 0 76762 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 77096 616768 [ 0 0 0 77096 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 77064 616512 [ 0 0 0 77064 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 76597 5514984 [ 0 0 0 0 76597 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 76907 615256 [ 0 0 0 76907 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Control: 612566 4900528 [ 0 0 612566 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Data: 606981 43702632 [ 0 0 606981 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.cacheMemory - system.l1_cntrl0.cacheMemory_total_misses: 77364 - system.l1_cntrl0.cacheMemory_total_demand_misses: 77364 + system.l1_cntrl0.cacheMemory_total_misses: 76731 + system.l1_cntrl0.cacheMemory_total_demand_misses: 76731 system.l1_cntrl0.cacheMemory_total_prefetches: 0 system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.cacheMemory_request_type_LD: 65.016% - system.l1_cntrl0.cacheMemory_request_type_ST: 34.984% + system.l1_cntrl0.cacheMemory_request_type_LD: 65.0962% + system.l1_cntrl0.cacheMemory_request_type_ST: 34.9038% - system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 77364 100% + system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 76731 100% --- L1Cache --- - Event Counts - -Load [50042 50017 50024 50037 50299 50232 49853 49771 ] 400275 +Load [49593 49882 49908 50150 49949 49848 49638 49304 ] 398272 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [27243 26866 27097 26703 27065 26941 26948 27004 ] 215867 -Data [77282 76881 77119 76737 77360 77170 76800 76774 ] 616123 -Fwd_GETX [1032 1078 1020 1018 995 1047 999 1066 ] 8255 +Store [27101 26882 26855 26448 26782 26721 26578 26927 ] 214294 +Data [76691 76762 76761 76597 76730 76567 76213 76230 ] 612551 +Fwd_GETX [989 991 992 1017 1040 1030 1037 1060 ] 8156 Inv [0 0 0 0 0 0 0 0 ] 0 -Replacement [77281 76879 77117 76736 77360 77169 76797 76771 ] 616110 -Writeback_Ack [76243 75800 76094 75713 76359 76118 75798 75703 ] 607828 -Writeback_Nack [316 350 294 325 335 336 324 334 ] 2614 +Replacement [76690 76760 76759 76594 76727 76565 76212 76227 ] 612534 +Writeback_Ack [75699 75765 75764 75577 75686 75534 75170 75167 ] 604362 +Writeback_Nack [325 340 308 313 339 318 322 338 ] 2603 - Transitions - -I Load [50042 50017 50024 50037 50299 50232 49853 49771 ] 400275 +I Load [49593 49882 49908 50150 49949 49848 49638 49304 ] 398272 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [27243 26866 27097 26703 27065 26941 26948 27004 ] 215867 +I Store [27101 26882 26855 26448 26782 26721 26578 26927 ] 214294 I Inv [0 0 0 0 0 0 0 0 ] 0 -I Replacement [716 728 726 693 660 711 675 732 ] 5641 +I Replacement [664 651 684 704 701 712 715 722 ] 5553 -II Writeback_Nack [316 350 294 325 335 336 324 334 ] 2614 +II Writeback_Nack [325 340 308 313 339 318 322 338 ] 2603 M Load [0 0 0 0 0 0 0 0 ] 0 M Ifetch [0 0 0 0 0 0 0 0 ] 0 M Store [0 0 0 0 0 0 0 0 ] 0 -M Fwd_GETX [716 728 726 693 660 711 675 732 ] 5641 +M Fwd_GETX [664 651 684 704 701 712 715 722 ] 5553 M Inv [0 0 0 0 0 0 0 0 ] 0 -M Replacement [76565 76151 76391 76043 76700 76458 76122 76039 ] 610469 +M Replacement [76026 76109 76075 75890 76026 75853 75497 75505 ] 606981 -MI Fwd_GETX [316 350 294 325 335 336 324 334 ] 2614 +MI Fwd_GETX [325 340 308 313 339 318 322 338 ] 2603 MI Inv [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [76243 75800 76094 75713 76359 76118 75798 75703 ] 607828 +MI Writeback_Ack [75699 75765 75764 75577 75686 75534 75170 75167 ] 604362 MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Data [50041 50016 50022 50034 50297 50229 49853 49770 ] 400262 +IS Data [49590 49880 49906 50150 49949 49846 49635 49303 ] 398259 -IM Data [27241 26865 27097 26703 27063 26941 26947 27004 ] 215861 +IM Data [27101 26882 26855 26447 26781 26721 26578 26927 ] 214292 Cache Stats: system.l1_cntrl1.cacheMemory - system.l1_cntrl1.cacheMemory_total_misses: 77173 - system.l1_cntrl1.cacheMemory_total_demand_misses: 77173 + system.l1_cntrl1.cacheMemory_total_misses: 76569 + system.l1_cntrl1.cacheMemory_total_demand_misses: 76569 system.l1_cntrl1.cacheMemory_total_prefetches: 0 system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.cacheMemory_request_type_LD: 65.0901% - system.l1_cntrl1.cacheMemory_request_type_ST: 34.9099% + system.l1_cntrl1.cacheMemory_request_type_LD: 65.1021% + system.l1_cntrl1.cacheMemory_request_type_ST: 34.8979% - system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 77173 100% + system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 76569 100% Cache Stats: system.l1_cntrl2.cacheMemory - system.l1_cntrl2.cacheMemory_total_misses: 76801 - system.l1_cntrl2.cacheMemory_total_demand_misses: 76801 + system.l1_cntrl2.cacheMemory_total_misses: 76216 + system.l1_cntrl2.cacheMemory_total_demand_misses: 76216 system.l1_cntrl2.cacheMemory_total_prefetches: 0 system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.cacheMemory_request_type_LD: 64.9119% - system.l1_cntrl2.cacheMemory_request_type_ST: 35.0881% + system.l1_cntrl2.cacheMemory_request_type_LD: 65.1281% + system.l1_cntrl2.cacheMemory_request_type_ST: 34.8719% - system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76801 100% + system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76216 100% Cache Stats: system.l1_cntrl3.cacheMemory - system.l1_cntrl3.cacheMemory_total_misses: 76775 - system.l1_cntrl3.cacheMemory_total_demand_misses: 76775 + system.l1_cntrl3.cacheMemory_total_misses: 76231 + system.l1_cntrl3.cacheMemory_total_demand_misses: 76231 system.l1_cntrl3.cacheMemory_total_prefetches: 0 system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.cacheMemory_request_type_LD: 64.8271% - system.l1_cntrl3.cacheMemory_request_type_ST: 35.1729% + system.l1_cntrl3.cacheMemory_request_type_LD: 64.6771% + system.l1_cntrl3.cacheMemory_request_type_ST: 35.3229% - system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76775 100% + system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76231 100% Cache Stats: system.l1_cntrl4.cacheMemory - system.l1_cntrl4.cacheMemory_total_misses: 77285 - system.l1_cntrl4.cacheMemory_total_demand_misses: 77285 + system.l1_cntrl4.cacheMemory_total_misses: 76694 + system.l1_cntrl4.cacheMemory_total_demand_misses: 76694 system.l1_cntrl4.cacheMemory_total_prefetches: 0 system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.cacheMemory_request_type_LD: 64.75% - system.l1_cntrl4.cacheMemory_request_type_ST: 35.25% + system.l1_cntrl4.cacheMemory_request_type_LD: 64.6635% + system.l1_cntrl4.cacheMemory_request_type_ST: 35.3365% - system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 77285 100% + system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 76694 100% Cache Stats: system.l1_cntrl5.cacheMemory - system.l1_cntrl5.cacheMemory_total_misses: 76883 - system.l1_cntrl5.cacheMemory_total_demand_misses: 76883 + system.l1_cntrl5.cacheMemory_total_misses: 76764 + system.l1_cntrl5.cacheMemory_total_demand_misses: 76764 system.l1_cntrl5.cacheMemory_total_prefetches: 0 system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.cacheMemory_request_type_LD: 65.056% - system.l1_cntrl5.cacheMemory_request_type_ST: 34.944% + system.l1_cntrl5.cacheMemory_request_type_LD: 64.981% + system.l1_cntrl5.cacheMemory_request_type_ST: 35.019% - system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 76883 100% + system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 76764 100% Cache Stats: system.l1_cntrl6.cacheMemory - system.l1_cntrl6.cacheMemory_total_misses: 77121 - system.l1_cntrl6.cacheMemory_total_demand_misses: 77121 + system.l1_cntrl6.cacheMemory_total_misses: 76763 + system.l1_cntrl6.cacheMemory_total_demand_misses: 76763 system.l1_cntrl6.cacheMemory_total_prefetches: 0 system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.cacheMemory_request_type_LD: 64.8643% - system.l1_cntrl6.cacheMemory_request_type_ST: 35.1357% + system.l1_cntrl6.cacheMemory_request_type_LD: 65.0157% + system.l1_cntrl6.cacheMemory_request_type_ST: 34.9843% - system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 77121 100% + system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 76763 100% Cache Stats: system.l1_cntrl7.cacheMemory - system.l1_cntrl7.cacheMemory_total_misses: 76740 - system.l1_cntrl7.cacheMemory_total_demand_misses: 76740 + system.l1_cntrl7.cacheMemory_total_misses: 76598 + system.l1_cntrl7.cacheMemory_total_demand_misses: 76598 system.l1_cntrl7.cacheMemory_total_prefetches: 0 system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.cacheMemory_request_type_LD: 65.2033% - system.l1_cntrl7.cacheMemory_request_type_ST: 34.7967% + system.l1_cntrl7.cacheMemory_request_type_LD: 65.4717% + system.l1_cntrl7.cacheMemory_request_type_ST: 34.5283% - system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 76740 100% + system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 76598 100% Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 1215736 - memory_reads: 607873 - memory_writes: 607828 - memory_refreshes: 60020 - memory_total_request_delays: 87259380 - memory_delays_per_request: 71.7749 - memory_delays_in_input_queue: 1519458 - memory_delays_behind_head_of_bank_queue: 40027777 - memory_delays_stalled_at_head_of_bank_queue: 45712145 - memory_stalls_for_bank_busy: 7071199 + memory_total_requests: 1208787 + memory_reads: 604397 + memory_writes: 604365 + memory_refreshes: 59684 + memory_total_request_delays: 86764072 + memory_delays_per_request: 71.7778 + memory_delays_in_input_queue: 1509968 + memory_delays_behind_head_of_bank_queue: 39767134 + memory_delays_stalled_at_head_of_bank_queue: 45486970 + memory_stalls_for_bank_busy: 7019107 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 11246699 - memory_stalls_for_arbitration: 9161203 - memory_stalls_for_bus: 12538876 + memory_stalls_for_anti_starvation: 11191838 + memory_stalls_for_arbitration: 9120916 + memory_stalls_for_bus: 12483705 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 4625197 - memory_stalls_for_read_read_turnaround: 1068971 - accesses_per_bank: 38200 37933 37788 38170 38170 38159 38358 38044 38330 38092 38142 38320 37763 37679 37948 38038 37829 37792 38064 38023 38122 37894 38063 37979 37916 37422 38015 37136 37884 38037 38326 38100 + memory_stalls_for_read_write_turnaround: 4604021 + memory_stalls_for_read_read_turnaround: 1067383 + accesses_per_bank: 38081 37280 38059 37993 37808 37669 38264 38058 37708 37676 37829 37380 37422 38256 37284 38186 37917 37744 38412 38248 37780 37359 37760 37766 37532 37908 37452 37826 37364 37732 37412 37622 --- Directory --- - Event Counts - -GETX [786348 ] 786348 +GETX [784980 ] 784980 GETS [0 ] 0 -PUTX [607852 ] 607852 -PUTX_NotOwner [2614 ] 2614 +PUTX [604378 ] 604378 +PUTX_NotOwner [2603 ] 2603 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [607869 ] 607869 -Memory_Ack [607828 ] 607828 +Memory_Data [604396 ] 604396 +Memory_Ack [604362 ] 604362 - Transitions - -I GETX [607884 ] 607884 +I GETX [604409 ] 604409 I PUTX_NotOwner [0 ] 0 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 -M GETX [8255 ] 8255 -M PUTX [607852 ] 607852 -M PUTX_NotOwner [2614 ] 2614 +M GETX [8156 ] 8156 +M PUTX [604378 ] 604378 +M PUTX_NotOwner [2603 ] 2603 M DMA_READ [0 ] 0 M DMA_WRITE [0 ] 0 @@ -428,21 +428,21 @@ M_DWRI Memory_Ack [0 ] 0 M_DRDI GETX [0 ] 0 M_DRDI Memory_Ack [0 ] 0 -IM GETX [65216 ] 65216 +IM GETX [64832 ] 64832 IM GETS [0 ] 0 IM PUTX [0 ] 0 IM PUTX_NotOwner [0 ] 0 IM DMA_READ [0 ] 0 IM DMA_WRITE [0 ] 0 -IM Memory_Data [607869 ] 607869 +IM Memory_Data [604396 ] 604396 -MI GETX [104993 ] 104993 +MI GETX [107583 ] 107583 MI GETS [0 ] 0 MI PUTX [0 ] 0 MI PUTX_NotOwner [0 ] 0 MI DMA_READ [0 ] 0 MI DMA_WRITE [0 ] 0 -MI Memory_Ack [607828 ] 607828 +MI Memory_Ack [604362 ] 604362 ID GETX [0 ] 0 ID GETS [0 ] 0 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr index b60dc70fa..635c424d0 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,74 +1,82 @@ -system.cpu0: completed 10000 read, 5375 write accesses @856398 -system.cpu7: completed 10000 read, 5367 write accesses @862743 -system.cpu4: completed 10000 read, 5441 write accesses @863378 -system.cpu5: completed 10000 read, 5493 write accesses @863384 -system.cpu6: completed 10000 read, 5390 write accesses @871145 -system.cpu2: completed 10000 read, 5481 write accesses @872080 -system.cpu3: completed 10000 read, 5307 write accesses @887641 -system.cpu1: completed 10000 read, 5435 write accesses @888236 -system.cpu0: completed 20000 read, 10720 write accesses @1697024 -system.cpu4: completed 20000 read, 10674 write accesses @1708688 -system.cpu2: completed 20000 read, 10679 write accesses @1718143 -system.cpu7: completed 20000 read, 10680 write accesses @1726961 -system.cpu5: completed 20000 read, 10844 write accesses @1731599 -system.cpu6: completed 20000 read, 10755 write accesses @1744688 -system.cpu1: completed 20000 read, 10834 write accesses @1760840 -system.cpu3: completed 20000 read, 10861 write accesses @1783274 -system.cpu0: completed 30000 read, 16096 write accesses @2576060 -system.cpu7: completed 30000 read, 16150 write accesses @2587892 -system.cpu2: completed 30000 read, 16059 write accesses @2589422 -system.cpu4: completed 30000 read, 16216 write accesses @2589611 -system.cpu5: completed 30000 read, 16311 write accesses @2606290 -system.cpu1: completed 30000 read, 16085 write accesses @2614280 -system.cpu6: completed 30000 read, 16250 write accesses @2617742 -system.cpu3: completed 30000 read, 16179 write accesses @2640821 -system.cpu0: completed 40000 read, 21491 write accesses @3463636 -system.cpu5: completed 40000 read, 21654 write accesses @3466586 -system.cpu4: completed 40000 read, 21608 write accesses @3466694 -system.cpu6: completed 40000 read, 21630 write accesses @3468467 -system.cpu2: completed 40000 read, 21509 write accesses @3470109 -system.cpu7: completed 40000 read, 21495 write accesses @3471086 -system.cpu1: completed 40000 read, 21461 write accesses @3476351 -system.cpu3: completed 40000 read, 21515 write accesses @3523754 -system.cpu4: completed 50000 read, 27063 write accesses @4330388 -system.cpu6: completed 50000 read, 27077 write accesses @4332246 -system.cpu5: completed 50000 read, 27022 write accesses @4334407 -system.cpu1: completed 50000 read, 26821 write accesses @4334861 -system.cpu2: completed 50000 read, 27005 write accesses @4339007 -system.cpu0: completed 50000 read, 27011 write accesses @4351000 -system.cpu7: completed 50000 read, 27023 write accesses @4371905 -system.cpu3: completed 50000 read, 26894 write accesses @4421954 -system.cpu6: completed 60000 read, 32380 write accesses @5185697 -system.cpu2: completed 60000 read, 32320 write accesses @5197049 -system.cpu1: completed 60000 read, 32167 write accesses @5197304 -system.cpu4: completed 60000 read, 32460 write accesses @5201909 -system.cpu5: completed 60000 read, 32453 write accesses @5222405 -system.cpu0: completed 60000 read, 32443 write accesses @5224148 -system.cpu7: completed 60000 read, 32400 write accesses @5229110 -system.cpu3: completed 60000 read, 32209 write accesses @5281507 -system.cpu6: completed 70000 read, 37664 write accesses @6045459 -system.cpu4: completed 70000 read, 37836 write accesses @6058226 -system.cpu1: completed 70000 read, 37476 write accesses @6063535 -system.cpu2: completed 70000 read, 37820 write accesses @6074654 -system.cpu5: completed 70000 read, 37785 write accesses @6097069 -system.cpu7: completed 70000 read, 37611 write accesses @6097865 -system.cpu0: completed 70000 read, 37769 write accesses @6104873 -system.cpu3: completed 70000 read, 37585 write accesses @6142157 -system.cpu4: completed 80000 read, 43086 write accesses @6914689 -system.cpu6: completed 80000 read, 42941 write accesses @6923107 -system.cpu1: completed 80000 read, 42761 write accesses @6929131 -system.cpu2: completed 80000 read, 43045 write accesses @6933740 -system.cpu5: completed 80000 read, 43067 write accesses @6962084 -system.cpu7: completed 80000 read, 43014 write accesses @6974408 -system.cpu0: completed 80000 read, 43066 write accesses @6974987 -system.cpu3: completed 80000 read, 43041 write accesses @7015199 -system.cpu4: completed 90000 read, 48630 write accesses @7775720 -system.cpu1: completed 90000 read, 48156 write accesses @7793810 -system.cpu6: completed 90000 read, 48441 write accesses @7801463 -system.cpu2: completed 90000 read, 48518 write accesses @7804520 -system.cpu5: completed 90000 read, 48378 write accesses @7834475 -system.cpu0: completed 90000 read, 48500 write accesses @7849400 -system.cpu7: completed 90000 read, 48425 write accesses @7864016 -system.cpu3: completed 90000 read, 48443 write accesses @7889702 -system.cpu4: completed 100000 read, 54108 write accesses @8642753 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 +system.cpu4: completed 10000 read, 5220 write accesses @847627 +system.cpu7: completed 10000 read, 5333 write accesses @853307 +system.cpu1: completed 10000 read, 5223 write accesses @856720 +system.cpu2: completed 10000 read, 5343 write accesses @856757 +system.cpu0: completed 10000 read, 5346 write accesses @859240 +system.cpu3: completed 10000 read, 5325 write accesses @862609 +system.cpu5: completed 10000 read, 5417 write accesses @867929 +system.cpu6: completed 10000 read, 5429 write accesses @870556 +system.cpu7: completed 20000 read, 10546 write accesses @1710362 +system.cpu3: completed 20000 read, 10676 write accesses @1715625 +system.cpu2: completed 20000 read, 10865 write accesses @1717913 +system.cpu1: completed 20000 read, 10472 write accesses @1718245 +system.cpu4: completed 20000 read, 10710 write accesses @1723388 +system.cpu0: completed 20000 read, 10695 write accesses @1731500 +system.cpu6: completed 20000 read, 10923 write accesses @1732721 +system.cpu5: completed 20000 read, 10714 write accesses @1741949 +system.cpu3: completed 30000 read, 16111 write accesses @2561534 +system.cpu7: completed 30000 read, 15801 write accesses @2564909 +system.cpu0: completed 30000 read, 15963 write accesses @2570530 +system.cpu2: completed 30000 read, 16167 write accesses @2572444 +system.cpu4: completed 30000 read, 16049 write accesses @2589273 +system.cpu6: completed 30000 read, 16204 write accesses @2590810 +system.cpu5: completed 30000 read, 15952 write accesses @2600828 +system.cpu1: completed 30000 read, 15999 write accesses @2614055 +system.cpu7: completed 40000 read, 21145 write accesses @3411914 +system.cpu0: completed 40000 read, 21350 write accesses @3420253 +system.cpu2: completed 40000 read, 21529 write accesses @3428587 +system.cpu3: completed 40000 read, 21460 write accesses @3434840 +system.cpu6: completed 40000 read, 21523 write accesses @3443024 +system.cpu4: completed 40000 read, 21533 write accesses @3467265 +system.cpu5: completed 40000 read, 21305 write accesses @3470138 +system.cpu1: completed 40000 read, 21461 write accesses @3492145 +system.cpu7: completed 50000 read, 26466 write accesses @4272276 +system.cpu2: completed 50000 read, 26738 write accesses @4280117 +system.cpu0: completed 50000 read, 26773 write accesses @4295924 +system.cpu6: completed 50000 read, 26837 write accesses @4299550 +system.cpu3: completed 50000 read, 26845 write accesses @4312607 +system.cpu5: completed 50000 read, 26698 write accesses @4316933 +system.cpu4: completed 50000 read, 26954 write accesses @4344468 +system.cpu1: completed 50000 read, 26769 write accesses @4358867 +system.cpu7: completed 60000 read, 31755 write accesses @5113250 +system.cpu0: completed 60000 read, 32149 write accesses @5156117 +system.cpu2: completed 60000 read, 32096 write accesses @5160599 +system.cpu6: completed 60000 read, 32168 write accesses @5173313 +system.cpu3: completed 60000 read, 32243 write accesses @5178563 +system.cpu5: completed 60000 read, 32247 write accesses @5183771 +system.cpu4: completed 60000 read, 32381 write accesses @5220290 +system.cpu1: completed 60000 read, 32294 write accesses @5220865 +system.cpu7: completed 70000 read, 37125 write accesses @5977718 +system.cpu0: completed 70000 read, 37636 write accesses @6026353 +system.cpu6: completed 70000 read, 37517 write accesses @6027404 +system.cpu2: completed 70000 read, 37549 write accesses @6039275 +system.cpu3: completed 70000 read, 37632 write accesses @6040322 +system.cpu5: completed 70000 read, 37704 write accesses @6061913 +system.cpu1: completed 70000 read, 37680 write accesses @6066326 +system.cpu4: completed 70000 read, 37794 write accesses @6080683 +system.cpu7: completed 80000 read, 42401 write accesses @6837718 +system.cpu0: completed 80000 read, 43037 write accesses @6872986 +system.cpu6: completed 80000 read, 42861 write accesses @6886837 +system.cpu3: completed 80000 read, 43022 write accesses @6895964 +system.cpu2: completed 80000 read, 43017 write accesses @6904754 +system.cpu5: completed 80000 read, 43129 write accesses @6910157 +system.cpu1: completed 80000 read, 42955 write accesses @6929917 +system.cpu4: completed 80000 read, 43333 write accesses @6955798 +system.cpu7: completed 90000 read, 47777 write accesses @7715699 +system.cpu0: completed 90000 read, 48512 write accesses @7730512 +system.cpu6: completed 90000 read, 48227 write accesses @7747760 +system.cpu1: completed 90000 read, 48224 write accesses @7775090 +system.cpu2: completed 90000 read, 48474 write accesses @7775105 +system.cpu3: completed 90000 read, 48528 write accesses @7778761 +system.cpu5: completed 90000 read, 48627 write accesses @7786116 +system.cpu4: completed 90000 read, 48988 write accesses @7814863 +system.cpu7: completed 100000 read, 53297 write accesses @8594451 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index a9a755cda..de4675b40 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.008643 # Number of seconds simulated -sim_ticks 8642753 # Number of ticks simulated -final_tick 8642753 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.008594 # Number of seconds simulated +sim_ticks 8594451 # Number of ticks simulated +final_tick 8594451 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 200801 # Simulator tick rate (ticks/s) -host_mem_usage 409268 # Number of bytes of host memory used -host_seconds 43.04 # Real time elapsed on the host +host_tick_rate 108749 # Simulator tick rate (ticks/s) +host_mem_usage 418376 # Number of bytes of host memory used +host_seconds 79.03 # Real time elapsed on the host system.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -55,29 +55,29 @@ system.l1_cntrl3.cacheMemory.num_tag_array_reads 0 system.l1_cntrl3.cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l1_cntrl3.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l1_cntrl3.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99336 # number of read accesses completed -system.cpu0.num_writes 53454 # number of write accesses completed +system.cpu0.num_reads 99932 # number of read accesses completed +system.cpu0.num_writes 53945 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99686 # number of read accesses completed -system.cpu1.num_writes 53261 # number of write accesses completed +system.cpu1.num_reads 99540 # number of read accesses completed +system.cpu1.num_writes 53424 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99694 # number of read accesses completed -system.cpu2.num_writes 53721 # number of write accesses completed +system.cpu2.num_reads 99404 # number of read accesses completed +system.cpu2.num_writes 53533 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98699 # number of read accesses completed -system.cpu3.num_writes 53080 # number of write accesses completed +system.cpu3.num_reads 99305 # number of read accesses completed +system.cpu3.num_writes 53683 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 54108 # number of write accesses completed +system.cpu4.num_reads 99222 # number of read accesses completed +system.cpu4.num_writes 53970 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99065 # number of read accesses completed -system.cpu5.num_writes 53284 # number of write accesses completed +system.cpu5.num_reads 99453 # number of read accesses completed +system.cpu5.num_writes 53665 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99678 # number of read accesses completed -system.cpu6.num_writes 53683 # number of write accesses completed +system.cpu6.num_reads 99859 # number of read accesses completed +system.cpu6.num_writes 53616 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98986 # number of read accesses completed -system.cpu7.num_writes 53291 # number of write accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 53297 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr index e47dd4681..41e8d0489 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu1: completed 10000 read, 5306 write accesses @32059956 -system.cpu6: completed 10000 read, 5293 write accesses @32275139 -system.cpu7: completed 10000 read, 5474 write accesses @32325344 -system.cpu3: completed 10000 read, 5220 write accesses @32355571 -system.cpu2: completed 10000 read, 5392 write accesses @32378350 -system.cpu4: completed 10000 read, 5411 write accesses @32427761 -system.cpu5: completed 10000 read, 5317 write accesses @32754271 -system.cpu0: completed 10000 read, 5539 write accesses @32833317 -system.cpu1: completed 20000 read, 10662 write accesses @55871338 -system.cpu3: completed 20000 read, 10529 write accesses @56061050 -system.cpu2: completed 20000 read, 10630 write accesses @56140317 -system.cpu4: completed 20000 read, 10816 write accesses @56432989 -system.cpu7: completed 20000 read, 10899 write accesses @56513495 -system.cpu6: completed 20000 read, 10845 write accesses @56565627 -system.cpu5: completed 20000 read, 10626 write accesses @57072718 -system.cpu0: completed 20000 read, 11113 write accesses @57586418 -system.cpu2: completed 30000 read, 16017 write accesses @79407742 -system.cpu1: completed 30000 read, 16151 write accesses @79725766 -system.cpu3: completed 30000 read, 15856 write accesses @79754749 -system.cpu6: completed 30000 read, 16195 write accesses @80206236 -system.cpu4: completed 30000 read, 16333 write accesses @80758801 -system.cpu7: completed 30000 read, 16467 write accesses @80845126 -system.cpu5: completed 30000 read, 16040 write accesses @81280754 -system.cpu0: completed 30000 read, 16740 write accesses @81836055 -system.cpu3: completed 40000 read, 21110 write accesses @102187140 -system.cpu1: completed 40000 read, 21543 write accesses @102788912 -system.cpu2: completed 40000 read, 21441 write accesses @103129249 -system.cpu6: completed 40000 read, 21490 write accesses @103224826 -system.cpu7: completed 40000 read, 21781 write accesses @104248123 -system.cpu4: completed 40000 read, 21750 write accesses @104259134 -system.cpu5: completed 40000 read, 21538 write accesses @104623876 -system.cpu0: completed 40000 read, 22049 write accesses @105025965 -system.cpu3: completed 50000 read, 26445 write accesses @126560435 -system.cpu1: completed 50000 read, 27002 write accesses @127296516 -system.cpu6: completed 50000 read, 26751 write accesses @127652113 -system.cpu2: completed 50000 read, 26915 write accesses @127863043 -system.cpu5: completed 50000 read, 26795 write accesses @128758388 -system.cpu7: completed 50000 read, 27154 write accesses @128837444 -system.cpu4: completed 50000 read, 27195 write accesses @128884190 -system.cpu0: completed 50000 read, 27370 write accesses @129107611 -system.cpu3: completed 60000 read, 31813 write accesses @150500482 -system.cpu1: completed 60000 read, 32357 write accesses @151324410 -system.cpu6: completed 60000 read, 32276 write accesses @152241130 -system.cpu2: completed 60000 read, 32455 write accesses @152510509 -system.cpu4: completed 60000 read, 32625 write accesses @152799581 -system.cpu5: completed 60000 read, 32145 write accesses @152911895 -system.cpu7: completed 60000 read, 32658 write accesses @153053742 -system.cpu0: completed 60000 read, 32669 write accesses @153243898 -system.cpu3: completed 70000 read, 37148 write accesses @174290350 -system.cpu1: completed 70000 read, 37719 write accesses @175320592 -system.cpu6: completed 70000 read, 37631 write accesses @176658170 -system.cpu4: completed 70000 read, 37993 write accesses @176957081 -system.cpu2: completed 70000 read, 37835 write accesses @177152761 -system.cpu5: completed 70000 read, 37525 write accesses @177243860 -system.cpu7: completed 70000 read, 38186 write accesses @177800828 -system.cpu0: completed 70000 read, 38119 write accesses @178467538 -system.cpu3: completed 80000 read, 42562 write accesses @198146360 -system.cpu1: completed 80000 read, 43234 write accesses @199454254 -system.cpu4: completed 80000 read, 43314 write accesses @200406450 -system.cpu5: completed 80000 read, 42980 write accesses @200646810 -system.cpu2: completed 80000 read, 43306 write accesses @200927158 -system.cpu6: completed 80000 read, 43086 write accesses @200956315 -system.cpu7: completed 80000 read, 43539 write accesses @201412026 -system.cpu0: completed 80000 read, 43547 write accesses @202267757 -system.cpu3: completed 90000 read, 47828 write accesses @222074356 -system.cpu1: completed 90000 read, 48627 write accesses @223900144 -system.cpu5: completed 90000 read, 48291 write accesses @224840552 -system.cpu4: completed 90000 read, 48802 write accesses @224884716 -system.cpu6: completed 90000 read, 48479 write accesses @224938254 -system.cpu2: completed 90000 read, 48708 write accesses @225566271 -system.cpu7: completed 90000 read, 48770 write accesses @225725770 -system.cpu0: completed 90000 read, 48880 write accesses @226596871 -system.cpu3: completed 100000 read, 53214 write accesses @246648467 +system.cpu0: completed 10000 read, 5290 write accesses @74885500 +system.cpu7: completed 10000 read, 5447 write accesses @78072500 +system.cpu2: completed 10000 read, 5330 write accesses @78536500 +system.cpu5: completed 10000 read, 5401 write accesses @79479500 +system.cpu3: completed 10000 read, 5406 write accesses @80479500 +system.cpu1: completed 10000 read, 5452 write accesses @80823500 +system.cpu4: completed 10000 read, 5330 write accesses @82914500 +system.cpu6: completed 10000 read, 5363 write accesses @83627000 +system.cpu7: completed 20000 read, 10668 write accesses @150917000 +system.cpu0: completed 20000 read, 10683 write accesses @151253500 +system.cpu5: completed 20000 read, 10718 write accesses @151911500 +system.cpu2: completed 20000 read, 10688 write accesses @152119000 +system.cpu3: completed 20000 read, 10954 write accesses @159391000 +system.cpu6: completed 20000 read, 10780 write accesses @160278500 +system.cpu1: completed 20000 read, 10888 write accesses @160835000 +system.cpu4: completed 20000 read, 10745 write accesses @162137000 +system.cpu2: completed 30000 read, 16060 write accesses @225600500 +system.cpu0: completed 30000 read, 16073 write accesses @226217000 +system.cpu7: completed 30000 read, 15898 write accesses @227550500 +system.cpu5: completed 30000 read, 16102 write accesses @230201000 +system.cpu3: completed 30000 read, 16375 write accesses @233880500 +system.cpu1: completed 30000 read, 16184 write accesses @234964500 +system.cpu6: completed 30000 read, 16132 write accesses @236785500 +system.cpu4: completed 30000 read, 16103 write accesses @242571500 +system.cpu7: completed 40000 read, 21206 write accesses @298942500 +system.cpu2: completed 40000 read, 21441 write accesses @299465500 +system.cpu0: completed 40000 read, 21388 write accesses @302202500 +system.cpu5: completed 40000 read, 21578 write accesses @308632000 +system.cpu6: completed 40000 read, 21492 write accesses @314697500 +system.cpu3: completed 40000 read, 22088 write accesses @315960000 +system.cpu4: completed 40000 read, 21590 write accesses @317147500 +system.cpu1: completed 40000 read, 21566 write accesses @317423500 +system.cpu7: completed 50000 read, 26570 write accesses @373251000 +system.cpu2: completed 50000 read, 26788 write accesses @373919000 +system.cpu0: completed 50000 read, 26897 write accesses @382805000 +system.cpu5: completed 50000 read, 27003 write accesses @384437500 +system.cpu3: completed 50000 read, 27349 write accesses @389623000 +system.cpu4: completed 50000 read, 26792 write accesses @389830500 +system.cpu6: completed 50000 read, 27002 write accesses @392270000 +system.cpu1: completed 50000 read, 26853 write accesses @392392000 +system.cpu7: completed 60000 read, 31855 write accesses @449936000 +system.cpu2: completed 60000 read, 32201 write accesses @452901500 +system.cpu0: completed 60000 read, 32209 write accesses @457331000 +system.cpu5: completed 60000 read, 32356 write accesses @458864500 +system.cpu4: completed 60000 read, 32204 write accesses @464577500 +system.cpu3: completed 60000 read, 32813 write accesses @468126500 +system.cpu6: completed 60000 read, 32463 write accesses @469913500 +system.cpu1: completed 60000 read, 32376 write accesses @472262000 +system.cpu7: completed 70000 read, 37203 write accesses @526760000 +system.cpu2: completed 70000 read, 37525 write accesses @530661000 +system.cpu5: completed 70000 read, 37749 write accesses @533141500 +system.cpu0: completed 70000 read, 37615 write accesses @537691500 +system.cpu3: completed 70000 read, 38216 write accesses @538787500 +system.cpu4: completed 70000 read, 37614 write accesses @545810500 +system.cpu6: completed 70000 read, 37722 write accesses @546307000 +system.cpu1: completed 70000 read, 37746 write accesses @546660500 +system.cpu7: completed 80000 read, 42460 write accesses @600681000 +system.cpu5: completed 80000 read, 42949 write accesses @604308500 +system.cpu2: completed 80000 read, 42841 write accesses @606628000 +system.cpu0: completed 80000 read, 43072 write accesses @615043500 +system.cpu3: completed 80000 read, 43808 write accesses @615907000 +system.cpu4: completed 80000 read, 43047 write accesses @622672500 +system.cpu6: completed 80000 read, 43213 write accesses @622720000 +system.cpu1: completed 80000 read, 43140 write accesses @626035000 +system.cpu2: completed 90000 read, 48140 write accesses @675974000 +system.cpu7: completed 90000 read, 48058 write accesses @680921000 +system.cpu5: completed 90000 read, 48486 write accesses @683376500 +system.cpu3: completed 90000 read, 49174 write accesses @687533500 +system.cpu0: completed 90000 read, 48447 write accesses @690023000 +system.cpu6: completed 90000 read, 48621 write accesses @702298000 +system.cpu4: completed 90000 read, 48429 write accesses @703717000 +system.cpu1: completed 90000 read, 48600 write accesses @705675000 +system.cpu2: completed 100000 read, 53454 write accesses @753126500 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index ed860ddcf..8e44f53e1 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:08:41 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest +gem5 compiled Oct 15 2012 19:23:25 +gem5 started Oct 15 2012 19:23:52 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 223713460 because maximum number of loads reached +Exiting @ tick 753126500 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 0a4a4cf1a..9268efa23 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,633 +1,634 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000761 # Number of seconds simulated -sim_ticks 761298000 # Number of ticks simulated -final_tick 761298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000753 # Number of seconds simulated +sim_ticks 753126500 # Number of ticks simulated +final_tick 753126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 219241825 # Simulator tick rate (ticks/s) -host_mem_usage 341324 # Number of bytes of host memory used -host_seconds 3.47 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 89717 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 92471 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 92156 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 88405 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 90559 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 92920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 90802 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 90403 # Number of bytes read from this memory -system.physmem.bytes_read::total 727433 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 479872 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5306 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5518 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5318 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5364 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory -system.physmem.bytes_written::total 522898 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11201 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11107 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11275 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89747 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7498 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5306 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5518 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5318 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5364 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50524 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 117847413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 121464919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 121051152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 116124041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 118953419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 122054701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 119272611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 118748506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 955516762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 630333982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7150945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6969675 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7248147 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6985438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6999887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7045861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7053742 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7062937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 686850616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 630333982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 124998358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 128434595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 128299299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 123109479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 125953306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 129100562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 126326353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 125811443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1642367378 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15728 # number of replacements -system.l2c.tagsinuse 804.643799 # Cycle average of tags in use -system.l2c.total_refs 152339 # Total number of references to valid blocks. -system.l2c.sampled_refs 16530 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.215910 # Average number of references to valid blocks. +host_tick_rate 111238456 # Simulator tick rate (ticks/s) +host_mem_usage 391924 # Number of bytes of host memory used +host_seconds 6.77 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 90167 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 90714 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 93247 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 94741 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 86405 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 91776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 89783 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 85071 # Number of bytes read from this memory +system.physmem.bytes_read::total 721904 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 471360 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5341 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5232 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5319 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5446 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5378 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5389 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5299 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5260 # Number of bytes written to this memory +system.physmem.bytes_written::total 514024 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11284 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10805 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88502 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7365 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5341 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5232 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5319 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5446 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5378 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5389 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5299 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5260 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50029 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 119723579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 120449885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 123813197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 125796928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 114728402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 121860006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 119213704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 112957119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 958542821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 625870953 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7091770 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6947040 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7062559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 7231189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7140899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7155504 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7036003 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 6984218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 682520134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 625870953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 126815349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 127396925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 130875756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 133028117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 121869301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 129015511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 126249707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 119941338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1641062956 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15498 # number of replacements +system.l2c.tagsinuse 803.451409 # Cycle average of tags in use +system.l2c.total_refs 150823 # Total number of references to valid blocks. +system.l2c.sampled_refs 16301 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.252377 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 741.658747 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.524103 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.613306 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.692083 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.940636 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.758878 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 8.184629 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 8.593994 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 7.677424 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.724276 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007348 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007435 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007512 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007755 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007577 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007993 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.008393 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.007497 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.785785 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 11015 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10772 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10969 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10886 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10950 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10937 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10991 # number of ReadReq hits -system.l2c.ReadReq_hits::total 87199 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 77421 # number of Writeback hits -system.l2c.Writeback_hits::total 77421 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 333 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 352 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 370 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 391 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 398 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2885 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2096 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2090 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2017 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2119 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2028 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2112 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2055 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16579 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 13111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12862 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12986 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12798 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13012 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 13049 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 13046 # number of demand (read+write) hits -system.l2c.demand_hits::total 103778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 13111 # number of overall hits -system.l2c.overall_hits::cpu1 12862 # number of overall hits -system.l2c.overall_hits::cpu2 12986 # number of overall hits -system.l2c.overall_hits::cpu3 12798 # number of overall hits -system.l2c.overall_hits::cpu4 12914 # number of overall hits -system.l2c.overall_hits::cpu5 13012 # number of overall hits -system.l2c.overall_hits::cpu6 13049 # number of overall hits -system.l2c.overall_hits::cpu7 13046 # number of overall hits -system.l2c.overall_hits::total 103778 # number of overall hits -system.l2c.ReadReq_misses::cpu0 811 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 850 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 841 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 797 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 822 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 866 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 868 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 801 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6656 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1904 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1786 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1883 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1815 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1890 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1852 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1884 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1828 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14842 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4339 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4322 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4349 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4270 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4225 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4246 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4116 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4276 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34143 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5150 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5172 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5190 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5067 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5047 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5112 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 4984 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5077 # number of demand (read+write) misses -system.l2c.demand_misses::total 40799 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5150 # number of overall misses -system.l2c.overall_misses::cpu1 5172 # number of overall misses -system.l2c.overall_misses::cpu2 5190 # number of overall misses -system.l2c.overall_misses::cpu3 5067 # number of overall misses -system.l2c.overall_misses::cpu4 5047 # number of overall misses -system.l2c.overall_misses::cpu5 5112 # number of overall misses -system.l2c.overall_misses::cpu6 4984 # number of overall misses -system.l2c.overall_misses::cpu7 5077 # number of overall misses -system.l2c.overall_misses::total 40799 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 67585481 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 72673967 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 72507473 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 67900486 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 70984967 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 72621982 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 74019971 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 71889473 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 570183800 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 54932462 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 51505961 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 54811454 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53694953 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 54685961 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 53053446 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 55065452 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 53902466 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 431652155 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 247942331 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 244706822 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 247942337 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 243863836 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 241149827 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 241354363 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234845330 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 242655342 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1944460188 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 315527812 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 317380789 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 320449810 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 311764322 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 312134794 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 313976345 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 308865301 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 314544815 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2514643988 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 315527812 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 317380789 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 320449810 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 311764322 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 312134794 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 313976345 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 308865301 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 314544815 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2514643988 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11826 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11622 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11810 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11476 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11708 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11816 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11805 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11792 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 93855 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 77421 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77421 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2247 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2119 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2235 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2185 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2252 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2188 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2275 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2226 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17727 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6435 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6412 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6366 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6253 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6308 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6228 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50722 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18261 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18034 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18176 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17865 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17961 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18033 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18123 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 144577 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18261 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18034 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18176 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17865 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17961 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18124 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18033 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18123 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 144577 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.068578 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.073137 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.071211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.069449 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.070208 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.073290 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.073528 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.067927 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.070918 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.847352 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.842850 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.842506 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.830664 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.839254 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.846435 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.828132 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.821204 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.837254 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.674281 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.674049 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.683161 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.668336 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.675676 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.673114 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.660886 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.675407 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.673140 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.282022 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.286792 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.285541 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.283627 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.280998 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.282057 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.276382 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.280141 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.282196 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.282022 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.286792 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.285541 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.283627 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.280998 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.282057 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.276382 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.280141 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.282196 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 83335.981504 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 85498.784706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 86215.782402 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 85195.089084 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 86356.407543 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 83859.101617 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 85276.464286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 89749.654182 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85664.633413 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28851.082983 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28838.723964 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29108.578864 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29583.996143 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28934.370899 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28646.569114 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29227.946921 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29487.125821 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29083.152877 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 57142.735884 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 56618.885238 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 57011.344447 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 57110.968618 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 57076.882130 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 56842.760951 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 57056.688533 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 56748.209074 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 56950.478517 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 61267.536311 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 61365.195089 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 61743.701349 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 61528.384054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 61845.610065 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 61419.472809 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 61971.368579 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 61954.858184 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61634.941739 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 61267.536311 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 61365.195089 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 61743.701349 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 61528.384054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 61845.610065 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 61419.472809 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 61971.368579 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 61954.858184 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61634.941739 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 618 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 740.977974 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.980396 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.585151 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 8.326366 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 7.791550 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.277354 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 7.805973 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 7.956689 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 7.749957 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.723611 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007793 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007407 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.008131 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007609 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007107 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.007623 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.007770 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.007568 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784621 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10624 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10791 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10648 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10876 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10598 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10892 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86047 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 76684 # number of Writeback hits +system.l2c.Writeback_hits::total 76684 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 327 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 379 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 347 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 352 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 359 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 389 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2869 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2022 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1993 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 2049 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2057 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1996 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2073 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 2040 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2058 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16288 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12740 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12617 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12949 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12848 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12644 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12949 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12638 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12950 # number of demand (read+write) hits +system.l2c.demand_hits::total 102335 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12740 # number of overall hits +system.l2c.overall_hits::cpu1 12617 # number of overall hits +system.l2c.overall_hits::cpu2 12949 # number of overall hits +system.l2c.overall_hits::cpu3 12848 # number of overall hits +system.l2c.overall_hits::cpu4 12644 # number of overall hits +system.l2c.overall_hits::cpu5 12949 # number of overall hits +system.l2c.overall_hits::cpu6 12638 # number of overall hits +system.l2c.overall_hits::cpu7 12950 # number of overall hits +system.l2c.overall_hits::total 102335 # number of overall hits +system.l2c.ReadReq_misses::cpu0 829 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 817 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 838 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 845 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 778 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 836 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 836 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 763 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6542 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1906 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1857 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1865 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1898 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1862 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1833 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1819 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14915 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4259 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4029 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4260 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4288 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4087 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4203 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4290 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4312 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 33728 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5088 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 4846 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5098 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5133 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 4865 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5039 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5126 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5075 # number of demand (read+write) misses +system.l2c.demand_misses::total 40270 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5088 # number of overall misses +system.l2c.overall_misses::cpu1 4846 # number of overall misses +system.l2c.overall_misses::cpu2 5098 # number of overall misses +system.l2c.overall_misses::cpu3 5133 # number of overall misses +system.l2c.overall_misses::cpu4 4865 # number of overall misses +system.l2c.overall_misses::cpu5 5039 # number of overall misses +system.l2c.overall_misses::cpu6 5126 # number of overall misses +system.l2c.overall_misses::cpu7 5075 # number of overall misses +system.l2c.overall_misses::total 40270 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 72627487 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 68308474 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 75006474 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 70533471 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 66613974 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 67813479 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 73978476 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 69040973 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 563922808 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54756455 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 53319972 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 53416959 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 57331458 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 53682456 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 54000963 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 51801955 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 51941959 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 430252177 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 241663349 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 231681341 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 241380832 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 244014828 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 232261321 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 242148860 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 245082818 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 243371325 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1921604674 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 314290836 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 299989815 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 316387306 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 314548299 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 298875295 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 309962339 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 319061294 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 312412298 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2485527482 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 314290836 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 299989815 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 316387306 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 314548299 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 298875295 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 309962339 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 319061294 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 312412298 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2485527482 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11547 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11441 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11738 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11636 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11426 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11712 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11434 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11655 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 92589 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 76684 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 76684 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2233 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2212 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2250 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2221 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2264 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2195 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2173 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17784 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6281 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6022 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6309 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6345 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6083 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6276 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6330 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6370 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50016 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17828 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18047 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17981 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17509 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17988 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17764 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18025 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 142605 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17828 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18047 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17981 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17509 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17988 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17764 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18025 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 142605 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.071794 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.071410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.071392 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.072619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.068090 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.071380 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.073115 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.065465 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.070656 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.853560 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.830501 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.843128 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.843556 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.838361 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.828180 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.835080 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.837092 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.838675 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.678077 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.669047 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.675226 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.675808 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.671872 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.669694 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.677725 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.676923 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.674344 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.285394 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.277501 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.282485 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.285468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.277857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.280131 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.288561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.281553 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.282388 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.285394 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.277501 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.282485 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.285468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.277857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.280131 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.288561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.281553 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.282388 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 87608.548854 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 83608.903305 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 89506.532220 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 83471.563314 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 85622.074550 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 81116.601675 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 88491 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 90486.203145 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 86200.368083 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28728.465373 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28712.962843 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28641.801072 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30206.247629 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28830.534909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28800.513600 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28260.750136 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28555.227598 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28846.944485 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 56741.805353 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 57503.435344 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 56662.167136 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 56906.443097 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 56829.293125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 57613.338092 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 57128.862005 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 56440.474258 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 56973.573114 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 61770.997642 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 61904.625464 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 62061.064339 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 61279.621859 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 61433.770812 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 61512.668982 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 62243.717128 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 61559.073498 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 61721.566476 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 61770.997642 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 61904.625464 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 62061.064339 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 61279.621859 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 61433.770812 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 61512.668982 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 62243.717128 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 61559.073498 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 61721.566476 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 205 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 94 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 34 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.574468 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.029412 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7498 # number of writebacks -system.l2c.writebacks::total 7498 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 34 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 98 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 804 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 843 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 831 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 788 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 815 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 856 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 857 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 798 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6592 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1902 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1786 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1883 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1815 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1889 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1852 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1884 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1828 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14839 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4334 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4318 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4340 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4265 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4222 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4242 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4116 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4272 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34109 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5138 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5161 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5171 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5053 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5037 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5098 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 4973 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5070 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40701 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5138 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5161 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5171 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5053 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5037 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5098 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 4973 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5070 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40701 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 57455481 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 61467468 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 61812473 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 57960486 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 60571467 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 61211482 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 62615971 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 61885973 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 484980801 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78471422 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73680432 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77692433 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74790419 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 77910437 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76253912 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 77720922 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75415430 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 611935407 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 195176331 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 192089822 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 194667337 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 191905836 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 189907827 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 189746863 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 184982830 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 190582842 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1529059688 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 252631812 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 253557290 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 256479810 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 249866322 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 250479294 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 250958345 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 247598801 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 252468815 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2014040489 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 252631812 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 253557290 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 256479810 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 249866322 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 250479294 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 250958345 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 247598801 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 252468815 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2014040489 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 426624598 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 414248119 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417125081 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 415481622 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 425535608 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 422832619 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413879620 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 421948093 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3357675360 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 234914484 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 229533990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 238126486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 230756493 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230060497 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 233129489 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 235046492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 235339481 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1866907412 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 661539082 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 643782109 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 655251567 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 646238115 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 655596105 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 655962108 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 648926112 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 657287574 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5224582772 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.067986 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.072535 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.070364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.068665 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069611 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072444 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.072596 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067673 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846462 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842850 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.842506 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.830664 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838810 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.846435 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.828132 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.821204 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.837085 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.673504 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.673425 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.681747 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.667554 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.675196 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672479 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.660886 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.674775 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.672470 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.281518 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.281518 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 71462.041045 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72915.145907 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 74383.240674 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 73553.916244 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74320.818405 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 71508.740654 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 73064.143524 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 77551.344612 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 73571.116657 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41257.319664 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41254.441209 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41259.921933 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41206.842424 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41244.275807 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41173.818575 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41253.143312 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41255.705689 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41238.318418 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45033.763498 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44485.831867 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44854.225115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44995.506682 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44980.536949 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44730.519331 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44942.378523 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44612.088483 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44828.628456 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency +system.l2c.writebacks::writebacks 7365 # number of writebacks +system.l2c.writebacks::total 7365 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 22 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 817 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 811 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 833 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 837 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 768 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 832 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 831 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 756 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6485 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1905 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1857 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1865 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1897 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1862 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1833 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1819 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14913 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4027 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4258 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4285 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4083 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4201 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4288 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4309 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 33706 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5072 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4838 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5091 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5122 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 4851 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5033 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5119 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5065 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40191 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5072 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4838 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5091 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5122 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 4851 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5033 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5119 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5065 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40191 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 62233988 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 58293474 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 64591474 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 59635471 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 57012474 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 57238479 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 63446976 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 59031473 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 481483809 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78461421 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76760937 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77303426 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78549924 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 76789922 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77341424 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 75742929 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75130926 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 616080909 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 189411849 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 182830341 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 189356832 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 191977328 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 182678822 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 190853860 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 192540318 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 191094825 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1510744175 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 251645837 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 241123815 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 253948306 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 251612799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 239691296 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 248092339 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 255987294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 250126298 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1992227984 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 251645837 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 241123815 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 253948306 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 251612799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 239691296 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 248092339 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 255987294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 250126298 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1992227984 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 411426099 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 414392619 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 419713103 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 412462117 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 406761621 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 421965569 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 407663587 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419790595 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3314175310 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 231152983 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 227958986 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 229754991 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 235704484 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 234071489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230948990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 231546487 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 229152485 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1850290895 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 642579082 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 642351605 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 649468094 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 648166601 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 640833110 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 652914559 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 639210074 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 648943080 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5164466205 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070754 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070885 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.070966 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071932 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067215 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.071038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.072678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.064865 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.070041 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.853112 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.830501 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.843128 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.843111 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838361 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.828180 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835080 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837092 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.838563 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.668715 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.674909 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.675335 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.671215 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.669375 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.677409 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.676452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.673904 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.284496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.277043 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.282097 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.284856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.277058 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.279798 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.288167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.280999 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.281834 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.284496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.277043 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.282097 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.284856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.277058 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.279798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.288167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.280999 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.281834 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 76173.791922 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 71878.512947 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 77540.785114 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 71249.069295 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74234.992188 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 68796.248798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 76350.151625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 78083.958995 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 74245.768543 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41187.097638 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41335.991922 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41449.558177 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41407.445440 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41240.559613 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41248.759467 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41321.837971 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41303.422760 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41311.668276 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44515.123149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45401.127638 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44470.838891 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44802.176896 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44741.323047 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45430.578434 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44902.126399 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44347.835925 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 44821.223966 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 49614.715497 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 49839.564903 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 49881.812218 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 49123.935767 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 49410.698000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 49293.133121 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 50007.285407 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 49383.276999 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49569.007589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 49614.715497 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 49839.564903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 49881.812218 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 49123.935767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 49410.698000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 49293.133121 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 50007.285407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 49383.276999 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49569.007589 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -656,114 +657,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 99935 # number of read accesses completed -system.cpu0.num_writes 53927 # number of write accesses completed +system.cpu0.num_reads 98761 # number of read accesses completed +system.cpu0.num_writes 53242 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22552 # number of replacements -system.cpu0.l1c.tagsinuse 390.299440 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13259 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22978 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.577030 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22316 # number of replacements +system.cpu0.l1c.tagsinuse 389.737995 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13032 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22724 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.573491 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 390.299440 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.762304 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.762304 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8650 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8650 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1121 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9771 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9771 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9771 # number of overall hits -system.cpu0.l1c.overall_hits::total 9771 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36111 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36111 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23070 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23070 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59181 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59181 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59181 # number of overall misses -system.cpu0.l1c.overall_misses::total 59181 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 4619304150 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 4619304150 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 3123415012 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 3123415012 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 7742719162 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 7742719162 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 7742719162 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 7742719162 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44761 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44761 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24191 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68952 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68952 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806751 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806751 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953660 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953660 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858293 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858293 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858293 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858293 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127919.585445 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 127919.585445 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 135388.600433 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 135388.600433 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 130831.164766 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 130831.164766 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 130831.164766 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 130831.164766 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1413270 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 389.737995 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.761207 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.761207 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8451 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8451 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1130 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1130 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9581 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9581 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9581 # number of overall hits +system.cpu0.l1c.overall_hits::total 9581 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35764 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35764 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 22786 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 22786 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58550 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58550 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58550 # number of overall misses +system.cpu0.l1c.overall_misses::total 58550 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 4595217343 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 4595217343 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 3140614125 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 3140614125 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 7735831468 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 7735831468 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 7735831468 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 7735831468 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44215 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44215 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 23916 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 23916 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68131 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68131 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68131 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68131 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808866 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808866 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952751 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952751 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859374 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859374 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859374 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859374 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 128487.231378 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 128487.231378 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 137830.866541 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 137830.866541 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 132123.509274 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 132123.509274 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 132123.509274 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 132123.509274 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1390817 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 64534 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 63512 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.899619 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.898492 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9856 # number of writebacks -system.cpu0.l1c.writebacks::total 9856 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36111 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36111 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23070 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23070 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59181 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59181 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4547088150 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4547088150 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3077287012 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3077287012 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7624375162 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 7624375162 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7624375162 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 7624375162 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1436864073 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1436864073 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 955697316 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 955697316 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2392561389 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2392561389 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806751 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806751 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953660 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953660 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858293 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858293 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125919.751599 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125919.751599 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 133389.120590 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 133389.120590 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9722 # number of writebacks +system.cpu0.l1c.writebacks::total 9722 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35764 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35764 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22786 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 22786 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58550 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58550 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58550 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58550 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4523701343 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4523701343 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3095050125 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3095050125 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7618751468 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 7618751468 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7618751468 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 7618751468 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1332951909 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1332951909 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 956448961 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 956448961 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2289400870 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2289400870 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808866 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808866 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952751 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952751 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859374 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859374 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859374 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859374 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 126487.566911 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 126487.566911 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 135831.217634 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 135831.217634 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 130123.850863 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 130123.850863 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 130123.850863 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 130123.850863 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -771,114 +772,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 97805 # number of read accesses completed -system.cpu1.num_writes 52541 # number of write accesses completed +system.cpu1.num_reads 96397 # number of read accesses completed +system.cpu1.num_writes 52047 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21861 # number of replacements -system.cpu1.l1c.tagsinuse 389.546383 # Cycle average of tags in use -system.cpu1.l1c.total_refs 12913 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22254 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.580255 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21248 # number of replacements +system.cpu1.l1c.tagsinuse 388.599667 # Cycle average of tags in use +system.cpu1.l1c.total_refs 12959 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 21596 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.600065 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 389.546383 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.760833 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.760833 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8526 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8526 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9571 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9571 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9571 # number of overall hits -system.cpu1.l1c.overall_hits::total 9571 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35398 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35398 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22650 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22650 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58048 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58048 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58048 # number of overall misses -system.cpu1.l1c.overall_misses::total 58048 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 4577570179 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 4577570179 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 3175338798 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 3175338798 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 7752908977 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 7752908977 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 7752908977 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 7752908977 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 43924 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 43924 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23695 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23695 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 67619 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 67619 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 67619 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 67619 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805892 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805892 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955898 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955898 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858457 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858457 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858457 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858457 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129317.198119 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 129317.198119 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140191.558411 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 140191.558411 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 133560.311759 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 133560.311759 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 133560.311759 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 133560.311759 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1404233 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 388.599667 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.758984 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.758984 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8521 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8521 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1037 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1037 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9558 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9558 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9558 # number of overall hits +system.cpu1.l1c.overall_hits::total 9558 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 34759 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 34759 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22425 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22425 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 57184 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 57184 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 57184 # number of overall misses +system.cpu1.l1c.overall_misses::total 57184 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 4505667082 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 4505667082 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 3159000290 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 3159000290 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 7664667372 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 7664667372 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 7664667372 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 7664667372 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 43280 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 43280 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23462 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23462 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 66742 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 66742 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 66742 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 66742 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803119 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.803119 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955801 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.955801 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.856792 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.856792 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.856792 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.856792 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129625.912195 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 129625.912195 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140869.578149 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 140869.578149 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 134035.173685 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 134035.173685 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 134035.173685 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 134035.173685 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1387894 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62944 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62397 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.309243 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.242960 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks -system.cpu1.l1c.writebacks::total 9603 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35398 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35398 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22650 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22650 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58048 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58048 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58048 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58048 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4506790179 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4506790179 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3130040798 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3130040798 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7636830977 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 7636830977 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7636830977 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 7636830977 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1394209419 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1394209419 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 928511940 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 928511940 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2322721359 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2322721359 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805892 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805892 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955898 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955898 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858457 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858457 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127317.650121 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127317.650121 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138191.646711 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138191.646711 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9378 # number of writebacks +system.cpu1.l1c.writebacks::total 9378 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 34759 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 34759 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22425 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22425 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 57184 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 57184 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 57184 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 57184 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4436169082 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4436169082 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3114154290 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3114154290 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7550323372 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 7550323372 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7550323372 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 7550323372 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1384263931 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1384263931 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 908274469 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 908274469 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2292538400 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2292538400 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803119 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803119 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955801 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955801 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856792 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.856792 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856792 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.856792 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127626.487586 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127626.487586 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138869.756522 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138869.756522 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132035.593383 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132035.593383 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132035.593383 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132035.593383 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -887,113 +888,113 @@ system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 54114 # number of write accesses completed +system.cpu2.num_writes 53454 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22990 # number of replacements -system.cpu2.l1c.tagsinuse 392.060782 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13456 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 23401 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.575018 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22874 # number of replacements +system.cpu2.l1c.tagsinuse 393.105668 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13406 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 23291 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.575587 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 392.060782 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.765744 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.765744 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8750 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8750 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1243 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1243 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits -system.cpu2.l1c.overall_hits::total 9993 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36203 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36203 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23173 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23173 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59376 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59376 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59376 # number of overall misses -system.cpu2.l1c.overall_misses::total 59376 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 4641358719 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 4641358719 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 3127191782 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 3127191782 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 7768550501 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 7768550501 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 7768550501 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 7768550501 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44953 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44953 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24416 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24416 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 69369 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 69369 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 69369 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 69369 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805352 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805352 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.949091 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.949091 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.855944 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.855944 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.855944 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.855944 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 128203.704638 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 128203.704638 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 134949.802874 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 134949.802874 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 130836.541717 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 130836.541717 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 130836.541717 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 130836.541717 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1392289 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 393.105668 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.767785 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.767785 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8773 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8773 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1158 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1158 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9931 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9931 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9931 # number of overall hits +system.cpu2.l1c.overall_hits::total 9931 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36255 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36255 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22757 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22757 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59012 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59012 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59012 # number of overall misses +system.cpu2.l1c.overall_misses::total 59012 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 4588921928 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 4588921928 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 3096881635 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 3096881635 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 7685803563 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 7685803563 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 7685803563 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 7685803563 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45028 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45028 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23915 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23915 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68943 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68943 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68943 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68943 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805166 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805166 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951579 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.951579 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.855953 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.855953 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.855953 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.855953 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 126573.491325 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 126573.491325 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 136084.793031 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 136084.793031 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 130241.367230 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 130241.367230 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 130241.367230 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 130241.367230 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1394100 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 64514 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 64388 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.581192 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.651550 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9991 # number of writebacks -system.cpu2.l1c.writebacks::total 9991 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36203 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23173 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23173 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59376 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59376 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59376 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59376 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4568956719 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4568956719 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3080855782 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3080855782 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7649812501 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 7649812501 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7649812501 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 7649812501 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1362583834 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1362583834 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971805765 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971805765 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2334389599 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334389599 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805352 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805352 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.949091 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.949091 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.855944 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.855944 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 126203.815126 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 126203.815126 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 132950.234411 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 132950.234411 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9909 # number of writebacks +system.cpu2.l1c.writebacks::total 9909 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36255 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36255 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22757 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22757 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59012 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59012 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59012 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59012 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4516419928 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4516419928 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3051379635 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3051379635 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7567799563 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 7567799563 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7567799563 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 7567799563 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1394051277 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1394051277 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 902954372 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 902954372 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2297005649 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2297005649 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805166 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805166 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951579 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951579 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855953 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.855953 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855953 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.855953 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 124573.711985 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 124573.711985 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 134085.320341 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 134085.320341 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128241.706145 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128241.706145 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128241.706145 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128241.706145 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1001,114 +1002,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98308 # number of read accesses completed -system.cpu3.num_writes 52892 # number of write accesses completed +system.cpu3.num_reads 98905 # number of read accesses completed +system.cpu3.num_writes 53947 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21879 # number of replacements -system.cpu3.l1c.tagsinuse 388.243829 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13269 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22290 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.595289 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22486 # number of replacements +system.cpu3.l1c.tagsinuse 391.587362 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13348 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22882 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.583341 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 388.243829 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.758289 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.758289 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8771 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8771 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1066 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1066 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9837 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9837 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9837 # number of overall hits -system.cpu3.l1c.overall_hits::total 9837 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35672 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35672 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22858 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22858 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58530 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58530 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58530 # number of overall misses -system.cpu3.l1c.overall_misses::total 58530 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 4705192371 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 4705192371 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 3092503889 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 3092503889 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 7797696260 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 7797696260 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 7797696260 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 7797696260 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44443 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44443 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 23924 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 23924 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68367 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68367 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68367 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68367 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.802646 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.802646 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955442 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955442 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.856115 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.856115 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.856115 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.856115 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 131901.557832 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 131901.557832 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135291.971695 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 135291.971695 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 133225.632325 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 133225.632325 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 133225.632325 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 133225.632325 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1411864 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 391.587362 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.764819 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.764819 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8745 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8745 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1178 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1178 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9923 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9923 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9923 # number of overall hits +system.cpu3.l1c.overall_hits::total 9923 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36044 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36044 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22870 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22870 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58914 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58914 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58914 # number of overall misses +system.cpu3.l1c.overall_misses::total 58914 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 4630744245 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 4630744245 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 3061222174 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 3061222174 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 7691966419 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 7691966419 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 7691966419 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 7691966419 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44789 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44789 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24048 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24048 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68837 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68837 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68837 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68837 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804751 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.804751 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951015 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.951015 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.855848 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.855848 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.855848 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.855848 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 128474.759877 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 128474.759877 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 133853.177700 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 133853.177700 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 130562.623808 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 130562.623808 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 130562.623808 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 130562.623808 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1375135 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63831 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 63801 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 22.118782 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.553502 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9578 # number of writebacks -system.cpu3.l1c.writebacks::total 9578 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35672 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35672 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22858 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22858 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58530 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58530 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58530 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58530 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4633860371 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4633860371 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3046797889 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3046797889 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7680658260 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 7680658260 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7680658260 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 7680658260 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1383140389 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1383140389 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919277948 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919277948 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2302418337 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2302418337 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.802646 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.802646 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955442 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955442 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.856115 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.856115 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 129901.894231 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 129901.894231 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133292.409178 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133292.409178 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9848 # number of writebacks +system.cpu3.l1c.writebacks::total 9848 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36044 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36044 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22870 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22870 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58914 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58914 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4558664245 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4558664245 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3015496174 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3015496174 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7574160419 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 7574160419 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7574160419 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 7574160419 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1332002539 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1332002539 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 965663255 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 965663255 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2297665794 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2297665794 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804751 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804751 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951015 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951015 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.855848 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.855848 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.855848 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.855848 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 126474.981828 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 126474.981828 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 131853.789856 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 131853.789856 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 128562.997233 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128562.997233 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128562.997233 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128562.997233 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1116,114 +1117,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99646 # number of read accesses completed -system.cpu4.num_writes 53184 # number of write accesses completed +system.cpu4.num_reads 96174 # number of read accesses completed +system.cpu4.num_writes 51853 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22486 # number of replacements -system.cpu4.l1c.tagsinuse 389.564427 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13323 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22871 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.582528 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 21569 # number of replacements +system.cpu4.l1c.tagsinuse 388.492426 # Cycle average of tags in use +system.cpu4.l1c.total_refs 12628 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 21966 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.574888 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 389.564427 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.760868 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.760868 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8662 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8662 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1144 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1144 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9806 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9806 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9806 # number of overall hits -system.cpu4.l1c.overall_hits::total 9806 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36129 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36129 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22914 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22914 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59043 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59043 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59043 # number of overall misses -system.cpu4.l1c.overall_misses::total 59043 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 4597368029 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 4597368029 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 3131496490 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 3131496490 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 7728864519 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 7728864519 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 7728864519 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 7728864519 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44791 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44791 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24058 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68849 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68849 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68849 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68849 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806613 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.806613 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952448 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952448 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857572 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857572 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857572 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857572 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 127248.692989 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 127248.692989 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 136663.022170 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 136663.022170 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 130902.300340 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 130902.300340 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 130902.300340 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 130902.300340 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1409065 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 388.492426 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.758774 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.758774 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8239 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8239 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 990 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 990 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9229 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9229 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9229 # number of overall hits +system.cpu4.l1c.overall_hits::total 9229 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 34929 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 34929 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22565 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22565 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 57494 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 57494 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 57494 # number of overall misses +system.cpu4.l1c.overall_misses::total 57494 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 4583503891 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 4583503891 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 3126262139 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 3126262139 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 7709766030 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 7709766030 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 7709766030 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 7709766030 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 43168 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 43168 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 23555 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 23555 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 66723 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 66723 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 66723 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 66723 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809141 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.809141 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957971 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.957971 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.861682 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.861682 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.861682 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.861682 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 131223.450170 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 131223.450170 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 138544.743585 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 138544.743585 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 134096.880196 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 134096.880196 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 134096.880196 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 134096.880196 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1393760 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 64552 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 62546 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.828371 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 22.283759 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9768 # number of writebacks -system.cpu4.l1c.writebacks::total 9768 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36129 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36129 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22914 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22914 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59043 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59043 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59043 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59043 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4525124029 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4525124029 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3085672490 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3085672490 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7610796519 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 7610796519 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7610796519 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 7610796519 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1426221714 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1426221714 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 886330386 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 886330386 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2312552100 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2312552100 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806613 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806613 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952448 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952448 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857572 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857572 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 125249.080489 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 125249.080489 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 134663.196736 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 134663.196736 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9434 # number of writebacks +system.cpu4.l1c.writebacks::total 9434 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 34929 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 34929 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22565 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22565 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 57494 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 57494 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 57494 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 57494 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4513651891 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4513651891 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3081144139 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3081144139 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7594796030 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 7594796030 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7594796030 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 7594796030 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1346430009 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1346430009 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 963144394 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 963144394 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2309574403 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2309574403 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809141 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809141 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957971 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957971 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861682 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.861682 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861682 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.861682 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 129223.621947 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 129223.621947 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 136545.275382 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 136545.275382 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 132097.193272 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 132097.193272 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 132097.193272 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 132097.193272 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1231,114 +1232,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99510 # number of read accesses completed -system.cpu5.num_writes 53712 # number of write accesses completed +system.cpu5.num_reads 98962 # number of read accesses completed +system.cpu5.num_writes 53362 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22704 # number of replacements -system.cpu5.l1c.tagsinuse 391.715809 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13238 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 23109 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.572850 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22485 # number of replacements +system.cpu5.l1c.tagsinuse 390.064411 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13538 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22892 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.591386 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 391.715809 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.765070 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.765070 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8676 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8676 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1153 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1153 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9829 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9829 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9829 # number of overall hits -system.cpu5.l1c.overall_hits::total 9829 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36073 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36073 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23060 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23060 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59133 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59133 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59133 # number of overall misses -system.cpu5.l1c.overall_misses::total 59133 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 4612203646 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 4612203646 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 3154708419 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 3154708419 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 7766912065 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 7766912065 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 7766912065 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 7766912065 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44749 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44749 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24213 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24213 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68962 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68962 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68962 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68962 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806119 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806119 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952381 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952381 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.857472 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.857472 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.857472 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.857472 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127857.501344 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 127857.501344 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136804.354683 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 136804.354683 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 131346.491215 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 131346.491215 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 131346.491215 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 131346.491215 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1402922 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 390.064411 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.761845 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.761845 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8808 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8808 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1142 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1142 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9950 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9950 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9950 # number of overall hits +system.cpu5.l1c.overall_hits::total 9950 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35846 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35846 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22890 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22890 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58736 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58736 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58736 # number of overall misses +system.cpu5.l1c.overall_misses::total 58736 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 4553672386 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 4553672386 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 3119643153 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 3119643153 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 7673315539 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 7673315539 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 7673315539 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 7673315539 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44654 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44654 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24032 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24032 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68686 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68686 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68686 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68686 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802750 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.802750 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952480 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952480 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.855138 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.855138 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.855138 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.855138 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127034.324220 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 127034.324220 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136288.473263 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 136288.473263 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 130640.757610 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 130640.757610 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 130640.757610 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 130640.757610 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1393328 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 64326 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 63640 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.809564 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.893903 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9873 # number of writebacks -system.cpu5.l1c.writebacks::total 9873 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36073 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36073 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23060 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59133 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59133 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59133 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59133 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4540061646 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4540061646 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3108604419 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3108604419 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7648666065 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 7648666065 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7648666065 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 7648666065 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1397826307 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1397826307 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 952355893 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 952355893 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2350182200 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2350182200 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806119 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806119 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952381 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952381 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.857472 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.857472 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125857.612231 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125857.612231 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134805.048526 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134805.048526 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9848 # number of writebacks +system.cpu5.l1c.writebacks::total 9848 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35846 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35846 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22890 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22890 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58736 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58736 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58736 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58736 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4481994386 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4481994386 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3073871153 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3073871153 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7555865539 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 7555865539 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7555865539 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 7555865539 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1395127827 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1395127827 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 940338919 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 940338919 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2335466746 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2335466746 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802750 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802750 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952480 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952480 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.855138 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.855138 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.855138 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.855138 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125034.714780 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125034.714780 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134288.822761 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134288.822761 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128641.132168 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128641.132168 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128641.132168 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128641.132168 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1346,114 +1347,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99341 # number of read accesses completed -system.cpu6.num_writes 53460 # number of write accesses completed +system.cpu6.num_reads 97085 # number of read accesses completed +system.cpu6.num_writes 52397 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 22728 # number of replacements -system.cpu6.l1c.tagsinuse 391.033952 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13418 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 23126 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.580213 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21752 # number of replacements +system.cpu6.l1c.tagsinuse 389.740766 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13001 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22153 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.586873 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 391.033952 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.763738 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.763738 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8762 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8762 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1095 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1095 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits -system.cpu6.l1c.overall_hits::total 9857 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35979 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35979 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23081 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23081 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 59060 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 59060 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 59060 # number of overall misses -system.cpu6.l1c.overall_misses::total 59060 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 4670056241 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 4670056241 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 3140122564 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 3140122564 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 7810178805 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 7810178805 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 7810178805 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 7810178805 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44741 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24176 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68917 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68917 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68917 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68917 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804162 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.804162 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954707 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954707 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.856973 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.856973 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.856973 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.856973 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129799.500848 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 129799.500848 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136047.942637 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 136047.942637 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 132241.429140 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 132241.429140 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 132241.429140 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 132241.429140 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1402385 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 389.740766 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.761212 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.761212 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8437 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8437 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1082 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1082 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9519 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9519 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9519 # number of overall hits +system.cpu6.l1c.overall_hits::total 9519 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35128 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35128 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 22626 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 22626 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 57754 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 57754 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 57754 # number of overall misses +system.cpu6.l1c.overall_misses::total 57754 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 4550980379 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 4550980379 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 3080862665 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 3080862665 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 7631843044 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 7631843044 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 7631843044 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 7631843044 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 43565 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 43565 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 23708 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 23708 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 67273 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 67273 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 67273 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 67273 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806335 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806335 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954361 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954361 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858502 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858502 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858502 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858502 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129554.212565 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 129554.212565 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136164.707195 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 136164.707195 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 132143.973474 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 132143.973474 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 132143.973474 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 132143.973474 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1372349 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 64109 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 62634 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.875010 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.910608 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9866 # number of writebacks -system.cpu6.l1c.writebacks::total 9866 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35979 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23081 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23081 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 59060 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 59060 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 59060 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 59060 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4598108241 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4598108241 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3093974564 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3093974564 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7692082805 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 7692082805 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7692082805 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 7692082805 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1335573448 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1335573448 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 977750934 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 977750934 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2313324382 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2313324382 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804162 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804162 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954707 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954707 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.856973 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.856973 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127799.778788 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127799.778788 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134048.549196 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134048.549196 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9668 # number of writebacks +system.cpu6.l1c.writebacks::total 9668 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35128 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35128 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22626 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 22626 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 57754 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 57754 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 57754 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 57754 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4480736379 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4480736379 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3035616665 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3035616665 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7516353044 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 7516353044 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7516353044 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 7516353044 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1387372518 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1387372518 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 999274904 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 999274904 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2386647422 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2386647422 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806335 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806335 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954361 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954361 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858502 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858502 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858502 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858502 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127554.554173 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127554.554173 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134164.972377 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134164.972377 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130144.285140 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130144.285140 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130144.285140 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130144.285140 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1461,114 +1462,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99191 # number of read accesses completed -system.cpu7.num_writes 53936 # number of write accesses completed +system.cpu7.num_reads 98863 # number of read accesses completed +system.cpu7.num_writes 52856 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22510 # number of replacements -system.cpu7.l1c.tagsinuse 390.052988 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13451 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22924 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.586765 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22616 # number of replacements +system.cpu7.l1c.tagsinuse 391.615445 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13178 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 23003 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.572882 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 390.052988 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.761822 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.761822 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8796 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8796 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1169 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1169 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9965 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9965 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9965 # number of overall hits -system.cpu7.l1c.overall_hits::total 9965 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35920 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35920 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23167 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23167 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59087 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59087 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59087 # number of overall misses -system.cpu7.l1c.overall_misses::total 59087 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 4583534857 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 4583534857 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 3157115869 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 3157115869 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 7740650726 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 7740650726 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 7740650726 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 7740650726 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44716 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24336 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24336 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69052 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69052 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69052 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69052 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803292 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.803292 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951964 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.951964 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.855688 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.855688 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.855688 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.855688 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 127603.977088 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 127603.977088 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136276.422023 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 136276.422023 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 131004.294109 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 131004.294109 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 131004.294109 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 131004.294109 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1403287 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 391.615445 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.764874 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.764874 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8679 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8679 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1098 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1098 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9777 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9777 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9777 # number of overall hits +system.cpu7.l1c.overall_hits::total 9777 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35968 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35968 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22753 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22753 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58721 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58721 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58721 # number of overall misses +system.cpu7.l1c.overall_misses::total 58721 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 4555865271 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 4555865271 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 3104187449 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 3104187449 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 7660052720 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 7660052720 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 7660052720 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 7660052720 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44647 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44647 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 23851 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68498 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68498 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68498 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68498 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805608 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805608 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953964 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953964 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857266 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857266 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857266 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857266 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 126664.403664 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 126664.403664 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136429.809212 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 136429.809212 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 130448.267570 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 130448.267570 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 130448.267570 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 130448.267570 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1381368 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 64246 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 63977 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.842403 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.591634 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9883 # number of writebacks -system.cpu7.l1c.writebacks::total 9883 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35920 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35920 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23167 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23167 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59087 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59087 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59087 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59087 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4511708857 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4511708857 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3110789869 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3110789869 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7622498726 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 7622498726 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7622498726 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 7622498726 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1423430289 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1423430289 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 942416285 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 942416285 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2365846574 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2365846574 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803292 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803292 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951964 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951964 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.855688 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.855688 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 125604.366843 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 125604.366843 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134276.767341 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134276.767341 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9880 # number of writebacks +system.cpu7.l1c.writebacks::total 9880 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35968 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22753 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22753 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58721 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58721 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58721 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58721 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4483949271 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4483949271 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3058683449 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3058683449 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7542632720 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 7542632720 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7542632720 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 7542632720 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1380003854 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1380003854 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 891969960 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 891969960 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2271973814 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2271973814 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805608 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805608 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857266 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857266 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 124664.959714 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 124664.959714 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134429.897112 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134429.897112 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |